DE102013203905B4 - Processor-controlled storage device and method - Google Patents

Abstract

Processor-controlled storage device, in particular data logger,
with a hardware interface (2) which can be coupled to a data source (3);
with a first memory (4);
a reconfigurable logic (15) coupled to the hardware interface (2) and the first memory (4) and being partitionable into first and second logic regions (5, 6);
with a computing device (7), which is designed
To configure the first logic area (5) in such a way that it is designed to sample signal curves received by the data source (3) and to store the sampled signal values obtained therefrom in the first memory (4), and
To configure the second logic area (6) in such a way that it is designed to read the sampled signal values stored in the first memory (4) and / or from the signal progressions received from the data source (3) from the data source (3) Extract data.

Description

FIELD OF THE INVENTION

The present invention relates to a processor-controlled memory device and a corresponding method for operating such a memory device.

TECHNICAL BACKGROUND

A datalogger refers to a processor-controlled storage device, which receives data in a certain rhythm via an interface and stores it on a storage medium. For this purpose, a data logger usually consists of a programmable microprocessor, a storage medium, at least one interface and one or more channels for connecting the data source, such as sensors. The data is recorded externally or internally via a manufacturer-specific interface. Although basically expandable to any processor-controlled storage devices, the present invention and the problem underlying it is explained below with reference to a designed as a data logger processor-controlled storage device.

In modern vehicle development, a variety of different systems for data acquisition are used, for example, to detect the behavior of the vehicle under predetermined environmental conditions or in given driving situations. In networked systems, it is also necessary that these systems z. B. can communicate with each other via a bus system. Due to the ever-increasing number of electronic units in such systems, communication between the units is becoming increasingly complex.

To z. As in the development or the test of such electronic systems problems and errors as early as possible to identify, it is necessary to be able to log and analyze the data communication between the individual electronic units. Usually, data loggers are used for this purpose.

Errors in the data communication between the electronic units of an electronic system can occur in particular in the startup phase, for. B. during the synchronization of the individual electronic units on the data bus. If a system for data acquisition has a relatively long so-called start-up time, first data packets may already have been transmitted between the individual electronic units of the electronic system before the system for data acquisition is ready for operation. Problems, eg. B. during the synchronization of the individual electronic units on the data bus, can be difficult to detect during this start-up time and thus difficult to analyze.

An alternative solution is to wait with data analysis and saving the data until the datalogger is fully configured and ready for use. This compromise solution is usually unacceptable for highly dynamic systems.

The publication US 2004/0 266 480 A1 relates to a way to integrate a sensor in mobile communication devices. The US 2004/0 266 480 A1 provides a sensor card, which is coupled via a sensor interface with a memory in which the sensor data are stored.

A host process can then access the stored sensor data via a digital interface.

The publication US 2014/0 019 672 A1 relates to a storage system with multiple logical areas and multiple parallel processing units accessing the memory. Furthermore, the accesses to the memory areas are logged.

The publication US 2007/0 123 282 A1 discloses a modular system architecture for a sensor network.

The publication DE 20 2008 015 405 U1 shows a data carrier with an FPGA, which is designed to transfer firmware from a computer to a sensor.

The US 2010/0 057 543 A1 shows a system for monitoring the movement of a patient in a bed.

SUMMARY OF THE INVENTION

Against this background, it is an object of the present invention to provide an improved possibility for dynamic data acquisition.

This object is achieved by a storage device having the features of claim 1 and / or by a method having the features of claim 10.

• – Ein prozessorgesteuertes Speichergerät, insbesondere Datenlogger, mit einer Hardwareschnittstelle, welche mit einer Datenquelle koppelbar ist; mit einem ersten Speicher; mit einer rekonfigurierbaren Logik, welche mit der Hardwareschnittstelle und dem ersten Speicher gekoppelt ist und welche in einen ersten und einen zweiten Logikbereich partitionierbar ist; mit einer Recheneinrichtung, welche dazu ausgebildet ist, den ersten Logikbereich derart zu konfigurieren, dass dieser dazu ausgebildet ist, von der Datenquelle empfangene Signalverläufe zu sampeln und die daraus gewonnenen gesampelten Signalwerte in dem ersten Speicher zu speichern, und den zweiten Logikbereich derart zu konfigurieren, dass dieser dazu ausgebildet ist, aus den in dem ersten Speicher gespeicherten gesampelten Signalwerten und/oder aus den von der Datenquelle empfangenen Signalverläufen die von der Datenquelle übertragenen Daten zu extrahieren.
• – Ein Verfahren zum Erfassen von Daten mindestens einer Datenquelle mittels eines prozessorgesteuerten Speichergerätes, mit den Schritten: Koppeln einer Hardwareschnittstelle des Speichergeräts mit mindestens einer Datenquelle, Konfigurieren eines ersten Logikbereichs einer rekonfigurierbaren Logik des Speichergeräts derart, dass dieser erste Logikbereich von der Datenquelle empfangene Signalverläufe sampelt und die gesampelten Signalwerte in einem ersten Speicher speichert, und Konfigurieren eines zweiten Logikbereichs der rekonfigurierbaren Logik des Speichergeräts derart, dass dieser zweite Logikbereich aus den in dem ersten Speicher gespeicherten gesampelten Signalwerten und/oder aus den von der Datenquelle empfangene Signalverläufen die von der Datenquelle übertragenen Daten extrahiert.

Accordingly, it is provided:

• - A processor-controlled storage device, in particular data logger, with a hardware interface, which can be coupled to a data source; with a first memory; with a reconfigurable logic coupled to the hardware interface and the first memory and being partitionable into first and second logic regions; with a computing device that is configured to configure the first logic area such that it is configured to sample signal curves received by the data source and to store the sampled signal values obtained therefrom in the first memory, and to configure the second logic area in such a way that in that it is designed to extract the data transmitted by the data source from the sampled signal values stored in the first memory and / or from the signal progressions received from the data source.
• A method for capturing data from at least one data source by means of a processor-controlled memory device, comprising the steps of: coupling a hardware interface of the memory device to at least one data source, configuring a first logic region of a reconfigurable logic of the memory device such that said first logic region will sample waveforms received from the data source and storing the sampled signal values in a first memory, and configuring a second logic portion of the reconfigurable logic of the memory device such that the second logic portion transfers the sampled signal values stored in the first memory and / or the waveforms received from the data source to those transmitted from the data source Extracted data.

The idea underlying the present invention is to minimize the start-up time of a memory device in order to be able to analyze the data communication between the individual electronic units of the electrical system even in the start-up phase of an electrical system. To this end, the present invention provides that a memory device is equipped with reconfigurable logic, which makes it possible to analyze the data provided by a data source, in particular data transmitted by means of different data transmission protocols. The reconfigurable logic can access the respective data sources via a hardware interface that performs only level adjustments and analog-to-digital conversion.

In particular, the present invention contemplates subdividing the reconfigurable logic into two logic areas. In addition to a first logic area provided specifically for the startup time, a second logic area is provided which is configured during the start of the memory device for the particular application or the respective data transmission protocol of the corresponding data source. The thus configured second logic area then forms an interface to the respective data source and can forward the data transmitted by this data source.

The logic, ie the programmable logic circuit, which is required for analyzing the data transmitted by means of a data transmission protocol is typically very complex, so that the configuration of the second logic area typically takes a very long time without any further precautions. Therefore, data may already have been transferred from the data source in the time between the startup of the memory device and the complete configuration of the second logic area.

The present invention now provides a first logic area which has a less complex configuration and therefore also is ready much earlier than the second logic area. This first logic area is merely configured to sample the raw data (s) transmitted from the data source and to temporarily store the sampled signal values in memory of the memory device. Since this first logic area, which is provided only for storing the raw data, is not very complex, the first logic area is very quickly ready for operation when the memory device is started.

While the first logic area can thus already sample signal curves after its configuration, the second logic area is completely configured in this time. After the configuration of the second logic area has ended, this second logic area can then take on its actual function and analyze the contents of the signal values buffered in the memory. Once the signal values stored in the memory have been analyzed, the second logic area may receive the data transmitted from the data source, e.g. In real time, analyze directly.

This makes it possible to provide a storage device which has a very short start-up time and yet can process largely completely complex data or data transmission protocols without the loss of data.

Advantageous embodiments and further developments emerge from the dependent claims and from the description with reference to the figures.

In one embodiment, the computing device is configured to configure the first logic area before the second logic area each time the memory device is put into operation again. This will ensure that the first Logic area is timely after switching on the storage device is ready.

In a further embodiment, the computing device is designed to commission and configure the first logic area in time prior to the configuration of the second logic area. This ensures that the first logic area begins to sample signal values soon after the memory device is turned on.

In one embodiment, a second memory is provided, wherein the second logic area in the configured state is configured to store the extracted data in the second memory. This makes it possible to provide the extracted data for later processing.

In one embodiment, the reconfigurable logic is implemented as a RAM-based reconfigurable logic, in particular as an FPGA. The short access cycles of a RAM memory allow fast configuration of the first logic area and the second logic area.

In one embodiment, a communication interface is provided, via which the storage device can be coupled to a device-external control and evaluation device. The computing device is designed to transmit the extracted data via the communication interface to the device-external control and evaluation device. This allows the transmission of the extracted data z. To a computer for convenient evaluation by a user.

In one embodiment, a non-volatile third memory is provided in which configuration data for the configuration of the first logic area and / or the second logic area are stored. This makes it possible to permanently store a configuration for the first logic area and the second logic area and to quickly provide this configuration data again even after interrupting the power supply of the memory device.

In one embodiment, the data source has a CAN bus and / or a LIN bus and / or a FlexRay bus and / or a MOST bus. This allows the use of a storage device according to the invention with a large number, especially in the automotive sector widespread bus systems.

In one embodiment, the data source has at least one sensor. This makes it possible to adapt the storage device individually to different measurement tasks.

In one embodiment, the computing device is embodied as a component of an FPGA in which the reconfigurable logic is arranged. This allows a compact construction of the storage device.

In a further embodiment, the computing device has more than one computing core. This allows a very fast processing of the extracted data. In a further embodiment, the computing device has at least one ARM calculation kernel and / or one MIPS calculation kernel and / or one x86 calculation kernel or the like. This allows the use of known processor architectures in the memory device. This simplifies the development of software for the computing device.

In a further embodiment, the computing device and the reconfigurable logic are operated at the lowest possible clock rate at which the desired recording of the data can still take place. This makes it possible, depending on the complexity of the respective measurement task, to reduce the clock rate and thus the power consumption of the computing device and the reconfigurable logic. In particular, in mobile or battery-powered applications so the energy needs of the storage device can be reduced.

In one embodiment, the storage device has an output device via which information of the storage device can be displayed to a user. The output device can, for. As a monitor, display, lights, speakers or the like.

In a further embodiment, the storage device has an input device via which a user can communicate control commands to the storage device. The input device may, for. As a touchpad, keyboard, microphone or the like.

The above embodiments and developments can, if appropriate, combine with each other as desired. Further possible refinements, developments and implementations of the invention also include combinations of features of the invention which have not been explicitly mentioned above or described below with regard to the exemplary embodiments. In particular, the person skilled in the art will also add individual aspects as improvements or additions to the respective basic form of the present invention.

CONTENTS OF THE DRAWINGS

The present invention will be described below with reference to the schematic figures of Drawings specified embodiments explained in more detail. It shows:

1 a block diagram of an embodiment of a processor-controlled storage device according to the invention;

2 a flowchart of an embodiment of a method according to the invention;

3 a block diagram of another embodiment of a storage device according to the invention;

4 a block diagram of a motor vehicle with a storage device according to the invention.

The accompanying drawings are intended to provide further understanding of the embodiments of the invention. They illustrate embodiments and, together with the description, serve to explain principles and concepts of the invention. Other embodiments and many of the stated advantages will become apparent with reference to the drawings. The elements of the drawings are not necessarily shown to scale to each other.

In the figures of the drawing are the same, functionally identical and same-acting elements, features and components - unless otherwise stated - each provided with the same reference numerals.

DESCRIPTION OF EMBODIMENTS

In the context of the present description of the invention, a hardware interface is to be understood as the hardware itself, which serves to connect the processor-controlled storage device with a data source, for. B. a data bus to couple. The hardware interface can be z. Example, an interface for levels of 0 volts-5 volts or from -5 volts + 5 volts or the like. The hardware interface can also be an optical interface, z. As a MOST bus interface.

In the context of this patent application, a data bus designates a system via which data can be transmitted in electronic or optical form in accordance with a predetermined data transmission protocol. A corresponding data bus can, for. For example, any fieldbus may be an Ethernet network or the like.

Under a reconfigurable logic is to be understood in the context of this application, a logic device whose function is not in the production, such. B. in an ASIC is set. Rather, the function of reconfigurable logic may be configured during operation of the reconfigurable logic. Possible reconfigurable logic modules can, for. As CPLDs, FPGAs or the like.

Under a computing device is in the context of this patent application each computing device, eg. As any processor understood that can be coupled with the reconfigurable logic devices. In particular, a computing device is also understood to mean a processor core which is arranged together with the reconfigurable logic components in an FPGA. The computing device can, for. An ARM processor, an x68 processor, an MIPS processor or the like. The computing device may also have more than one processor.

A communication interface may be any interface that allows the processor-controlled storage device to communicate with a PC. For example, the communication interface can be designed as an Ethernet interface, as a WLAN interface, as a USB or Firewire interface or the like.

The configuration data identifies the data needed by the computing device to configure the reconfigurable logic of the processor-controlled storage device. By way of example, the configuration data can have a memory image which the computing device can import into a RAM-based reconfigurable logic. The configuration data can z. B. have been described in a hardware description language. This hardware description language may e.g. B. VHDL or VERILOG. The configuration data thus described may then have been translated into a form that can be loaded by the computing device directly into a RAM-based reconfigurable logic device.

1 shows a block diagram of an embodiment of a storage device according to the invention. This with reference number 1 designated processor-controlled storage device 1 has a hardware interface 2 on that with a data source 3 can be coupled. The hardware interface 2 is with a first logic area 5 a reconfigurable logic 15 coupled.

The first logic area 5 is further with a first memory 4 coupled to signal values from the hardware interface 2 to sample and in the first memory 4 enroll.

The hardware interface 2 is also with a second logic area 6 the reconfigurable logic 15 coupled. The second logic area 6 is in addition to the first memory 4 coupled to from the data source 3 transmitted data and / or in the in the first memory 4 extracted data stored in the stored signal values.

Finally, the two are logic areas 5 . 6 with a computing device 7 coupled, which is adapted to the first logic area 5 and the second logic area 6 the reconfigurable logic 15 to configure.

The computing device 7 can in one embodiment, for. B. as a processor core 7 which is in the reconfigurable logic 15 is firmly integrated and with the reconfigurable part of the reconfigurable logic 15 is firmly coupled, be formed. The processor core 7 For example, an ARM processor 7 be with a single processor. The processor core 7 for example, an ARM processor 7 be with multiple cores. In other embodiments, other processor architectures are possible.

The reconfigurable logic 15 can z. B. be designed as FPGA. In other embodiments, the reconfigurable logic 15 also as any other reconfigurable logic device 15 be educated.

In one embodiment, the hardware interface 2 as an integral part of reconfigurable logic 15 be educated. For example, the reconfigurable logic 15 as an FPGA with integrated hardware interfaces, such as As A / D converters, optocouplers or the like may be formed.

In one embodiment, the processor-controlled storage device 1 an output device, e.g. Example, a display, via which a user status information of the processor-controlled storage device 1 can be displayed. About the output device can be a user z. B. also curves of the collected data are displayed.

In a further embodiment, the processor-controlled storage device 1 an input device via which a user the processor-controlled storage device 1 Control commands z. B. to start or stop the data recording.

2 shows a flowchart of an embodiment of a method according to the invention.

In a first step S1 becomes a hardware interface 2 the processor-controlled storage device 1 with at least one data source 3 coupled to read in the signals coming from the data source 3 be transmitted.

In a second step S2, a first logic area is created 5 a reconfigurable logic 15 the processor-controlled storage device 1 configured such that this first logic area 5 from the data source 3 Received waveforms and the sampled signal values in a first memory 4 stores.

Finally, in a third step S3, a second logic area is created 6 the reconfigurable logic 15 the processor-controlled storage device 1 configured such that this second logic area 6 from those in the first store 4 stored sampled signal values and / or from the data source 3 received waveforms from the data source 3 extracted data extracted.

In one embodiment, each time the processor-controlled storage device is powered up, it will be 1 the first logic area 5 before the second logic area 6 configured.

In one embodiment, the first logic area becomes 5 time before configuring the second logic area 6 put into operation and configured.

In one embodiment, the second logic area stores 6 in the configured state, the extracted data in a second memory 8th ,

In one embodiment, via a communication interface 9 the extracted data to an external control and evaluation device 10 transfer.

In one embodiment, configuration data becomes 12 to configure the first logic area 5 and the second logic area 6 from a non-volatile third memory 11 read.

In another embodiment, the complexity of the data transmission protocol becomes the data source 3 analyzed. Depending on the complexity being analyzed, the computing device and the reconfigurable logic are operated at the lowest possible clock rate at which the desired recording of the data can still take place.

In a further embodiment, information about the extracted data on an output device, e.g. As a display.

In yet another embodiment, user commands are used to control the operation of the controlled storage device 1 queried via an input device.

3 shows a block diagram of another embodiment of a storage device according to the invention 1 , The storage device 1 of the 3 is different from the one in 1 to the effect that a second memory 8th and a third memory 11 are provided. The second memory 8th is between the second logic area 6 and the controller 7 and serves to temporarily store the data extracted from the second logic area. The third memory 11 is designed as a non-volatile memory containing the configuration data 12 for the configuration of the first logic area 5 and the second logic area 6 stores.

At a start of the processor-controlled storage device 1 reads the calculator 7 the configuration data 12 from the third memory 11 and transmits them to the, in 3 for the sake of clarity, not explicitly drawn, reconfigurable logic 15 , By configuring the reconfigurable logic 15 form the two logic areas 5 and 6 that can be operated independently of each other.

The processor-controlled storage device 1 in 3 also has a communication interface 9 on which the processor-controlled storage device 1 with a computer 10 coupled. For example, the computer 10 via the communication interface 9 and the computing device 7 in the second memory 8th query stored data and display a user for evaluation.

In one embodiment, the computing device 7 a program module, which is adapted to predetermined analyzes of the data stored in the second memory 8th are stored to perform. In such an embodiment, the computing device 7 z. B. also be adapted to the results of these analyzes to the computer 10 to convey.

The computing device 7 may also include a program module that performs monitoring tasks related to the extracted data. For example, the program module may be designed to monitor the extracted data for the occurrence or exceeding of a predetermined maximum value. If this predetermined maximum value is exceeded, the computing device 7 z. B. via the communication interface 9 or issue a warning via the output device.

In one embodiment, additional functions are described above in connection with program modules of the computing device 7 were not designed as program modules. Rather, the additional functions are directly in the first logic area 5 or the second logic area 6 designed as a configured logic.

4 shows a block diagram of a motor vehicle 20 with an embodiment of a storage device according to the invention 1 , The car 20 has two controllers 21 and 22 on that over a CAN bus 3 coupled together. On the CAN bus 3 is a storage device 1 connected, which as a data logger 1 for the CAN bus 3 of the motor vehicle 20 serves.

The controllers 21 and 22 can z. B. a central gateway 21 of the motor vehicle 20 and an engine control unit 22 of the motor vehicle 20 be. Over the CAN bus 3 can the engine control unit z. B. data on the current state of the engine of the motor vehicle 20 to the central gateway 21 to transfer.

The hardware interface 2 of the storage device 1 is as a CAN-compatible hardware interface 2 educated.

In one embodiment, the storage device is in the 1 integrated a display, via which a user the transmitted data, eg. As the engine speed, are displayed as curves on the display.

In a further embodiment, the storage device 1 several buttons on which a user data acquisition by the processor-controlled storage device 1 control, z. B. can start and stop.

In a further embodiment, the storage device 1 instead of a CAN-compatible hardware interface 2 or in addition to a CAN-compatible hardware interface 2 a FlexRay-compatible and / or a LIN-compatible and / or an optical MOST-compatible hardware interface 2 on.

In one embodiment, the function is the hardware interface 2 as well as the function of the first logic area 5 and the second logic area 6 the processor-controlled storage device 1 ,

In another embodiment, the hardware interface is 2 of the storage device 1 designed to work with multiple bus systems 3 and sensors 3 to be coupled at the same time.

In such an embodiment, the first logic area is also included 5 and the second logic area 6 designed to sample or evaluate the different data transmission protocols of the different bus systems and sensors.

In one possible embodiment, the storage device 1 z. B. used to analyze the immobilizer of a vehicle. In such a case, the storage device 1 together with the other control units 21 . 22 of the vehicle over the ignition of the vehicle 20 be turned on. This is z. B. on longer test drives necessary because the storage device 1 the battery of the vehicle 20 could empty if it was permanently supplied by this.

But there the controllers 21 . 22 in a vehicle 20 usually a very short start-up time in the range of a few milliseconds, z. B. 20 ms, also begins the data transfer on the vehicle bus 3 also already after this short start-up time of 20 ms.

The control device 7 the processor-controlled storage device 1 configures the first logic area as soon as possible when the ignition is switched on 5 , This happens in particular within the start-up time of the individual control units 21 . 22 , Start the controllers 21 . 22 now with the data transfer, which is sampling in the first logic area 5 configured logic the waveforms on the vehicle bus 3 transmitted data and stores them in the memory 4 ,

The control device 7 of the storage device 1 configured after the configuration of the first logic area 5 the second logic area 6 , The configuration of the second logic area 6 takes longer than the startup time of each ECU 21 . 22 because the second logic area 6 has a more complex logic than the first logic area 5 , After the second logic area 6 is configured, the second logic area begins 6 with that, the sampled signal values from the memory 4 read out and according to the on the vehicle bus 3 to analyze the transmission protocol used. This allows the second logic area 6 on the vehicle bus 3 extract transmitted data from the sampled waveforms and the computing device 7 provide.

Has the second logic area 6 all in the store 4 stored signal values, the second logic area 6 seamlessly transition the waveforms directly from the hardware interface 2 interrogate and on the vehicle bus 3 to extract transferred data from them.

In this way, the present invention makes it possible to consistently log data that can be retrieved using complex data transmission protocols on z. B. are transmitted to a vehicle bus.

In other embodiments, the processor-controlled storage device 1 not only in a motor vehicle 20 be used. The storage device 1 can z. B. in an aircraft and spacecraft, a rail vehicle, a watercraft or the like.

In other embodiments, the processor-controlled storage device 1 z. B. also be used in automation systems.

Although the present invention has been described above with reference to preferred embodiments, it is not limited thereto, but modifiable in a variety of ways. In particular, the invention can be varied or modified in many ways without deviating from the gist of the invention.

The term data logger is to be understood in the description and claims as a processor-controlled memory unit, although a data logger per se, of course, represents the preferred embodiment of such a processor-controlled memory unit.

In particular, the data logger or the storage device according to the invention need not exclusively have the elements designated therein. Rather, the data logger or the storage device may also comprise further elements and functional units.

Moreover, the present invention is not limited to the protocols and standards made above, which are intended to be illustrative only.

Finally, the figures given are only for understanding and are not intended to limit the invention to that effect.

LIST OF REFERENCE NUMBERS

1

processor-controlled storage device

2

Hardware interface

3

Data Source

4

Storage

5

logic area

6

logic area

7

computing device

8th

Storage

9

Communication Interface

10

Control and evaluation device

11

Storage

12

configuration data

15

reconfigurable logic

20

motor vehicle

21

control unit

22

control unit

Claims (15)

Processor-controlled storage device, in particular datalogger, with a hardware interface ( 2 ) connected to a data source ( 3 ) can be coupled; with a first memory ( 4 ); with a reconfigurable logic ( 15 ), which communicate with the hardware interface ( 2 ) and the first memory ( 4 ) and which in a first and a second logic area ( 5 . 6 ) is partitionable; with a computing device ( 7 ), which is designed to - the first logic area ( 5 ) in such a way that it is designed to be accessible from the data source ( 3 ) to sample received waveforms and the sampled signal values obtained therefrom in the first memory ( 4 ), and - the second logic area ( 6 ) in such a way that it is designed to be composed of those in the first memory ( 4 stored sampled signal values and / or from the data source ( 3 ) received signal traces from the data source ( 3 ) to extract transferred data. Storage device according to claim 1, characterized in that the computing device ( 7 ) is adapted to each time the storage device is restarted ( 1 ) the first logic area ( 5 ) before the second logic area ( 6 ). Storage device according to claim 1 or 2, characterized in that the computing device ( 7 ) is adapted to the first logic area ( 5 ) before the configuration of the second logic area ( 6 ) to commission and configure. Storage device according to one of the preceding claims, characterized in that a second memory ( 8th ) and that the second logic area ( 6 ) is configured in the configured state, the extracted data in the second memory ( 8th ) save. Storage device according to one of the preceding claims, characterized in that the reconfigurable logic ( 15 ) as a RAM-based reconfigurable logic ( 15 ), in particular as an FPGA ( 15 ), is trained. Storage device according to one of the preceding claims, characterized in that a communication interface ( 9 ) through which the storage device ( 1 ) with a device-external control and evaluation device ( 10 ) and that the computing device ( 7 ) is adapted to the extracted data via the communication interface ( 9 ) to the device-external control and evaluation device ( 10 ) transferred to. Storage device according to one of the preceding claims, characterized in that a non-volatile third memory ( 11 ) configured and configured to store configuration data ( 12 ) for the configuration of the first logic area ( 5 ) and / or the second logic area ( 6 ) save. Storage device according to one of the preceding claims, characterized in that the data source ( 3 ) at least one data bus ( 3 ), in particular a CAN bus and / or a LIN bus and / or a FlexRay bus and / or a MOST bus. Storage device according to one of the preceding claims, characterized in that the data source ( 3 ) has at least one sensor. Method for collecting data from at least one data source ( 3 ) by means of a processor-controlled storage device ( 1 ), with the steps: coupling (S1) a hardware interface ( 2 ) of the storage device ( 1 ) with at least one data source ( 3 ); Configure (S2) a first logic area ( 5 ) a reconfigurable logic ( 15 ) of the storage device ( 1 ) such that this first logic area ( 5 ) from the data source ( 3 ) and the sampled signal values in a first memory ( 4 ) stores; Configure (S3) a second logic area ( 6 ) of the reconfigurable logic ( 15 ) of the storage device ( 1 ) such that this second logic area ( 6 ) from those in the first memory ( 4 stored sampled signal values and / or from the data source ( 3 ) received signal traces from the data source ( 3 ) transmitted data extracted. Method according to claim 10, characterized in that each time the storage device is restarted ( 1 ) the first logic area ( 5 ) before the second logic area ( 6 ) is configured. Method according to Claim 11, characterized in that the first logic area ( 5 ) before configuring the second logic area ( 6 ) is commissioned and configured. Method according to one of the preceding method-related claims, characterized in that the second logic area ( 6 ) in the configured state, the extracted data in a second memory ( 8th ) stores. Method according to one of the preceding method-related claims, characterized in that via a communication interface ( 9 ) the extracted data to an external control and evaluation device ( 10 ) be transmitted. Method according to one of the preceding method-related claims, characterized in that configuration data ( 12 ) for configuring the first logic area ( 5 ) and the second logic area ( 6 ) from a non-volatile third memory ( 11 ) to be read.

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