DE10236439B3 - Memory arrangement comprises a substrate, memory regions formed in and/or on the substrate with electrical resistances that can be adjusted by thermal treatment and structure arranged between the memory regions to remove heat - Google Patents

Abstract

Memory arrangement comprises: (a) a substrate; (b) a number of memory regions formed in and/or on the substrate with electrical resistances that can be adjusted by thermal treatment; and (c) structure arranged between the memory regions to remove heat introduced by the memory regions. An Independent claim is also included for a process for operating the memory arrangement.

Description

The invention relates to a memory arrangement, a method for operating a memory arrangement and a method for making a memory array.

A non-volatile memory using Ge _x Sb _y Te _z as a memory area is known from [1], [2]. With the material Ge _x Sb _y Te _z , a phase change can take place between an amorphous and a crystalline phase. With this conversion, the electrical resistance of the material changes significantly. In the case of a brief current pulse, the material is visually melted. During a subsequent rapid cooling, the material remains in an amorphous state in which the material has a high electrical resistance. Reprogramming to a crystalline state is done using a weaker current pulse that is applied for a long time. As a result, the material cools sufficiently slowly to form a crystalline phase that has a lower resistance.

In 6 is a memory cell known from the prior art 600 shown according to the principle described.

Between a first electrode 601 and a second electrode 602 is an arrangement of a heating element 603 and a Ge _x Sb _y Te _z layer 604 arranged. By applying an electrical current between the electrodes 601 . 602 can using the heating element 603 a programmable area 605 the Ge _x Sb _y Te _z layer 604 are heated to such an extent that a conversion between an amorphous and a crystalline phase is made possible. If the pulse is long enough and weak enough, the programmable range becomes 605 brought into a crystalline state, when a sufficiently short and strong pulse is applied, the programmable area becomes 605 brought into an amorphous state. Since the amorphous state has a significantly higher electrical resistance than the crystalline state, a small reading current can be applied between the electrodes 601 . 602 the state in which the programmable area is scanned 605 is located as a storage area.

Will memory cells like the one in 6 shown memory cell 600 Packed in a high-density array, undesirable heat coupling between the individual cells can occur. With a long programming time (typically 100 ns), as is required to set the crystalline phase, heat can be undesirably transferred to a memory cell adjacent to the memory cell to be programmed, and the state thereof can thus be changed unintentionally. As a result, the information contained in the adjacent memory cell can be lost. The high temperature for generating the amorphous phase remains essentially localized on a memory cell to be programmed because of the shorter time period (typically 5 ns), in which case a part of the heat can also be undesirably dissipated from the memory cell. This is particularly critical in the case of two adjacent cells, one of which is in the amorphous and the other in the crystalline phase, one cell being converted from the amorphous state to the crystalline state. For this purpose, a certain temperature must be maintained in the memory cell to be programmed for a longer period of time, which can be transferred to the neighboring cell and whose state can also change.

For the reasons described, among other things, it has so far not been possible to generate a memory arrangement using Ge _x Sb _y Te _z regions with a sufficiently high packing density, since a high packing density has a small spacing and therefore problems with heat coupling between individual cells brings with it.

The invention is based on the problem, a Memory cell arrangement with changeable memory cells to create electrical resistance at which the integration density elevated and at the same time a sufficiently secure programming is made possible.

The problem is solved by a memory arrangement, by a method for operating a Storage arrangement and by a method of manufacturing Memory arrangement with the features according to the independent claims.

The memory arrangement according to the invention contains a substrate and a plurality of formed on and / or in the substrate Storage areas, each of which is set up in such a way that the electrical resistance of the respective storage area by means of thermal Treat selectively to a first value or to a second The value that can be set is greater than the first value. Furthermore, the memory arrangement according to the invention has a arranged between the storage areas heat dissipation structure for dissipating one of the memory areas Heat up.

Furthermore, the invention provides a method for operating a memory arrangement with the features described above, an electrical write signal being applied in accordance with the method, which is set up in such a way that the value of its electrical resistance to the first or the second value is set. Alternatively, ge According to the method, an electrical read signal is applied which is set up in such a way that the value of its electrical resistance can be detected for a respective memory area.

According to a manufacturing method A memory array becomes a plurality of memory areas formed on and / or in a substrate, each of which is such is set up that the electrical resistance of the respective memory area selectively to a first value by means of thermal treatment or can be set to a second value that is greater than the first value. Between the storage areas has a heat dissipation structure for dissipating one of the memory areas Arranged heat.

A basic idea of the invention exists in being a sufficiently good heat conductor Strukaur between the memory areas of the memory arrangement according to the invention to arrange, and thus an undesirable heat transfer to one to one programming (or to be read) memory cell adjacent To prevent memory cell. This ensures according to the invention that that information can be stored in a memory cell with sufficient certainty or can be read out, and that the other memory cells simultaneously during a programming or reading process before an undesired change of the Storage content protected are. This increases the holding time and the robustness of the error Memory arrangement improved.

The heat dissipation structure is clear heat bath with a sufficiently large one Heat capacity so that a high amount of heat, as occurs, for example, when programming the memory areas, of the heat dissipation structure can be included, and at most a very small proportion of the heat released is transferred to neighboring storage cells become. This protects these neighboring memory cells from it, undesirably to be reprogrammed.

The memory arrangement according to the invention has the Advantage that they become scalable with increasing integration density is because the energy to be injected is proportional to the volume a memory area. Furthermore, the storage arrangement is very good writing and reading times can be achieved, for example much better than with flash memories. Furthermore, very low write and read voltages (in of the order of magnitude of one volt) is sufficient, whereas high for flash memories Voltages of typically 10 volts and more are required. This saves energy, reduces waste heat and makes it more sensitive Integrated components are subject to unwanted interference from high electrical voltages protected.

Preferred developments of the invention result themselves from the dependent Claims.

The memory arrangement of the invention can be set up in such a way that at each of the memory areas an electrical write signal can be selectively applied in such a way is set up for the respective memory area the value of its electrical resistance is set to the first or the second value. alternative an electrical read signal can be applied that is set up in this way is that for a respective memory area the value of its electrical resistance is detectable. Especially when an electrical write signal is applied Sufficiently high electrical currents are required to store the memory to reprogram a memory area. Because of the use the heat dissipation structure according to the invention are, however, memory areas adjacent to a programmable memory area while programming protected against unwanted reprogramming.

The heat dissipation structure can be set up in this way be that when the write signal is applied to a respective memory area to set the value of an electrical resistance from the Write signal resulting heat dissipated like this that the other memory areas before a change their electrical resistance due to the write signal are protected.

The write signal can in particular be an electric current with a predeterminable strength, which is for a predeterminable Time can be applied to a respective memory area.

At least part of the memory areas is preferably at least partially from. a heat insulation structure surrounded, which is set up so that it is the heat coupling between the associated Storage area and the other storage areas prevented. In particular with short heating pulses, as are typically required, around a storage area from a state with low electrical Resistance. in a state with high electrical resistance. to transport, can the heat insulation structure the heat dissipation prevent or at least reduce from a respective memory area. This is the amount of heat sufficiently localized in the memory area to be reprogrammed, so that the memory area to be reprogrammed can be safely reprogrammed and adjacent memory areas from an unwanted Programming protected are.

Clearly remains due to the functionality the thermal insulation structure with short heating pulses (typically 5ns) as they are used to generate the State of the memory area with a high electrical resistance almost all of the heat is required within the selected storage area.

For longer heating pulses (typically 100 ns), as are often required to convert the storage area to a low electrical resistance state, some of the heat is given off to the heat dissipation structure, with the heat structure preferably being Art is set up that it heats up only slightly.

The memory arrangement can be such be set up so that each of the memory areas between a amorphous and a crystalline phase (i.e. in particular lattice structure) is switchable, the memory area in the crystalline phase first value and in the amorphous phase the second value of the electrical Resistance.

The memory areas of the memory arrangement are preferably set up in such a way that the crystalline phase by applying the write signal for a first time interval and that the amorphous phase by applying the write signal for a second Time interval is adjustable, the first time interval being larger than the second time interval.

The crystalline becomes vivid Phase of the storage area by heating through a sufficient long application of a heating signal (or by a sufficiently slow Cooling down) generated. An amorphous phase can be generated by the memory area is exposed to a brief heating signal (or sufficient is cooled quickly).

The storage areas preferably have a chalcogenide material, in particular an alloy Ge _x Sb _y Te _z (germanium, antimony, tellurium). Such materials have the advantage that they can be reprogrammed using sufficiently small electrical currents with short programming times (5ns or 100ns). The difference in the electrical resistances in the two phase states is significant, so that programming and reading of memory information that is robust in error is made possible. Typical values of the electrical resistances of chalcogenide storage areas are in the range of 1kΩ for the crystalline phase and in the range of 100kΩ for the amorphous phase.

As an alternative to chalcogenides also any other material can be used that is by means of annealing be selectively converted into an amorphous or crystalline state can. As an example of Another suitable material is the combination of crystalline materials To name silicon / amorphous silicon, which is particularly important for the integrability of the memory arrangement according to the invention in silicon microtechnology is advantageous.

The material of the heat dissipation structure is preferably a metal, polycrystalline silicon or an aluminate (in particular aluminum oxide, Al ₂ O ₃ ). When using a metal, the advantageous effect can be used that metals are typical. Conditions typically have a factor of a hundred greater thermal conductivity than insulators. This creates a heat bath that is suitable for sufficient amounts of heat generated when programming storage areas. to be distributed securely over the memory arrangement according to the invention and thus to protect memory areas that are not to be reprogrammed from an undesired change in their phase state and thus memory state.

In the memory arrangement according to the invention the insulation structure can be set up in such a way that it associated Storage area electrically decoupled from the other storage areas.

In other words, it can. the heat insulation structure must not only be set up and function for heat insulation, but also for electrical decoupling. For example, the heat insulation structure can be a cavity or it can be made of an electrically insulating material. In particular, can. the heat insulation structure can be made of silicon oxide (SiO ₂ ) or silicon nitride (Si ₃ N ₄ ).

The storage areas are preferably in the form of a matrix and / or arranged in the substrate. The heat dissipation structure can cover the storage areas essentially lattice-shaped surround. Alternatively, the heat dissipation structure the storage areas also zigzag, meandering or according to one surround another functionally suitable form.

As a substrate see in particular a semiconductor substrate, furthermore in particular a silicon substrate. However, it can also any other substrate (e.g. glass, ceramic) can be used.

At least part of the memory areas can a heating element coupled to the respective storage area in a thermally conductive manner have, by means of which the respective storage area thermal energy supplied is. By using a heating element, preferably made of a material a sufficiently high ohmic resistance, with a respective Storage area is coupled, it is ensured that when creating an electric current, the heating element is heated sufficiently strong, whereby the associated storage area is also heated in a spatially defined manner. The heating element can be tungsten and / or polycrystalline silicon exhibit.

It should be noted that the configurations, the above for the memory arrangement according to the invention are also described for the method for operating a memory arrangement or for the method apply to making a memory array.

Embodiments of the invention are shown in the figures and are explained in more detail below.

Show it:

1A to 1E Layer sequences at different times during a method for producing a memory arrangement according to a first exemplary embodiment of the invention,

2 3 shows a layout view of a memory arrangement according to the first exemplary embodiment of the invention,

3 2 shows a cross-sectional view of a memory arrangement according to the first exemplary embodiment of the invention,

4 2 shows a cross-sectional view of a memory arrangement according to a second exemplary embodiment of the invention,

5A 2 shows a schematic cross-sectional view of a storage area of the storage arrangement according to the invention,

5B another schematic cross-sectional view of a memory area of a memory arrangement according to the invention,

6 a memory cell according to the prior art.

Same or similar components in different Figures are given the same reference numerals.

The following will refer to 1A to 1E describes a method for producing a memory arrangement according to a first exemplary embodiment of the invention.

This method shows a 6F ² cell field based in part on the DRAM technology. Alternatively, any other cell array from DRAM technology can be used to apply the invention to this technology.

To the in 1A layer sequence shown 100 get in a silicon substrate 101 n ⁺ -doped areas 102 to 104 formed as first to third source / drain regions. Furthermore, first and second silicon oxide areas 105 . 106 formed in surface areas of the silicon substrate by etching trenches and filling the trenches with silicon oxide material. By means of the silicon oxide areas 105 . 106 an electrical decoupling of different memory cells of a memory arrangement to be formed is clearly realized. Furthermore, first and second word lines 107 . 108 made of an electrically conductive material on the substrate 101 in areas between the first source / drain area 102 and the second source / drain region 103 or between the second source / drain region 103 and the third source / drain region 104 formed, between the substrate 101 and the word lines 107 . 108 in each case a thin silicon oxide film is formed as a gate insulating layer. At the second source / drain region 103 becomes a common control line 111 formed from polycrystalline silicon. First and second auxiliary structures 109 . 110 are like the word lines 107 . 108 built and serve a self-aligned contact between the lines 108 . 110 and 109 . 107 to put. The control line 111 can be self-aligned between the word lines 107 . 108 be generated. Furthermore, the layer sequence obtained in this way is encapsulated with silicon oxide material, thereby encapsulating silicon oxide 112 is formed.

To the in 1B layer sequence shown 120 trenches are obtained using a lithography and an etching process 121 in the silicon oxide encapsulation 112 etched, creating the first and third source / drain regions 102, 104 be exposed. Furthermore, doped polysilicon material is placed in the trenches 121 introduced and etched back, creating first heating element components 122 be formed. Below is the first heating element components 122 Tungsten material in the trenches 121 deposited, creating second heating element components 123 be formed.

To the in 1C layer sequence shown 140 Chalcogenide material (Ge _x Sb _y Te _z ) is obtained on the surface of the layer sequence 120 deposited and part of the chalcogenide material etched back, creating chalcogenide structures 141 be formed. Furthermore, silicon oxide material is the silicon oxide encapsulation 112 etched back.

To the in 1D layer sequence shown 160 to get the exposed chalcogenide structures 141 by depositing and etching back silicon oxide material from lateral silicon oxide spacers 161 surround. Furthermore, copper material or aluminum material is deposited on the surface of the layer sequence thus obtained and etched back, thereby creating a copper-metal grid 162 (alternatively an aluminum metal grid), embedded between neighboring ones, by means of the silicon oxide spacers 161 Chalcogenide structures largely decoupled electrically and thermally from the environment 141 , is trained. Furthermore, additional silicon oxide material is deposited on the surface of the layer sequence obtained in this way and planarized using a CMP process ("chemical mechanical polishing").

To the in 1E shown storage arrangement 180 will get on top of the layer sequence 160 Metal material deposited and using a lithography and an etching process to a bit line 181 structured.

The following will refer to 1E the functionality of the memory arrangement 180 described according to the first embodiment of the invention.

It is clear in the phase state of chalcogenide structures 141  the Storage information of the respective memory cell is stored. The Memory arrangement 180  out 1E  shows two memory cells, associated the two chalcogenide structures 141 , The chalcogenide structures 141  can each be in a crystalline state in which the electrical Resistance of chalcogenide structures 141  is less than in an amorphous state. By applying an electric current will be a selected one Chalcogenide structure 141 . supports through the heating element components 122 . 123 , so very warm, that dependent ofthe length the application of the pulse (or depending on the cooling rate and strength of the pulse) the chalcogenide structures 141  selectively in the crystalline or amorphous state can be brought. through Application of a sufficiently long heating signal (typically 100ns) becomes the chalcogenide structure 141  brought into the crystalline state, by applying a sufficiently short heating signal (typically 5ns), the respective chalcogenide structure 141  in the brought amorphous state. In order to create the resulting heating pulses heat in the immediate vicinity of the respective chalcogenide structure 141  to localize are the chalcogenide structures 141  with the Silicon oxide spacers 161  as surrounded by thermal and electrical insulators. If what in particular with a longer one Heating pulse can occur, part of the heat of the chalcogenide structures 141  by the associated Silicon oxide spacer 161  can get this Warmth the metallic grid 162  given, which heats up only slightly. So there are other chalcogenide structures 141 that in the present Scenario should not be the subject of a programming process, protected from unintentionally a change their phase state (crystalline or amorphous). In the further describes how the left of the in 1E  chalcogenide structures shown 141  an information is programmed. Therefor is the first left chalcogenide structure 141  as a memory cell of the memory arrangement 180  selected by to the first week r tleitung 107 . clearly the gate area of a selection transistor, such electrical voltage is applied to the area of the substrate 101  (Channel region) between the first and second source / drain regions 102, 103  electrically conductive is. By applying a sufficiently high heating current as a result a programming signal on the common control line 111  becomes the electrical heating signal through the channel area over the Heater components 122 . 123  in the left Chalcogenide structure 141  passed, creating the chalcogenide structure 141  strongly heated becomes. With a sufficiently short heating pulse, the chalcogenide structure 141  in transferred an amorphous state with a high electrical resistance the chalcogenide structure becomes a sufficiently long heating pulse 141  in transferred a crystalline state with low ohmic resistance. The Heater components 122 . 123  are from one sufficiently high-resistance material is formed so that from the heating signal resulting ohmic heat in the heating element components 122 . 123  generated what heat the associated Chalcogenide structure 141  heated. For example, the crystalline state of the chalcogenide structure 141  with the low value of the ohmic resistance is assigned a logical value "1" and it can reflect the amorphous state of the chalcogenide structure 141  With a logic value "0" is assigned to the high value of the ohmic resistance become.

To one in one of the chalcogenide structures 141 Reading out stored information is in turn sent to the first word line 107 such an electrical voltage is applied to the common drive line 111 with the bit line 181 on the chalcogenide structure 141 is coupled. If an electrical read signal (for example a sufficiently small electrical current that does not change the state of the assigned chalcogenide structure) is now applied, then the flow depends on whether the chalcogenide structure 141 in the amorphous state with the high ohmic resistance or in the crystalline state with the low ohmic resistance, on the bit line 181 a large or a smaller electrical current that is detected. In this way, the memory information can be read out.

In the following we refer to 2 a layout top view 210 the storage arrangement 180 described according to the first embodiment of the invention.

In particular, in 2 shown that the 6F ² memory cells 200 the storage arrangement 180 are arranged in a matrix. F is the minimum structural dimension that can be achieved in a technology generation. The bit lines run along a first direction 181 , whereas the word lines 107 . 108 run in a direction orthogonal to it. It should be noted that in 2 the silicon oxide spacers 161 and the metal grill 162 are not shown.

The following will refer to 3 a sectional view 300 the storage arrangement 180 along an in 1E shown section line II '.

The storage arrangement 180 contains memory cells with a space requirement per memory cell of 6F ² , each of the memory cells as in 3 shown a chalcogenide structure 141 and a silicon oxide spacer surrounding it 161 having. Each of the memory cells is embedded in the grid-shaped metal grid 162 as a heat dissipation structure. The silicon oxide spacers 161 serve as a heat insulation structure. Especially in areas 301 the storage arrangement 180 , in which adjacent memory cells are arranged closely adjacent, the provision of the heat dissipation structure and the heat insulation structure is decisive in order to prevent thermal crosstalk between adjacent memory cells.

The following will refer to 4 a storage arrangement 400 described according to a second embodiment of the invention.

The storage arrangement 400 corresponds essentially to the memory arrangement 180 , but is designed as a memory arrangement with an area requirement of 4F ² per memory cell, that is with an even greater integration density than the memory arrangement 180 ,

With the storage arrangement 400 are the individual memory cells, each having a chalcogenide structure 141 and a silicon oxide spacer surrounding it 161 , again in a latticed metal structure 162 embedded. In contrast to the storage arrangement 180 are the memory cells in the memory arrangement 400 regularly arranged in a grid, that is, in the horizontal direction or in the vertical direction at a fixed distance from each other.

The following will refer to 5A . 5B an estimate of the heat exchange characteristics between a chalcogenide structure 141 and their surroundings, the chalcogenide structure 141 from a hollow cylindrical silicon oxide spacer 161 is surrounded by the metal structure 162 borders. In 5A is a cross-sectional view 500 , in 5B a top view 501 the structure shown.

As the height of the cylindrical chalcogenide structure 141 or the hollow cylindrical silicon oxide spacer 161 is assumed 100nm, the diameter of the chalcogenide structure 141 is assumed to be 50nm, and the thickness of the hollow cylinder wall of the silicon oxide spacer 161 is assumed to be 10nm.

The volume of the chalcogenide cylinder 141 results in 2⋅10 ^–22 m ³ .

The dissipated power ΔP in the cylindrical volume with the height of 100nm and the diameter of 50nm during programming results in ΔP = 0.2mA × 0.5V = 0.1mW (1) if 0.2mA current and 0.5V voltage are assumed. This corresponds to a heat generated in a time of Δt = 100ns when programming the crystalline state (5ns when programming the amorphous state) of: .DELTA.Q prog = ΔP Δt = 10 -11 J (5-10 -13 J) (2)

The heat flow through a cross section with the surface A and the length L of the chalcogenide structure 141 surrounding insulator 161 results at a thermal conductivity λ and a temperature difference Δt .DELTA.Q a b / Δt = A / L λ ΔT (3)

For the given dimensions and the given materials, a quantity of heat of ΔQ _ab / Δt = 1mW can be removed from the side walls of the volume if ΔT = 600K is assumed. This corresponds to a transported energy in a time of 100ns (5ns) .DELTA.Q from = 1⋅10 -10 J (0.5⋅10 -11 J) (4)

This leads to a heating of the cylindrical volume of the chalcogenide structure in 5ns 141 of ΔT = ΔQ prog (Δt = 5ns) / C v V = 1000K (5) for the above volume in the case of ideal insulation.

For good insulation, a thickness is the silicon oxide spacer 161 of 10nm is sufficient, since the heat dissipated in 5ns is smaller than the heat produced.

Because the melting point of chalcogenides at approximately 900K, the heating is large enough to change the Bring about phase state.

With a volume of chalcogenide structure 141 With a diameter of 50nm and a height of 100nm, a programming current of approximately 0.2mA or more is a good choice.

Furthermore, the heating of the surrounding metal 162 calculated. Under typical operating conditions, metal conducts approximately 100 times better than silicon dioxide. Therefore, the volume becomes roughly 100 times larger than the volume of the chalcogenide structure 141 and the silicon oxide spacer 161 heated up within 100ns: ΔT = Q prog (Δt = 100ns) / C v V = 10K [6]

Therefore, a metal absorbs most of it of energy without being significantly heated, provided that for each programming cell a metal volume of about 100 times larger volume is provided as the volume of the cell.

In a block of 256 × 256 cells can 256 Cells can be programmed in parallel.

In the proposed layout, the metal volume for a unit cell is V _m = 3⋅V _chalcogenide . As a result, each cell has a metal volume of approximately 700 times the volume of a cell volume. The proposed layout therefore helps to dissipate the energy from the programming cell into the surrounding area without significantly heating up neighboring cells.

• [1] Lai, S, Lowrey, T "OUM – A 180nm Nonvolatile Memory Cell Element Technology For Stand Alone und Embedded Applications", 2001 International Electron Devices Meeting, 5.12.2001
• [2] Gill,M, Lowrey, T, Park, J "Ovonic Unified Memory – A High-Performance Nonvolatile Memory Technology for Stand Alone Memory und Embedded Applications", IEEE International Solid State Circuits Conference, 4.-6.2.2002, Session 12, Abschnitt 12.4

The following publications are cited in this document:

• [1] Lai, S, Lowrey, T "OUM - A 180nm Nonvolatile Memory Cell Element Technology For Stand Alone and Embedded Applications", 2001 International Electron Devices Meeting, December 5, 2001
• [2] Gill, M, Lowrey, T, Park, J "Ovonic Unified Memory - A High-Performance Nonvolatile Memory Technology for Stand Alone Memory and Embedded Applications", IEEE International Solid State Circuits Conference, 4-6 February 2002, session 12, section 12.4

100

layer sequence

101

Silicon substrate

102

first Source / drain region

103

second Source / drain region

104

third Source / drain region

105

first Silicon area

106

second Silicon area

107

first wordline

108

second wordline

109

first auxiliary structure

110

second auxiliary structure

111

common drive line

112

Silica encapsulation

120

layer sequence

121

trenches

122

first Heater components

123

second Heater components

140

layer sequence

141

Chalcogenide structures

160

layer sequence

161

Silicon oxide spacer

162

metal grid

163

Silicon oxide intermediate layer

180

Memory arrangement

181

bit

200

6F ² memory cell

210

Layout plan view

300

sectional view

301

areas

400

Memory arrangement

500

cross-section

501

Top view

600

memory cell

601

first electrode

602

second electrode

603

heating element

604

Ge _x Sb _y Te _z layer

605

programmable Area

Claims (16)

Storage arrangement with - a substrate; - one A plurality of storage areas formed on and / or in the substrate, each of which is set up so that the electrical resistance of the respective storage area selectively by means of thermal treatment can be set to a first value or to a second value, which is bigger as the first value; - one heat dissipation structure arranged between the storage areas for the dissipation of one of the memory areas Warmth. Memory arrangement according to claim 1, so arranged is that selective to each of the memory areas - an electric one Write signal can be applied, which is set up in such a way that for the respective storage area the value of its electrical resistance is set to the first or the second value; or - an electric one Read signal can be applied, which is set up in such a way that for one respective storage area the value of its electrical resistance is detectable. Storage arrangement according to claim 2, wherein the heat dissipation structure is set up such that when the write signal is applied to a respective memory area for setting the value of its electrical resistance resulting from the write signal Warmth like that is dissipated that the other memory areas before changing their electrical Resistance due to the write signal are protected. Memory arrangement according to one of claims 1 to 3, in which at least a part of the storage areas at least partially of a thermal insulation structure is surrounded, which is set up such that it is the heat coupling between the associated Storage area and the other storage areas decreased. Memory arrangement according to one of claims 1 to 4, wherein each the storage areas between an amorphous and a crystalline Phase is switchable, with the memory area in the crystalline Phase the first value and in the amorphous phase the second value of electrical resistance. The memory arrangement of claim 5, wherein the memory areas are set up such that the crystalline phase is applied of the write signal for a first time interval and that the amorphous phase by applying of the write signal for a second time interval is adjustable, the first time interval is bigger than the second time interval. The memory arrangement of claim 6, wherein the memory areas have a chalcogenide material. A memory arrangement according to claim 7, wherein the memory areas have Ge _x Sb _y Te _z . Storage arrangement according to one of claims 1 to 8, wherein the material the heat dissipation structure - a metal; - polycrystalline Silicon; or - on Is aluminate. Memory arrangement according to one of the claims che 4 to 9, in which the thermal insulation structure is set up such that it electrically decouples the associated storage area from the other storage areas. Storage arrangement according to one of claims 4 to 10, wherein the heat insulation structure - silicon oxide; or - silicon nitride is made. Memory arrangement according to one of claims 1 to 11, wherein the memory areas in matrix form are arranged on and / or in the substrate and in which the heat dissipation structure surrounds the storage areas in a substantially lattice shape. Memory arrangement according to one of claims 1 to 12, in which at least a part of the storage areas is coupled to the respective storage area in a thermally conductive manner Has heating element, by means of which the respective storage area thermal energy can be supplied is. Storage arrangement according to claim 13, wherein at least one heating element - tungsten; and or - polycrystalline Has silicon. Method for operating a memory arrangement - with a memory arrangement with - a substrate; A plurality of storage areas formed on and / or in the substrate, each of which is set up in such a way that the electrical resistance of the respective storage area can be selectively adjusted to a first value or to a second value by means of thermal treatment, which is greater than the first Value; A heat dissipation structure arranged between the storage areas for dissipating heat supplied to one of the storage areas; - being according to the procedure An electrical write signal is applied which is set up in such a way that the value of its electrical resistance is set to the first or the second value for the respective memory area; or - an electrical read signal is applied which is set up in such a way that the value of its electrical resistance can be detected for a respective memory area. Method for producing a memory arrangement, in which - a majority of memory areas formed on and / or in a substrate each of which is set up so that the electrical Resistance of the respective storage area by means of thermal treatment selectively adjustable to a first value or to a second value is the bigger as the first value; - between a heat dissipation structure in the storage areas for draining heat supplied from one of the storage areas is arranged.