DE10329325A1 - Structuring treatment of surface with edge, on which protection layer is deposited and then removed by etching together with edge - Google Patents
Structuring treatment of surface with edge, on which protection layer is deposited and then removed by etching together with edge Download PDFInfo
- Publication number
- DE10329325A1 DE10329325A1 DE2003129325 DE10329325A DE10329325A1 DE 10329325 A1 DE10329325 A1 DE 10329325A1 DE 2003129325 DE2003129325 DE 2003129325 DE 10329325 A DE10329325 A DE 10329325A DE 10329325 A1 DE10329325 A1 DE 10329325A1
- Authority
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- Germany
- Prior art keywords
- edge
- protective layer
- protection layer
- deposited
- photoresist
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
- B81C1/00523—Etching material
- B81C1/00547—Etching processes not provided for in groups B81C1/00531 - B81C1/00539
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00404—Mask characterised by its size, orientation or shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3085—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31058—After-treatment of organic layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/16—Coating processes; Apparatus therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09145—Edge details
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Plasma & Fusion (AREA)
- Micromachines (AREA)
Abstract
Description
Die Erfindung betrifft die Behandlung einer Oberfläche mit einer Kante.The The invention relates to the treatment of a surface with an edge.
Wie
in
Nach
dem derzeitigen Stand der Technik wird für die Herstellung der Struktur
Dieses Problem tritt beispielsweise in der MEMS (Michroelectromechanical System)-Technologie auf, mit deren Hilfe Gräben in Silizium mit vorgegebenem Neigungswinkel geätzt werden können.This Problem occurs for example in the MEMS (Michroelectromechanical System) technology, with the help of trenches in silicon with a given Etched angle can be.
Davon ausgehend liegt der Erfindung die Aufgabe zugrunde, ein, insbesondere fotolithographisches, Erzeugen von Strukturen über scharfe Kanten zu ermöglichen.From that Based on the invention, the object is based, in particular photolithographic, creating structures over sharp edges.
Diese Aufgabe wird durch die in den unabhängigen Ansprüchen angegebenen Erfindungen gelöst.These The object is achieved by those specified in the independent claims Inventions solved.
Vorteilhafte Ausgestaltungen ergeben sich aus den abhängigen Ansprüchen.advantageous Embodiments emerge from the dependent claims.
Der Erfindung liegt die Idee zugrunde, dass sich die geschilderten Schwierigkeiten bei der Herstellung einer Struktur über eine Kante hinweg vermeiden lassen, wenn die Kante abgerundet wird. Die Ursache für die Schwierigkeiten ist darin begründet, dass der Fotolack an Spitzen Kanten aufgrund der Oberflächenspannung sehr dünn wird. Dagegen bildet der Lack auf einem abgerundeten Bereich eine kontinuierliche Fläche über die Topografie hinweg, so dass eine weitere Strukturierung möglich ist.Of the Invention is based on the idea that the difficulties described avoid creating over the edge of a structure leave when the edge is rounded. The cause of the difficulties is due to the fact that the photoresist edges at edges due to surface tension very thin becomes. In contrast, the paint on a rounded area forms a continuous Surface over the Topography away, so that a further structuring is possible.
Dementsprechend wird in einem Behandlungsverfahren für eine Oberfläche mit einer Kante zunächst an der Kante eine Schutzschicht aufgebracht. Dann wird die Schutzschicht und die Kante einem Ätzprozess ausgesetzt und die Kante durch den Ätzprozess verrundet.Accordingly is involved in a treatment process for a surface an edge first applied a protective layer on the edge. Then the protective layer and the edge of an etching process exposed and the edge rounded by the etching process.
Prinzipiell reicht es, die Schutzschicht gleich dick über die Kante und die benachbarten Ebenen verlaufen zu lassen. Durch die exponierte Lage der Kante aufgrund der Topografie der Oberfläche erfolgt ein verstärktes Ätzen an der Kante, wodurch diese abgetragen und dabei verrundet wird. Vorteilhaft wird die Schutzschicht aber gleich so aufgetragen, dass sie auf der Kante dünner ist als neben der Kante, insbesondere so dass sie auf der Kante vollständig oder zumindest nahezu vollständig verschwindet.in principle It is sufficient, the protective layer of the same thickness over the edge and the adjacent Levels to go. Due to the exposed position of the edge Due to the topography of the surface, there is an increased etching the edge, whereby this is removed and thereby rounded. Advantageous However, the protective layer is applied immediately so that they on the edge thinner is as next to the edge, especially so that it is on the edge Completely or at least almost completely disappears.
Vorzugsweise wird eine Schutzschicht aus Fotolack eingesetzt. Es kann aber auch ein anderes, insbesondere im Ätzprozess wegätzbares Material zum Einsatz kommen, wie beispielsweise eine auflaminierte Folie.Preferably a protective layer of photoresist is used. But it can too another, especially in the etching process wegätzbares Material are used, such as a laminated Foil.
Vorzugsweise ist die Oberfläche die Oberfläche eines Schaltungsträgers, auf dem nachher eine Schaltungsstruktur erzeugt wird.Preferably is the surface the surface a circuit board, on which a circuit structure is subsequently generated.
Die Oberfläche kann die Oberfläche von Keramik, Metall, Glas, Kunststoff oder eines Halbleiters sein. Die Kante wird insbesondere von zwei nicht parallelen Ebenen eines Kristallgitters gebildet und ist dadurch eine atomare Kante. Beispielsweise kann sie von der 1,1,1-Ebene und der 1,0,0-Ebene eines Silizium-Einkristalls gebildet werden.The surface can the surface of ceramic, metal, glass, plastic or a semiconductor. In particular, the edge is made up of two non-parallel planes Crystal lattice is formed and is thus an atomic edge. For example For example, it may be formed by the 1,1,1 level and the 1,0,0 level of a silicon single crystal become.
Nach dem Verrunden der Kante durch Abtragen kann die restliche Schutzschicht entfernt und die Oberfläche mit einem leitfähigen Metall bedeckt werden, um auf der Oberfläche eine Struktur zu erzeugen.To The rounding off of the edge by removing it can remove the remaining protective layer removed and the surface with a conductive Metal to be produced on the surface of a structure.
Vorteilhafte Ausgestaltungen eines Erzeugnisses mit einer Oberfläche, die mit einem Verfahren nach einer der zuvor geschilderten Ausgestaltungen behandelt wurde, ergeben sich analog zu den vorteilhaften Ausgestaltungen des Verfahrens. Das Erzeugnis ist insbesondere ein MEMS.advantageous Embodiments of a product having a surface, the treated with a method according to one of the previously described embodiments was, arise analogously to the advantageous embodiments of the procedure. The product is in particular a MEMS.
Weitere Vorteile und Merkmale der Erfindung ergeben sich aus der Beschreibung eines Ausführungsbeispiels anhand der Zeichnung. Dabei zeigt:Further Advantages and features of the invention will become apparent from the description an embodiment based on the drawing. Showing:
In
Entlang
der Linie, an der der erste ebene Bereich
Als
nächstes
der Fotolack
Wie
in
Anschließend kann
der Fotolack
Das
Ergebnis ist die in
Das beschriebene Verfahren hat zahlreiche Vorteile:
- – Es ist leicht durchführbar.
- – Es ist leicht, beispielsweise durch optische Inspektion, nachprüfbar, ob das Verfahren eingesetzt wurde.
- – Ein ganzer Wafer kann auf einmal, also im Nutzen, prozessiert werden, statt die Kanten einzeln abfahren zu müssen, wie in einem mechanischen Verfahren.
- - It's easy to do.
- - It is easy, for example, by optical inspection, verifiable that the process has been used.
- - A whole wafer can be processed in one go, ie in use, instead of having to cut off the edges individually, as in a mechanical process.
Ein Hauptanwendungsbereich des Verfahrens sind Silizium-Einkristalle, insbesondere für die MEMS-Technologie. Das Verfahren ist allerdings auch für alle anderen Materialien mit spitzen Kanten einsetzbar, wie beispielsweise Halbleiter, Metalle, Keramiken, Gläser, Kunststoffe usw. Es ist insbesondere für alle Materialien geeignet, bei denen ein mechanisches Polieren nicht möglich ist, weil beispielsweise die vorhandenen Strukturen zu klein sind.One Main application of the method are silicon single crystals, in particular for the MEMS technology. The procedure is however also for all other materials can be used with sharp edges, such as semiconductors, metals, ceramics, glasses, Plastics, etc. It is especially suitable for all materials where a mechanical polishing is not possible because, for example the existing structures are too small.
Claims (11)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2003129325 DE10329325A1 (en) | 2003-06-30 | 2003-06-30 | Structuring treatment of surface with edge, on which protection layer is deposited and then removed by etching together with edge |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2003129325 DE10329325A1 (en) | 2003-06-30 | 2003-06-30 | Structuring treatment of surface with edge, on which protection layer is deposited and then removed by etching together with edge |
Publications (1)
Publication Number | Publication Date |
---|---|
DE10329325A1 true DE10329325A1 (en) | 2005-02-17 |
Family
ID=34071555
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2003129325 Withdrawn DE10329325A1 (en) | 2003-06-30 | 2003-06-30 | Structuring treatment of surface with edge, on which protection layer is deposited and then removed by etching together with edge |
Country Status (1)
Country | Link |
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DE (1) | DE10329325A1 (en) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1999022406A1 (en) * | 1997-10-28 | 1999-05-06 | Fairchild Semiconductor Corporation | Trench ic and method of making |
US6027982A (en) * | 1999-02-05 | 2000-02-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures with improved isolation fill and surface planarity |
US6265317B1 (en) * | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
DE4240504C2 (en) * | 1992-12-02 | 2003-04-30 | Cis Inst Fuer Mikrosensorik Gg | Process for the production of interconnect structures over trench regions of substrates |
-
2003
- 2003-06-30 DE DE2003129325 patent/DE10329325A1/en not_active Withdrawn
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE4240504C2 (en) * | 1992-12-02 | 2003-04-30 | Cis Inst Fuer Mikrosensorik Gg | Process for the production of interconnect structures over trench regions of substrates |
WO1999022406A1 (en) * | 1997-10-28 | 1999-05-06 | Fairchild Semiconductor Corporation | Trench ic and method of making |
US6027982A (en) * | 1999-02-05 | 2000-02-22 | Chartered Semiconductor Manufacturing Ltd. | Method to form shallow trench isolation structures with improved isolation fill and surface planarity |
US6265317B1 (en) * | 2001-01-09 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Top corner rounding for shallow trench isolation |
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