DE112004003046B4 - Power semiconductor devices - Google Patents
Power semiconductor devices Download PDFInfo
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- DE112004003046B4 DE112004003046B4 DE112004003046.3T DE112004003046T DE112004003046B4 DE 112004003046 B4 DE112004003046 B4 DE 112004003046B4 DE 112004003046 T DE112004003046 T DE 112004003046T DE 112004003046 B4 DE112004003046 B4 DE 112004003046B4
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- gate electrode
- semiconductor device
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Abstract
Halbleitervorrichtung (3300) mit: – einem Driftbereich (3306) von einem ersten Leitfähigkeitstyp, – einem Wannenbereich (p), der sich über dem Driftbereich (3306) erstreckt und einen zweiten Leitfähigkeitstyp aufweist, der dem ersten Leitfähigkeitstyp entgegengesetzt ist, – einer Mehrzahl von aktiven Gräben (3302), die sich durch den Wannenbereich (p) und in den Driftbereich (3306) erstrecken, wobei innerhalb eines jeden der Mehrzahl von aktiven Gräben (3302) gebildet sind: – eine erste leitfähige Gate-Elektrode (3310), die entlang einer ersten Grabenseitenwand angeordnet und gegenüber dieser isoliert ist, – eine zweite leitfähige Gate-Elektrode (3310), die entlang einer zweiten Grabenseitenwand angeordnet und gegenüber dieser isoliert ist, – eine leitfähige Abschirmelektrode (3311), die zwischen der ersten (3310) und der zweiten (3310) leitfähigen Gate-Elektrode angeordnet ist, wobei die Abschirmelektrode (3311) gegenüber der ersten (3310) und der zweiten (3310) Gate-Elektrode isoliert ist und sich tiefer in den Graben (3302) erstreckt als die erste (3310) und die zweite (3310) Gate-Elektrode, wobei sich das leitfähige Abschirm-Poly vertikal bis zu der Siliziumoberfläche entlang der Höhe des Grabens erstreckt, bis oberhalb einer Hohe der ersten und zweiten leitfähigen Gate-Elektroden, – Source-Bereichen (n+) mit dem ersten Leitfähigkeittyp, die innerhalb des Wannenbereichs (p) und benachbart zu der Mehrzahl von aktiven Gräben (3302) gebildet sind, und – einem Umfangsgraben (2603A, 3213), der sich zumindest teilweise um die Mehrzahl von aktiven Gräben (3302) erstreckt, so dass zumindest einige der Gräben (3302) der Mehrzahl von aktiven Gräben (3302) senkrecht zu dem Umfangsgraben (2603A, 3213) sind, wobei die leitfähige Abschirmelektrode (3311) mit der Source-Metallisierung elektrisch leitend verbunden ist, wobei der Umfangsgraben (2603A, 3213) mit einem Dielektrikum (2605A) ausgekleidet und mit leitfähigem Material (2607A) gefüllt ist, wobei die erste leitfähige Gate-Elektrode (3310) und die zweite leitfähige Gate-Elektrode (3310) entlang einer dritten Dimension innerhalb der Mehrzahl von aktiven Gräben (3302) verbunden sind.A semiconductor device (3300) comprising: - a drift region (3306) of a first conductivity type, - a well region (p) extending over the drift region (3306) and having a second conductivity type opposite to the first conductivity type, - a plurality of active trenches (3302) extending through the well region (p) and into the drift region (3306), wherein within each of the plurality of active trenches (3302) are formed: a first conductive gate electrode (3310) is disposed along and insulated from a first trench sidewall, a second conductive gate electrode (3310) disposed along and insulated from a second trench sidewall, a conductive shield electrode (3311) disposed between the first (3310) and the second (3310) conductive gate electrode is arranged, wherein the shielding electrode (3311) opposite to the first (3310) and the second (331 0) gate electrode and extends deeper into the trench (3302) than the first (3310) and second (3310) gate electrodes, the conductive shield poly extending vertically to the silicon surface along the height of the trench extends to above a height of the first and second conductive gate electrodes, first conductivity type source regions (n +) formed within the well region (p) and adjacent to the plurality of active trenches (3302), and a circumferential trench (2603A, 3213) extending at least partially around the plurality of active trenches (3302) so that at least some of the trenches (3302) of the plurality of active trenches (3302) are perpendicular to the circumferential trench (2603A, 3213) wherein the conductive shield electrode (3311) is electrically connected to the source metallization, wherein the peripheral trench (2603A, 3213) is lined with a dielectric (2605A) and coated with conductive material (2607A) wherein the first conductive gate electrode (3310) and the second conductive gate electrode (3310) are connected along a third dimension within the plurality of active trenches (3302).
Description
HINTERGRUND DER ERFINDUNGBACKGROUND OF THE INVENTION
Die vorliegende Erfindung betrifft im Allgemeinen Halbleitervorrichtungen und im Besonderen verschiedene Ausführungsformen für verbesserte Leistungshalbleitervorrichtungen, wie etwa Transistoren und Dioden, und deren Herstellungsverfahren, einschließlich Packages und Schaltungen, die selbige enthalten.The present invention relates generally to semiconductor devices and, more particularly, to various embodiments for improved power semiconductor devices, such as transistors and diodes, and their fabrication processes, including packages and circuits incorporating the same.
Die Schlüsselkomponente in Leistungselektronikanwendungen ist der Festkörperschalter. Von der Zündsteuerung in Kraftfahrzeuganwendungen bis hin zu batteriebetriebenen elektronischen Geräten von Endverbrauchern sowie zu Leistungsumwandlern in industriellen Anwendungen gibt es einen Bedarf für einen Leistungsschalter, der die Anforderungen der besonderen Anwendung optimal erfüllt. Festkörperschalter, die beispielsweise den Leistungs-Metalloxid-Halbleiter-Feldeffekttransistor (Leistungs-MOSFET), den Bipolar-Transistor mit isoliertem Gate (IGBT) und verschiedene Arten von Thyristoren umfassen, haben sich fortlaufend weiterentwickelt, um diesen Bedarf zu erfüllen. Im Fall des Leistungs-MOSFET sind beispielsweise doppelt diffundierte Strukturen (DMOS) mit lateralem Kanal (z. B.
Einige der definierenden Leistungseigenschaften für den Leistungsschalter sind sein Ein-Widerstand, die Durchbruchspannung und die Schaltgeschwindigkeit. Abhängig von den Anforderungen einer besonderen Anwendung wird eine unterschiedliche Betonung auf jedes dieser Leistungsfähigkeitskriterien gelegt. Beispielsweise für Leistungsanwendungen von größer als ungefähr 300–400 Volt zeigt der IGBT einen inhärent niedrigeren Ein-Widerstand im Vergleich mit dem Leistungs-MOSFET, aber seine Schaltgeschwindigkeit ist aufgrund seiner langsameren Ausschaltkennlinien niedriger. Deshalb ist der IGBT für Anwendungen von mehr als 400 Volt mit niedrigen Schaltfrequenzen, die einen niedrigen Ein-Widerstand erfordern, der bevorzugte Schalter, wohingegen der Leistungs-MOSFET häufig die Vorrichtung der Wahl für relativ höherfrequentige Anwendungen ist. Wenn die Frequenzanforderungen einer gegebenen Anwendung die Art von Schalter, die verwendet wird, vorschreiben, bestimmen die Spannungsanforderungen die konstruktive Ausbildung des besonderen Schalters. Beispielsweise im Fall des Leistungs-MOSFET stellt die Verbesserung des Spannungsleistungsvermögens des Transistors, während ein niedriger RDSon aufrechterhalten wird, wegen der proportionalen Beziehung zwischen dem Drain-Source-Ein-Widerstand RDSon und der Durchbruchspannung eine Herausforderung dar. Um diese Herausforderung anzusprechen, sind verschiedene Ladungsausgleichsstrukturen in dem Transistordriftbereich mit unterschiedlichen Graden an Erfolg entwickelt worden.Some of the defining performance characteristics for the circuit breaker are its on-resistance, breakdown voltage and switching speed. Depending on the requirements of a particular application, a different emphasis is placed on each of these performance criteria. For example, for power applications greater than about 300-400 volts, the IGBT exhibits an inherently lower on-resistance compared to the power MOSFET, but its switching speed is lower because of its slower turn-off characteristics. Therefore, for applications of more than 400 volts with low switching frequencies requiring low on-resistance, the IGBT is the preferred switch, whereas the power MOSFET is often the device of choice for relatively higher frequency applications. When the frequency requirements of a given application dictate the type of switch that is used, the voltage requirements determine the structural design of the particular switch. For example, in the case of the power MOSFET, improving the voltage capability of the transistor while maintaining a low R DSon poses a challenge because of the proportional relationship between the drain-source on-resistance R DSon and the breakdown voltage. To address this challenge, Various charge balancing structures have been developed in the transistor drift area with varying degrees of success.
Die Leistungsfähigkeitsparameter der Vorrichtung werden auch durch den Fertigungsprozess und das Verpacken des Chips beeinflusst. Es sind Versuche unternommen worden, einige dieser Herausforderung durch Entwickeln einer Vielfalt von verbesserten Verarbeitungs- und Verpackungstechniken anzusprechen.The performance parameters of the device are also affected by the manufacturing process and packaging of the chip. Attempts have been made to address some of this challenge by developing a variety of improved processing and packaging techniques.
Ob dies nun in besonders tragbaren elektronischen Geräten für Endverbraucher oder Routern und Hubs in Kommunikationssystemen ist, wachsen die Arten von Anwendungen für den Leistungsschalter weiterhin mit der Ausbreitung der elektronischen Industrie an. Der Leistungsschalter bleibt deshalb eine Halbleitervorrichtung mit einem hohen Entwicklungspotenzial.Whether this is in particularly portable consumer electronic devices or routers and hubs in communications systems, the types of circuit breaker applications continue to grow with the spread of the electronic industry. The power switch therefore remains a semiconductor device with a high development potential.
Halbleitervorrichtungen der eingangs genannten Art sind beispielsweise aus der
KURZE ZUSAMMENFASSUNG DER ERFINDUNGBRIEF SUMMARY OF THE INVENTION
Die vorliegende Erfindung stellt verschiedene Ausführungsformen für Leistungsvorrichtungen für eine breite Vielfalt von Leistungselektronikanwendungen bereit. Im weiteren Sinn kombiniert ein Aspekt der Erfindung eine Anzahl von Ladungsausgleichstechniken und andere Techniken, zum Reduzieren parasitärer Kapazität, um zu verschiedenen Ausführungsformen für Leistungsvorrichtungen mit verbessertem Spannungsleistungsvermögen, höherer Schaltgeschwindigkeit und niedrigerem Ein-Widerstand zu gelangen. Ein anderer Aspekt der Erfindung stellt verbesserte Terminierungsstrukturen für Nieder-, Mittel- und Hochspannungsvorrichtungen bereit. Gemäß einem anderen Aspekt der Erfindung umfassen Leistungsvorrichtungen mit Ladungsausgleich Temperatur- und Strommesselemente, wie etwa Dioden, auf dem gleichen Chip. Andere Aspekte der Erfindung verbessern den Ersatzreihenwiderstand (ESR) oder Gate-Widerstand für Leistungsvorrichtungen. The present invention provides various embodiments of power devices for a wide variety of power electronics applications. More broadly, an aspect of the invention combines a number of charge balancing techniques and other techniques to reduce parasitic capacitance to arrive at various embodiments for power devices having improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. According to another aspect of the invention, charge balanced power devices include temperature and current sensing elements, such as diodes, on the same chip. Other aspects of the invention improve equivalent series resistance (ESR) or gate resistance for power devices.
Diese und andere Aspekte der Erfindung werden nachstehend ausführlicher in Verbindung mit den begleitenden Zeichnungen beschrieben. These and other aspects of the invention will be described in more detail below in conjunction with the accompanying drawings.
KURZBESCHREIBUNG DER ZEICHNUNGENBRIEF DESCRIPTION OF THE DRAWINGS
Die FIG. sind nicht fortlaufend nummeriert.The FIG. are not consecutively numbered.
AUSFÜHRLICHE BESCHREIBUNG DER ERFINDUNGDETAILED DESCRIPTION OF THE INVENTION
Der Leistungsschalter kann durch irgendein Bauelement einem von Leistungs-MOSFET, einem IGBT, verschiedenen Arten von Thyristoren und dergleichen implementiert sein. Viele der neuartigen hierin vorgestellten Techniken sind zu Veranschaulichungszwecken im Zusammenhang mit dem Leistungs-MOSFET beschrieben. Es ist jedoch zu verstehen, dass die verschiedenen Ausführungsformen der hierin beschriebenen Erfindung nicht auf den Leistungs-MOSFET beschränkt sind und auf viele andere Arten von Leistungsschalttechnologien angewandt werden können, die beispielsweise IGBTs und andere Arten von bipolaren Schaltern, und verschiedenen Arten von Thyristoren sowie Dioden umfassen. Weiter sind die verschiedenen Ausführungsformen der Erfindung zu Veranschaulichungszwecken so gezeigt, dass sie spezifische p- und n-leitende Bereiche umfassen. Fachleuten werden verstehen, dass die Lehren hierin gleichermaßen auf Vorrichtungen anwendbar sind, in denen die Leitfähigkeiten der verschiedenen Bereiche umgekehrt sind.The power switch may be implemented by any one of power MOSFET, IGBT, various types of thyristors, and the like. Many of the novel techniques presented herein are described in connection with the power MOSFET for purposes of illustration. It should be understood, however, that the various embodiments of the invention described herein are not limited to the power MOSFET and can be applied to many other types of power switching technologies, including IGBTs and other types of bipolar switches, and various types of thyristors and diodes include. Further, for purposes of illustration, the various embodiments of the invention are shown to include specific p- and n-type regions. It will be understood by those skilled in the art that the teachings herein are equally applicable to devices in which the conductivities of the various regions are reversed.
In
Wegen seiner vertikalen Gate-Struktur ermöglicht der MOSFET
Obwohl ein vertikaler Trench-MOSFET
Eine Möglichkeit, die Gate-Source-Kapazität Cgs zu verringern, ist, die Kanallänge des Transistors zu verringern. Eine kürzere Kanallänge verringert direkt die Gate-Kanal-Komponente von Cgs. Eine kürzere Kanallänge ist auch direkt proportional zu RDSon und ermöglicht das Erhalten der gleichen Vorrichtungsstromfähigkeit mit weniger Gate-Gräben. Dies verringert sowohl Cgs als auch Cgd, indem der Betrag an Gate-Source- und Gate-Drain-Überlappung verringert wird. Eine kürzere Kanallänge macht jedoch die Vorrichtung anfällig gegenüber Punch-Through, wenn die Verarmungsschicht, die infolge des in Sperrrichtung vorgespannten Body-Drain-Übergangs gebildet wird, sich tief in den Body-Bereich schiebt und den Source-Bereichen annähert. Ein Verringern der Dotierungskonzentration des Driftbereiches, so dass er mehr von der Verarmungsschicht trägt, hat den unerwünschten Effekt, dass der Ein-Widerstand RDSon des Transistors erhöht wird.One way to reduce the gate-to-source capacitance Cgs is to decrease the channel length of the transistor. A shorter channel length directly reduces the gate channel component of Cgs. A shorter channel length is also directly proportional to R DSon and allows obtaining the same device current capability with fewer gate trenches. This reduces both Cgs and Cgd by reducing the amount of gate-source and gate-drain overlap. However, a shorter channel length renders the device prone to punch-through when the depletion layer formed as a result of the reverse biased body-drain junction pushes deeply into the body region and approaches the source regions. Reducing the doping concentration of the drift region to carry more of the depletion layer has the undesirable effect of increasing the on-resistance R DSon of the transistor.
Eine Verbesserung der Transistorstruktur, die eine Verringerung der Kanallänge zulässt und auch wirksam ist, um die obigen Nachteile anzusprechen, verwendet zusätzliche ”Abschirm”-Gräben, die seitlich von Gate-Gräben beabstandet sind. In
Die Bedeutung von tieferen Source-Abschirmgräben
Um die Eingangskapazität weiter zu vermindern, können zusätzliche konstruktive Verbesserungen vorgenommen werden, die sich darauf fokussieren, die Gate-Drain-Kapazität Cgd zu verringern. Wie es oben besprochen wurde, wird die Gate-Drain-Kapazität Cgd durch die Überlappung zwischen dem Gate- und dem Driftbereich am Boden des Grabens hervorgerufen. Ein Verfahren zum Verringern dieser Kapazität erhöht die Dicke der Gate-Dielektrikumschicht am Boden des Grabens. Wieder nach
Eine andere Technik zum Verringern der Gate-Graben-Kapazität Cgd umfasst das Abschirmen des Gates unter Verwendung von einer oder mehreren vorgespannten Elektroden. Gemäß dieser Ausführungsform sind innerhalb des Gate-Grabens und unter dem leitfähigen Material, das die Gate-Elektrode bildet, eine oder mehrere Elektroden gebildet, um das Gate vor dem Driftbereich abzuschirmen, wodurch die Gate-Drain-Überlappungskapazität wesentlich verringert wird. In
Während die Ladungssteuergräben
Noch eine andere Technik zum verbessern Schaltgeschwindigkeit des Leistungs-MOSFET verringert die Gate-Drain-Kapazität Cgd durch Anwenden einer Doppel-Gate-Struktur. Gemäß dieser Ausführungsform ist die Gate-Struktur innerhalb des Grabens in zwei Segmente aufgespalten: ein erstes Segment, das die herkömmliche Gate-Funktion erfüllt, welche das Schaltsignal empfängt, und ein zweites Segment, das das erste Gate-Segment vor dem Drift-(Drain)-Bereich abschirmt und unabhängig vorgespannt sein kann. Dies verringert die Gate-Drain-Kapazität des MOSFET drastisch.
Eine andere Ausführungsform für einen verbesserten Leistungs-MOSFET ist in
Die verschiedenen soweit beschriebenen Techniken, wie etwa Gate-Abschirmung und Trench-Elektroden zur vertikalen Ladungssteuerung können kombiniert werden, um Leistungsvorrichtungen zu erhalten, die laterale und vertikale MOSFETs, IGBTs, Dioden und dergleichen umfassen, deren Leistungskennlinien für eine gegebene Anwendung optimiert sind. Beispielsweise kann die in
In einer Ausführungsform sind die Techniken mit Doppel-Gate und abgeschirmtem Gate innerhalb des gleichen Grabens kombiniert, um Schaltgeschwindigkeits- und Sperrspannungsverbesserungen bereitzustellen.
Die so weit beschriebenen Vorrichtungen wenden Kombinationen von abgeschirmtem Gate, Doppel-Gate und andere Techniken an, um parasitäre Kapazität zu verringern. Aufgrund von Störeffekten minimieren jedoch diese Techniken die Gate-Drain-Kapazität Cgd nicht vollständig. In
In beiden in den
Die mit einem Graben versehene tiefe Body-Struktur, wie sie in Verbindung mit den
Die Verbesserungen, die durch die obigen Leistungsvorrichtungen und Abwandlungen davon bereitgestellt werden, haben robuste Schaltelemente für Leistungselektronikanwendungen mit relativ niedriger Spannung ergeben. Niedrige Spannung, so wie es hierin verwendet wird, bezieht sich auf einen Spannungsbereich von beispielsweise ungefähr 30 V–40 V und darunter, obwohl dieser Bereich abhängig von der besonderen Anwendung variieren kann. Anwendungen, die Sperrspannungen wesentlich über diesen Bereich erfordern, benötigen irgendeine Art von konstruktiver Modifikation an dem Leistungstransistor. Typischerweise wird die Dotierungskonzentration in dem Driftbereich des Leistungstransistors reduziert, damit die Vorrichtung höheren Spannungen während des Sperrzustandes tragen kann. Ein eher leicht dotierter Driftbereich führt jedoch zu einer Zunahme des Ein-Widerstandes RDSon des Transistors. der höhere spezifische Widerstand erhöht direkt den Leistungsverlust des Schalters. Der Leistungsverlust hat Bedeutung gewonnen, da die jüngsten Fortschritte bei der Halbleiterherstellung die Packungsdichte der Leistungsvorrichtungen weiter erhöht haben.The improvements provided by the above power devices and variations thereof have yielded robust switching elements for relatively low voltage power electronics applications. Low voltage, as used herein, refers to a voltage range of, for example, about 30V-40V and below, although this range may vary depending on the particular application. Applications that require blocking voltages substantially beyond this range require some form of constructive modification to the power transistor. Typically, the doping concentration in the drift region of the power transistor is reduced to make the device higher Can carry voltages during the blocking state. However, a rather lightly doped drift region leads to an increase in the on-resistance R DSon of the transistor. the higher resistivity directly increases the power loss of the switch. The power loss has gained importance as recent advances in semiconductor fabrication have further increased the packing density of the power devices.
Es sind Versuche unternommen worden, den Ein-Widerstand und den Leistungsverlust der Vorrichtung zu verbessern, während gleichzeitig die hohe Sperrspannung aufrechterhalten wird. Viele dieser Versuche wenden verschiedene vertikale Ladungssteuertechniken an, um ein weitgehend flaches elektrisches Feld vertikal in der Halbleitervorrichtung zu schaffen. Eine Anzahl von Vorrichtungsstrukturen von dieser Art ist vorgeschlagen worden, welche die laterale Verarmungsvorrichtung, die in den
In
Jede der resultierenden Ausführungsformen kann auch mit der Technik des Trench-Bodys kombiniert werden, um die schädliche parasitäre Kapazität weiter zu minimieren, wie es in Verbindung mit MOSFET
In einer anderen Ausführungsform ist eine Klasse von Transistoren vom Akkumulationsmodus vorgesehen, die verschiedene Ladungsausgleichstechniken für einen kleineren Spannungsverlust in Durchlassrichtung und eine höhere Sperrfähigkeit anwenden. Bei einem typischen Transistor vom Akkumulationsmodus gibt es keinen Sperrübergang und die Vorrichtung wird abgeschaltet, indem der Kanalbereich neben dem Gate-Anschluss leicht invertiert wird, um den Stromfluss zu unterbinden. Wenn der Transistor eingeschaltet wird, indem eine Gate-Vorspannung angelegt wird, wird in dem Kanalbereich vielmehr eine Akkumulationsschicht als eine Inversionsschicht gebildet. Da es keine Bildung eines Inversionskanals gibt, ist der Kanalwiderstand minimiert. Zusätzlich gibt es keine PN-Body-Diode in einem Transistor vom Akkumulationsmodus, was die Verluste minimiert, die sonst in bestimmten Schaltkreisanwendungen, wie etwa synchronen Gleichrichtern, auftraten. Der Nachteil der herkömmlichen Vorrichtungen vom Akkumulationsmodus ist, dass der Driftbereich leicht dotiert sein muss, um eine Umkehr-Vorspannung zu unterstützen, wenn sich die Vorrichtung im Blockiermodus befindet. Ein leichter dotierter Driftbereich setzt sich zu einem höheren Ein-Widerstand um. Die hierin beschriebenen Ausführungsformen überwinden diese Einschränkung, indem sie verschiedene Ladungsausgleichstechniken in einer Vorrichtung vom Akkumulationsmodus anwenden.In another embodiment, a class of accumulation mode transistors is provided, which are different Use charge balance techniques for a smaller forward voltage drop and higher blocking capability. In a typical accumulation mode transistor, there is no blocking transition and the device is turned off by slightly inverting the channel region adjacent to the gate to prevent current flow. On the contrary, when the transistor is turned on by applying a gate bias, an accumulation layer is formed as an inversion layer in the channel region. Since there is no formation of an inversion channel, the channel resistance is minimized. In addition, there is no PN body diode in a accumulation mode transistor, which minimizes the losses that otherwise occurred in certain circuit applications, such as synchronous rectifiers. The disadvantage of the conventional accumulation mode devices is that the drift region must be lightly doped to support reverse bias when the device is in blocking mode. A light doped drift region converts to a higher on-resistance. The embodiments described herein overcome this limitation by applying various charge balancing techniques in an accumulation mode device.
In
Terminierungsstrukturentermination structures
Diskrete Vorrichtungen der oben beschriebenen verschiedenen Arten weisen eine Durchbruchspannung auf, die durch die zylindrische oder kugelförmige Form des Verarmungsbereiches am Rand des Chips begrenzt ist. Da diese zylindrische oder kugelförmige Durchbruchspannung typischerweise viel niedriger ist als die Parallelebenen-Durchbruchspannung BVpp in der aktiven Fläche der Vorrichtung, muss der Rand der Vorrichtung derart terminiert werden, dass eine Durchbruchspannung für die Vorrichtung erreicht wird, die nahe bei der Durchbruchspannung der aktiven Fläche liegt. Es sind unterschiedliche Techniken entwickelt worden, um das Feld und die Spannung gleichmäßig über die Randterminierungsbreite auszubreiten, um eine Durchbruchspannung zu erzielen, die nahe bei BVpp liegt. Diese umfassen Feldplatten, Feldringe, Übergangsterminierungserweiterung (JTE von junction termination extension) und unterschiedliche Kombinationen dieser Techniken. Das oben erwähnte
In alternativen Ausführungsformen wirken eine oder mehrere ringförmige Gräben, die den Umfang des Zellen-Arrays umgeben, derart, dass das elektrische Feld verringert wird und der Lawinendurchbruch erhöht wird.
Die
In einer anderen Abwandlung ist statt des Füllens des Terminierungsgrabens
Für Vorrichtungen mit niedriger Spannung kann es sein, dass die Eckenkonstruktionen für den Grabenterminierungsring nicht kritisch sind. Jedoch kann bei Vorrichtungen mit höherer Spannung die Rundung der Ecken des Terminierungsrings mit einem größeren Krümmungsradius erwünscht sein. Je höher die Spannungsanforderungen der Vorrichtung, desto größer kann der Krümmungsradius an den Ecken des Terminierungsgrabens sein. Ebenso kann die Anzahl von Terminierungsringen erhöht werden, wenn die Vorrichtungsspannung zunimmt.
Prozesstechnikenprocess technologies
Bislang ist eine Anzahl von unterschiedlichen Vorrichtungen mit Trench-Strukturen, die mehrfache vergrabene Elektroden oder Dioden aufweisen, beschrieben worden. Um diese Trench-Elektroden vorzuspannen, lassen es diese Vorrichtungen zu, dass ein elektrischer Kontakt mit jeder der vergrabenen Schichten hergestellt werden kann. Hierin ist eine Anzahl von Verfahren zum Bilden der Trench-Strukturen mit vergrabenen Elektroden und zum Herstellen eines Kontakts mit den vergrabenen Poly-Schichten innerhalb der Gräben offenbart. In einer Ausführungsform sind Kontakte mit Trench-Poly-Schichten an den Rand des Chips hergestellt.
In einer anderen Ausführungsform werden Kontakte zu mehrfachen Poly-Schichten in einem gegebenen Graben in der aktiven Fläche der Vorrichtung anstelle entlang des Randes des Chips hergestellt.
Die
Eine vereinfachte Layoutansicht von oben nach unten einer beispielhaften Trench-Vorrichtung mit einer Abschirmkontaktstruktur einer aktiven Fläche ist in
Eine alternative Ausführungsform zum Kontaktieren von Trench-Abschirm-Poly-Schichten in der aktiven Fläche ist in
Spezifische Prozessrezepturen und -parameter und Abwandlungen davon zum Durchführen von vielen der Schritte in den obigen Prozessabläufen sind allgemein bekannt. Für eine gegebene Anwendung können bestimmte Prozessrezepturen, Chemikalien und Materialtypen fein abgestimmt werden, um die Herstellbarkeit und das Leistungsvermögen der Vorrichtung zu verbessern. Verbesserungen können von dem Ausgangsmaterial aus vorgenommen werden, d. h. dem Substrat, auf dem der epitaktische (Epi) Driftbereich gebildet wird. In den meisten Leistungsanwendungen ist eine Reduktion des Ein-Widerstands RDSon des Transistors erwünscht. Der ideale Ein-Widerstand eines Leistungstransistors ist eine strenge Funktion des kritischen Feldes, welches definiert ist als das maximale elektrische Feld in der Vorrichtung unter Durchbruchbedingungen. Der spezifische Ein-Widerstand des Transistors kann signifikant verringert werden, wenn die Vorrichtung aus einem Material gefertigt wird, das ein kritisches Feld aufweist, das höher ist als das von Silizium, vorausgesetzt, dass eine vernünftige Beweglichkeit aufrechterhalten bleibt. Obgleich viele der Merkmale der Leistungsvorrichtungen, einschließlich die Strukturen und Prozesse, soweit im Kontext eines Siliziumsubstrats beschrieben worden sind, sind andere Ausführungsformen, die anderes Substratmaterial als Silizium verwenden, möglich. Gemäß einer Ausführungsform sind die hierin beschriebenen Leistungsvorrichtungen aus einem Substrat gefertigt, das aus einem Material mit breiter Bandlücke hergestellt ist, welches beispielsweise Siliziumcarbid (SiC), Galliumnitrid (GaN), Galliumarsenid (GaAs), Indiumphosphid (InP), Diamant und dergleichen umfasst. Diese Materialien mit breiter Bandlücke zeigen ein kritisches Feld, das höher ist als das kritische Feld für Silizium, und können eine signifikante Verringerung des Ein-Widerstandes des Transistors zulassen.Specific process formulas and parameters and variations thereof for performing many of the steps in the above processes are well known. For a given application, certain process formulations, chemicals, and types of materials may be fine-tuned to improve the manufacturability and performance of the device. Improvements can be made from the starting material, ie, the substrate on which the epitaxial (epi) drift region is formed. In most power applications , a reduction in the on-resistance R DSon of the transistor is desired. The ideal on-resistance of a power transistor is a strict function of the critical field, which is defined as the maximum electric field in the device under breakdown conditions. The specific on-resistance of the transistor can be significantly reduced if the device is made of a material having a critical field higher than that of silicon, provided that reasonable mobility is maintained. Although many of the features of the power devices, including the structures and processes, have been described in the context of a silicon substrate, other embodiments using substrate material other than silicon are possible. In one embodiment, the power devices described herein are fabricated from a substrate made of wide bandgap material including, for example, silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), indium phosphide (InP), diamond, and the like. These wide bandgap materials exhibit a critical field that is higher than the critical field for silicon and can allow a significant reduction in the on-resistance of the transistor.
Ein anderer primärer Beiträger für den Ein-Widerstand eines Transistors ist die Dicke und Dotierungskonzentration des Driftbereichs. Der Driftbereich ist typischerweise durch epitaktisch aufgewachsenes Silizium gebildet. Um RDSon zu verringern, ist es erwünscht, die Dicke des Epi-Driftbereichs zu minimieren. Die Dicke der Epi-Schicht wird teilweise durch die Art des Ausgangssubstrats vorgeschrieben. Beispielsweise ist ein mit rotem Phosphor dotiertes Substrat eine übliche Art von Ausgangssubstratmaterial für diskrete Halbleitervorrichtungen. Eine Eigenschaft von Phosphoratomen ist jedoch, dass sie in Silizium schnell diffundieren. Die Dicke des Epi-Bereichs, der oben auf dem Substrat gebildet wird, wird deshalb derart bestimmt, dass die Diffusion von Phosphoratomen nach oben aus dem darunter liegenden stark dotierten Substrat ausgeglichen wird.Another primary contributor to the on-resistance of a transistor is the thickness and doping concentration of the drift region. The drift region is typically formed by epitaxially grown silicon. In order to reduce R DSon , it is desirable to minimize the thickness of the epi drift region. The thickness of the epi-layer is dictated in part by the nature of the starting substrate. For example, a substrate doped with red phosphorus is a common type of starting substrate material for discrete semiconductor devices. However, one property of phosphorus atoms is that they diffuse rapidly in silicon. The thickness of the epi region formed on top of the substrate is therefore determined so as to balance the diffusion of phosphorous atoms upwardly from the underlying heavily doped substrate.
Es gibt eine Anzahl von anderen konstruktiven und verarbeitungstechnischen Aspekten des Leistungstransistors und anderer Leistungsvorrichtungen, die deren Leistungsvermögen signifikant beeinflussen können. Die Form des Grabens ist ein Beispiel. Um die potentiell beschädigenden elektrischen Felder zu verringern, die dazu neigen, sich um die Ecken des Grabens herum zu konzentrieren, ist es erwünscht, scharfe Ecken zu vermeiden und statt dessen Gräben zu bilden, die gerundete Ecken aufzuweisen. Um die Zuverlässigkeit zu verbessern, ist es auch erwünscht, Grabenseitenwände mit glatten Oberflächen zu besitzen. Die unterschiedlichen Ätzchemikalien bieten einen Ausgleich zwischen mehreren Antworten, wie etwa: Siliziumätzrate, Selektivität gegenüber der Ätzmaske, Ätzprofil (Seitenwandwinkel), Rundung der oberen Ecke, Seitenwandrauheit und Rundung des Grabenbodens. Eine Chemikalie mit Fluor, beispielsweise SF6, liefert eine hohe Siliziumätzrate (größer als 1,5 μm/min), gerundete Grabengründe und ein gerades Profil. Der Nachteil der Fluorchemikalie sind raue Seitenwände und Schwierigkeiten mit der Steuerung der Oberseite des Grabens (kann wieder eintretend sein). Eine Chlorchemikalie, beispielsweise Cl2, liefert glattere Seitenwände und eine bessere Steuerung des Ätzprofils und der Oberseite des Grabens. Der Ausgleich mit der Chlorchemikalie betrifft eine niedrigere Siliziumätzrate (kleiner als 1,0 μm/min) und ein geringeres Runden des Grabenbodens.There are a number of other design and processing aspects of the power transistor and other power devices that can significantly affect their performance. The shape of the trench is an example. In order to reduce the potentially damaging electrical fields which tend to concentrate around the corners of the trench, it is desirable to avoid sharp corners and instead form trenches having rounded corners. To improve reliability, it is also desirable to have trench sidewalls with smooth surfaces. The different etch chemistries provide a balance between multiple responses, such as: silicon etch rate, selectivity to the etch mask, etch profile (sidewall angle), top corner rounding, sidewall roughness, and trench bottom curve. A chemical with fluorine, such as SF6, provides a high silicon etch rate (greater than 1.5 μm / min), rounded Trenching grounds and a straight profile. The drawback of the fluorochemical are rough sidewalls and difficulty controlling the top of the trench (may be reentrant). A chlorochemical, such as Cl 2 , provides smoother sidewalls and better control of the etch profile and top of the trench. The balance with the chlorochemical concerns a lower silicon etch rate (less than 1.0 μm / min) and less rounding of the trench bottom.
Wie es oben in Verbindung mit verschiedenen Transistoren mit abgeschirmten Gate-Strukturen beschrieben wurde, isoliert eine Schicht aus dielektrischem Material die Abschirmelektrode vor der Gate-Elektrode. Diese Zwischenelektroden-Dielektrikumschicht, die manchmal als das Zwischen-Poly-Dielektrikum oder IPD bezeichnet wird, muss auf eine robuste und zuverlässige Weise gebildet werden, so dass sie der Potentialdifferenz standhalten kann, die zwischen der Abschirmelektrode und der Gate-Elektrode vorhanden sein kann. Mit erneutem Bezug auf die
Eine Anzahl von oben beschriebenen Trench-Vorrichtungen umfasst eine Grabenseitenwanddotierung zu Ladungsausgleichszwecken. Beispielsweise weisen alle in den
Fachleute werden feststellen, dass die Verwendung von Plasmadotierungstechnologie oder Dotierungstechnologie mit gepulstem Plasma nicht auf Graben-Ladungsausgleichsstrukturen begrenzt ist, sondern auch auf andere Strukturen angewandt werden kann, die Trench-Terminierungsstrukturen und Trench-Drain-, Source- oder Body-Verbindungen umfassen. Beispielsweise kann dieses Verfahren dazu verwendet werden, die Grabenseitenwände von Strukturen mit abgeschirmtem Graben zu dotieren, wie etwa jene, die in Verbindung mit den
Andere Verfahren, die angewandt werden können, um eine gleichmäßigere Kanalkonzentration zu erhalten, umfassend das Bilden des Kanalübergangs unter Verwendung eines Epitaxieprozesses, unter Verwendung von Mehrfach-Energieimplantationen und anderen Techniken zum Schaffen eines abrupten Übergangs. Eine andere Technik wendet einen Ausgangswafer mit einer leicht dotierten Deckschicht an. Auf diese Weise wird Kompensation minimiert und Aufwärtsdiffusion kann begrenzt werden, um ein gleichmäßigeres Kanaldotierungsprofil zu schaffen.Other methods that may be used to obtain a more uniform channel concentration include forming the channel junction using an epitaxial growth process, using multiple energy implantation and other techniques to provide an abrupt transition. Another technique uses a starting wafer with a lightly doped capping layer. In this way, compensation is minimized and upward diffusion can be limited to provide a more uniform channel doping profile.
Eine Graben-Vorrichtung kann Nutzen aus der Tatsache ziehen, dass der Schwellenwert durch die Kanaldotierungskonzentration entlang der Grabenseitenwände festgelegt wird. Ein Prozess, der eine hohe Dotierungskonzentration von den Gräben weg zulässt, während ein niedriger Schwellenwert aufrechterhalten wird, kann helfen, den Punch-Through-Mechanismus zu verhindern. Das Vorsehen der p– Wannen-Dotierung vor dem Gate-Oxidationsprozess erlaubt eine Segregation von p-leitenden Fremdstoffen der Wanne, z. B. Bor, in das Grabenoxid, um die Konzentration in dem Kanal zu verringern, wodurch der Schwellenwert vermindert wird. Wenn dies mit den obigen Techniken kombiniert wird, kann dies eine kürzere Kanallänge ohne Punch-Through ergeben.A trench device may benefit from the fact that the threshold is determined by the channel doping concentration along the trench sidewalls. A process that allows a high doping concentration away from the trenches while maintaining a low threshold can help reduce the punching Through mechanism to prevent. The provision of the p-well doping prior to the gate oxidation process allows segregation of p-type impurities of the well, e.g. Boron, into the trench oxide to reduce the concentration in the channel, thereby reducing the threshold. Combining this with the above techniques may result in a shorter channel length without punch through.
Manche Leistungsanwendungen erfordern das Messen des Betrags an Strom, der durch den Leistungstransistor fließt. Dies wird typischerweise bewerkstelligt, indem ein Teil des Gesamtvorrichtungsstroms isoliert und gemessen wird, der dann dazu verwendet wird, den Gesamtstrom zu extrapolieren, der durch die Vorrichtung fließt. Der isolierte Teil des Gesamtvorrichtungsstromes fließt durch eine Strommess- oder -detektionsvorrichtung, die ein Signal erzeugt, das die Größe des isolierten Stromes angibt und das dann dazu verwendet wird, den Gesamtvorrichtungsstrom zu bestimmen. Diese Anordnung ist allgemein als Stromspiegel bekannt. Der Strom erfassende Transistor wird gewöhnlich monolithisch mit der Leistungsvorrichtung gefertigt, wobei beide Vorrichtungen ein gemeinsames Substrat (Drain) und Gate teilen.
Verschiedene Verfahren zum Isolieren der Strommessvorrichtung von der Hauptvorrichtung sind in der übertragenen US-Patentanmeldung NR. 10/315,719 mit dem Titel ”Method of Isolating the Current Sense on Power Devices While Maintaining a Continuous Strip Cell” für Yedinak et al. beschrieben, deren Offenbarungsgehalt hierin durch Bezugnahme vollständig mit eingeschlossen ist. Ausführungsformen zum Integrieren der Messvorrichtung zusammen mit unterschiedlichen Leistungsvorrichtungen, die jene mit Ladungsausgleichsstrukturen umfassen, werden nachstehend beschrieben. Gemäß einer Ausführungsform wird in einem Leistungstransistor mit Ladungsausgleichsstrukturen und einer monolithisch integrierten Strommessvorrichtung die Strommessfläche vorzugsweise mit der gleichen kontinuierlichen MOSFET-Struktur sowie der Ladungsausgleichsstruktur gebildet. Ohne eine Kontinuität in der Ladungsausgleichsstruktur aufrecht zu erhalten, wird die Durchbruchspannung der Vorrichtung aufgrund einer Fehlanpassung in der Ladung verschlechtert, was dazu führt, dass der spannungstragende Bereich nicht vollständig verarmt wird.
Es gibt eine Anzahl von Leistungsanwendungen, bei denen es erwünscht ist, Dioden auf dem gleichen Chip wie der Leistungstransistor zu integrieren. Derartige Anwendungen umfassen eine Temperaturmessung, einen Schutz vor elektrostatischer Entladung (ESD), aktives Klemmen und Spannungsteilung, neben anderen. Zur Temperaturmessung werden beispielsweise ein oder mehrere in Reihe geschaltete Dioden monolithisch mit dem Leistungstransistor integriert, wobei die Anoden- und Kathodenanschlüsse der Diode heraus zu separaten Bond-Pads geführt werden, oder mit monolithischen Steuerschaltkreiskomponenten, die leitende Verbindungen verwenden, verbunden werden. Die Temperatur wird durch die Änderung der Spannung (Vf) in Durchlassrichtung der Diode (oder Dioden) gemessen. Beispielsweise mit einer geeigneten Verbindung mit dem Gate-Anschluss des Leistungstransistors wird die Gate-Spannung, wenn das Vf der Diode mit der Temperatur abfällt, heruntergezogen, was den Strom, der durch die Vorrichtung fließt, verringert, bis die gewünschte Temperatur erreicht ist.There are a number of power applications where it is desired to integrate diodes on the same chip as the power transistor. Such applications include temperature measurement, electrostatic discharge (ESD) protection, active clamping and voltage division, among others. For temperature measurement, for example, one or more series-connected diodes are monolithically integrated with the power transistor, with the anode and cathode terminals of the diode being routed out to separate bond pads, or connected to monolithic control circuit components using conductive connections. The temperature is measured by the change in the voltage (Vf) in the forward direction of the diode (or diodes). For example, with proper connection to the gate terminal of the power transistor, as the Vf of the diode drops with temperature, the gate voltage is pulled down, reducing the current flowing through the device until the desired temperature is reached.
In einer anderen Ausführungsform wird durch Anwenden ähnlicher Isolationstechniken, wie sie in Vorrichtung
Beispielhafte ESD-Schutzschaltkreise sind in den
Bei manchen Leistungsanwendungen ist eine wichtige Leistungskennlinie einer Leistungsschaltvorrichtung ihr Ersatzreihenwiderstand oder ESR (equivalent series resistance), der ein Maß der Impedanz des Schaltanschlusses oder Gates ist. Beispielsweise in synchronen Tiefsitzstellern, die Leistungs-MOSFETs verwenden, hilft ein niedrigeres ESR, Schaltverluste zu vermindern. Im Fall von Trench-Gate-MOSFETs wird deren Gate-ESR zum großen Teil durch die Abmessungen der mit Polysilizium gefüllten Gräben bestimmt. Die Länge der Gate-Gräben kann beispielsweise durch Packungseinschränkungen begrenzt werden, wie etwa die minimale Größe des Drahtbondpads. Es ist bekannt, dass ein Aufbringen eines Silizidfilms auf Polysilizium den Widerstand des Gates senkt. Das Implementieren eines silizierten Polys in Trench-MOSFETs stellt jedoch eine Anzahl von Herausforderungen. In typischen planaren, diskreten MOS-Strukturen kann das Gate-Poly siliziert werden, nachdem die Übergänge implantiert und auf ihre jeweiligen Tiefen hineingetrieben worden sind. Für Trench-Gate-Vorrichtungen, bei denen das Gate-Poly eingelassen ist, wird das Aufbringen eines Silizids komplizierter. Die Verwendung eines herkömmlichen Silizids begrenzt die maximale Temperatur, der ein Wafer einer Nach-Silizidbehandlung ausgesetzt werden kann, auf ungefähr weniger als 900°C. Dies stellt eine signifikante Einschränkung beim Stadium des Fertigungsprozesses dar, wenn Diffusionsbereiche, wie etwa Sourcen, Drains und Wannen gebildet werden. Das typischste Metall, das für Silizide verwendet wird, ist Titan. Andere Metalle, wie etwa Wolfram, Tantal, Kobalt und Platin können ebenfalls verwendet werden, was eine Nach-Silizidbehandlung mit höherem Wärmebudget zulässt, was wiederum eine größere Verarbeitungsbreite bietet. Der Gate-ESR kann auch durch verschiedene Layouttechniken verringert werden.In some power applications, an important performance characteristic of a power switching device is its equivalent series resistance (ESR), which is a measure of the impedance of the switching port or gate. For example, in low-speed synchronous actuators using power MOSFETs, a lower ESR helps reduce switching losses. In the case of trench gate MOSFETs, their gate ESR is largely determined by the dimensions of the polysilicon filled trenches. The length of the gate trenches may be limited, for example, by package constraints, such as the minimum size of the wire bonding pad. It is known that depositing a silicide film on polysilicon lowers the resistance of the gate. However, implementing a siliconized polys in trench MOSFETs presents a number of challenges. In typical planar, discrete MOS structures, the gate poly can be silicated after the junctions have been implanted and driven into their respective depths. For trench gate devices in which the gate poly is embedded, the application of a silicide becomes more complicated. The use of a conventional silicide limits the maximum temperature that a wafer can be subjected to post-silicide treatment to approximately less than 900 ° C. This represents a significant limitation on the stage of the manufacturing process when forming diffusion regions such as sources, drains, and wells. The most typical metal used for silicides is titanium. Other metals such as tungsten, tantalum, cobalt, and platinum may also be used, allowing post-silicide treatment with a higher heat budget, which in turn provides more processing latitude. The gate ESR can also be reduced by various layout techniques.
Nachstehend sind verschiedene Ausführungsformen zum Bilden von Leistungsschaltvorrichtungen mit Ladungsausgleich und niedrigerem ESR beschrieben. In einer in
In einer anderen Ausführungsform wird das Poly-Gate durch ein Metall-Gate ersetzt. Gemäß dieser Ausführungsform wird das Metall-Gate durch Abscheiden von z. B. Ti unter Verwendung einer kollimierten Quelle gebildet, um die Füllfähigkeit in einer Trench-Struktur zu verbessern. Nach dem Aufbringen des Metall-Gates und sobald die Übergänge implantiert und eingetrieben worden sind, umfassen Wahlmöglichkeiten für Dielektrika HDP und TEOS, um das Gate von den Source/Body-Kontakten zu isolieren. In alternativen Ausführungsformen wird ein Damascene, oder Doppel-Damascene-Ansatz mit verschiedenen Wahlmöglichkeiten für Metall von Aluminium- bis Kupfer-Deckmetallen verwendet, um den Gate-Anschluss zu bilden.In another embodiment, the poly gate is replaced by a metal gate. According to this embodiment, the metal gate is formed by depositing z. For example, Ti is formed using a collimated source to improve fillability in a trench structure. After the metal gate has been deposited and once the junctions have been implanted and driven in, selections for dielectrics include HDP and TEOS to isolate the gate from the source / body contacts. In alternative embodiments, a damascene or dual damascene approach with various choices of metal from aluminum to copper capping metals is used to form the gate terminal.
Das Layout des Gate-Leiters kann auch den Gate-ESR und die gesamte Schaltgeschwindigkeit der Vorrichtung beeinflussen.The layout of the gate conductor may also affect the gate ESR and the overall switching speed of the device.
Obgleich das Obige eine vollständige Beschreibung der bevorzugten Ausführungsformen der Erfindung angibt, sind viele Alternativen, Modifikationen und Äquivalente möglich. Beispielsweise sind viele der Ladungsausgleichstechniken hierin im Zusammenhang mit einem MOSFET und insbesondere mit einem Trench-Gate-MOSFET beschrieben. Fachleute werden feststellen, dass die gleichen Techniken auf andere Vorrichtungsarten angewandt werden können, die IGBTs, Thyristoren, Dioden oder planare MOSFETs sowie laterale Vorrichtungen umfassen. Aus diesen und anderen Gründen sollte deshalb die obige Beschreibung nicht als den Schutzumfang der Erfindung, welcher durch die beigefügten Ansprüche definiert ist, einschränkend betrachtet werden.Although the above is a complete description of the preferred embodiments of the invention, many alternatives, modifications, and equivalents are possible. For example, many of the charge balance techniques are described herein in the context of a MOSFET, and more particularly, a trench-gate MOSFET. Those skilled in the art will recognize that the same techniques can be applied to other types of devices including IGBTs, thyristors, diodes or planar MOSFETs, as well as lateral devices. For these and other reasons, therefore, the above description should not be taken as limiting the scope of the invention, which is defined by the appended claims.
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TWI399855B (en) | 2013-06-21 |
WO2005065385A3 (en) | 2006-04-06 |
TW200840041A (en) | 2008-10-01 |
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CN102420241A (en) | 2012-04-18 |
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CN101794817A (en) | 2010-08-04 |
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TW200527701A (en) | 2005-08-16 |
TWI521726B (en) | 2016-02-11 |
TWI404220B (en) | 2013-08-01 |
KR101216533B1 (en) | 2013-01-21 |
JP4903055B2 (en) | 2012-03-21 |
CN103199017A (en) | 2013-07-10 |
JP2012109580A (en) | 2012-06-07 |
CN101180737B (en) | 2011-12-07 |
JP2008227514A (en) | 2008-09-25 |
CN103199017B (en) | 2016-08-03 |
TW201308647A (en) | 2013-02-16 |
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