DE1524175A1 - Testing device in electronic data processing systems - Google Patents

Description

Testing device in electronic data processing systems

The invention relates to a device in electronic data processing systems for the automatic detection of defective components with a test character pattern source, a memory for storing the expected output pattern and a comparison and Display device. ·

Electronic data processing systems are known to consist of .multiple units made up of electronic circuits are what components like transistors, capacitors and resistors contain. During the operation of electronic data processing systems may be a mistake in any of the dei's learning interrupt the operations of the entire system.

-Z-

209844/0901

BAD ORiGtNAL

There are already a number of Proposals have been made and implemented based on that errors in the operation of the system are monitored. These techniques rely on generally predicting a result which is obtained during an operation step of the complete system. Deviations between the The actual result achieved and the predicted result during this operational step indicate that an error has occurred.

There is already a facility for correcting mistakes ^! that occur during the operation of an electronic data processing system. Such corrections can often be achieved by repeating those operational steps during which the error occurred, hoping that the cause of the error was temporary and therefore does not recur during the repetition. According to another known scheme, the operation is performed in a double set of circuits. According to another known method, a correction variable which compensates for the error is introduced into the results obtained during the operational steps in which the error occurred.

The previously mentioned methods and devices for automatic error detection thus use techniques with the aid of which errors can be detected and / or corrected which occur during the operation of electronic data processing systems without a relationship being established with the actual cause of the error. For maintenance problems, these methods and devices include the Γ disadvantage that they do not determine the location of the error within the machine structure ^N, which led to the erroneous operation, has. '. _:

Thereafter, facilities for identifying the location of the fault for faults occurring during operation were also known, which, however, required extensive additional circuits that were necessary for dl "

Docket 7816 ₂₀ gg _{4 4} / _Q g Q _{1 Β} ^

- Systems specially designed and built into these systems became. However, these facilities also have the disadvantage that they cannot easily be attached to already existing data processing systems, so that substantial additional costs for installation in such cases.

The following article may serve as an example of the group of devices for error detection explained above: ¹¹ A Computer Organization and Programming System for Automated Maintenance ", by K. Maling and EL Allen, published in ¹¹ IEEE Transactions on Electronic Computers", December 1965 * volume EC-12, No. 5, page 887.

This group also includes the article "Engineering Testing Techniques" by William Perzley, published in "Automatic Control", September 1958, page 2k. The essential thing about the facilities described there is the use of "probes" that are connected to the logical elements that are to be tested in the experimental circles. Here, known input signals are transmitted to the input of the experimental circuit and the output signals of the tested logic elements are recorded for the subsequent comparison with previously determined correct output signals. The analysis of the output signals of the tested elements helps to identify the cause of the failure which occurs during the operation of the experimental circuit. While this technique of fault location detects faults fairly accurately, it requires extensive additional wiring from test points in the circuit. The inclusion of numerous test sites in an existing electronic data processing system affects the operation of the system and therefore requires careful redesign of the entire system to accommodate the test sites.

Through the article "The Diagnosis of a Synchronous Subsequential Switching System", by S. Seshu and D.N. Freeman, published

Docket 761 υ *

BADOFHOfNAt.

£ 09if-ifQ-i 090/1

August 19 ^ 2 in "I, RE Transactions on Electronic Computers", Volume EC ^1. 1, No. 4, page 459, a system for testing the logic circuits of a machine is known, which locates fault, wherein a Zμgriff only. to the entrances; and outputs of the machine under test is available. This device transmits prescribed input signals to the machine to be tested, ■ monitors the output signals and compares these output signals with previously determined standard output signals. The results are used to identify the faulty components in the machine. While this system leads to an accurate determination of the faulty components in the logic circuits, it requires a complicated special test system, which is required in addition to the machine to be tested. In addition, it cannot identify any errors in those control circuits that do not have to perform any logical functions.

The state of the art for the aforementioned group of test devices is further supported by an essay in Proceedings Seminar onAutomatic Checkout Techniques held at Batteile Memorial Institute September 5, 6 and 7, 1962 Jointly Sponsord by the AERONAUTICAL SYSTEMS DIVISION OF THE AIR FOR

FORCE and BATTELLE MEMORIAL INSTITUTE, Columbus, Ohio Page 52- and

56 / "IRE Transactions On Reliability And Control", I960, April Pages 23 - 24. ^v added. ■

It must therefore be stated that the known facilities are not in are able to fully test all parts of the circuit under test. In addition, they require extensive additional equipment that is included in the Circuits to be examined must be inserted. In the Areas that can be verified by this type of technique can affect the accuracy fault localization to the identification of certain components (e.g. B, a transistor) which is the cause of an error in the operation of the circuit. In an existing electronic Data processing system in which the circuit elements are based on individual interchangeable cards are mounted, the use of this limited technique cannot be used to check and for all sheep cards When testing a single circuit board, these procedures are too precise. While

Docket PO 7816 2 O 9 8 4A / 0901

. ■ - BADORfQiMAL

-5- W2U1S

It is desirable to check each circuit card, but it is unnecessary to determine the specific ß; 3meiexEL, en.t 'which caused an error.

It is therefore the task of the invention to provide a device for determining the location of the fault to indicate for errors that arise during the operation of an electronic data processing system, without this system thus having to rebuild, so that the adaptation to extensive additional Error detection devices can be produced.

Another object of the invention is the automatic and rapid localization of errors in an already existing electronic data processing system s system star.

Another task is then to localize errors both in the logical elements as well as in the assigned control elements of this Systems.

For a test device in electronic data processing systems for the automatic detection of faulty components with a test character sample source, a memory for storing the expected output errors and a comparison and display device, the invention consists in that the test device also consists of a number of input and output circuits, which part of is to be tested, functional unit, wherein the controller of the test equipment is connected via the other cable with these groups, reset signals transmits, to the reset circuits before the test pattern signals, it first checks and if they corr €: kt ai ^- BEITEN with these circuits, the logical circuits of the?, u checking functional unit checked.

209844-090

we the invention on the basis of a .by drawings Ausfihrungsbeisp levies described in more detail. Show it :

Fig. 1A is a block diagram of the test system, including: -

lent to a unit to be tested,

Flg. 1 B is a block diagram showing the facility

shows those for testing the in Fig. 1 Λ shown System serves .. '■ - "

Figure 2 A is a schematic diagram showing dor to

testing unit,

Fig. 2B is a pulse diagram in the circuit according to

Fig. 2A signals used,

3 shows a basic circuit diagram of the control circuits and

Figures 4A and 4B.

(Sheet-Ί +2 a detailed circuit diagram of a version

from Flg. ^ Bzu-

saramengenoinnien) of the circuit according to Fig. 2 A.

.. 3AÖORK3INAL

20 984 4/090 1

GENERAL DESCRIPTION

1A shows a typical electronic data processing system. This system is for illustrative purposes only; it is intended that the invention can be used by any electronic system. Although input channel A 104 has been selected as the part of the electronic data processing system that is to be tested, but the invention can also be applied to any other part of the illustrated system. The electronic shown in Fig. 1A Data processing system contains data flow logic and controls 100, consisting of a central processing unit 101, Maintenance controls A 102A for testing input channel A 104, maintenance controls B 102B for testing input channel B 106, if desired, and other maintenance controls not shown here for other parts of the system to be tested. The central processing unit 101 can be any general purpose electronic data processing system with a memory program. A set of console lamps 103 on the console for the operator the central processing unit 101 is thus assigned the operation of the electronic data processing system visually can be monitored.

The Datenflußlogik- and controls 100, 'and is connected via data and control cables 109, 110 11 ^ with ^OEEM input channel A 104 and channel B input 106th These cables consist of several data and control lines, which are shown in Fig. ΊΑ by continuous lines Docket 7816

209844/0901

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are presented. Such cables have already been proposed wordc-n (v-.i Patent application US J 27 S19). The input sampler for simulated Data of cable 110 and output bus ^ for logical Signals are shown in phantom to indicate that between a central processing unit and the one on it connected channels are usually not provided, but only for the purposes of the inventions described here be used. The input device 105 and the magnet » Ribbon unit 107 are just examples of peripheral devices associated with input channels 10Ί and 106 can, and are not further described here. Of course, output channels could also illustrate the invention equally well *

On the basis of the Flg. TB v? The use of the roped units in Fig. 1A for troubleshooting will now be described in detail. A sequence of binary input characters is delivered to the data flow logic and controls 100 via the input bus for simulated data in the cable 110 from the maintenance control A 10 2A. The maintenance controller A102A can form these characters from manually operated switches in the maintenance controller A 102A or on the operator's console. Another possible Q ₁ line for binary input characters is the central processing unit 101, which in turn can receive these characters from an associated memory or peripheral input device. The blue input signal brought in via the aforementioned input bus in cable 110 contains a reset signal for actuating the normal reset circuit arrangement of the input channel 10 '.

BAD ORfQINAL Docket 7816 209844/0901

The output signals of the input channel Λ 104 are transmitted by means of a Output line 11j5, which is sent to the maintenance control A 102A of the data flow logic and controls is connected. These monitored output binary signs are compared to predetermined ones Output characters that come from your table 150 in the middle of a comparator 16Ο. The maintenance control A 102A can be the central processing unit 101 both as a source of predetermined output characters as well as for comparison purposes or additional components may be provided as part of the maintenance controller A 102A. The predetermined output binary character can also be graphically presented to an operator which then manually execute the comparison operation.

· ■ '■' ■■■■ »

leads to detect faulty circuits.

Let us now briefly discuss the methods involved in the automated design of electronic data processing systems in order to show their specific applicability to the plague to explain defective circuits by means of the invention. A detailed A description of these processes can be found on pages 127-14O of the "IBM Journal of Research and Development" from April 1964 (Volume 8, No. 2). The building blocks of the illustration Serving electronic data processing system are electronic circuits mounted on individual circuit boards. Each circuit board is replaceably mounted on a larger terminal block, one of the large groups of circuit boards and performs one or more elementary logical functions. When constructing an electronic

Docket 7816 209844/0901

The designer initially refers to the data processing system the elementary logical functions (e.g. and, or, etc.), are necessary to perform the desired operations. At this single-wave;! construction becomes the logical one to be executed Functions in general without special consideration of the species and catfish indicated in which these functions of the dem. constructor in the form of available circuit boards will. A typical example of such a logic circuit is shown in Fig. 2A and will be described later. Thereafter will the first circuit of the structure - .: ri? on special Coordinate paper redrawn, whereby each function is assigned its own coordinate. Operators provide punch cards for each coordinate that the function to be executed < identify and read these cards into a computer. Of the The computer is programmed in such a way that it reads the punched cards and assigns the functions to the circuit boards available as building blocks. Indicating connections between the circuit boards and prints a new schematic * Selected parts of a typical circuit diagram made by a computer in this way are in Flg. 4A and 4b. This schematic identifies the functions performed and the physical location the circuit board, which contains the elements for executing such Carry functions.

1A and 1B thus illustrate the structure of an electronic Data processing system that can be tested for troubleshooting.

. : ■■■> ■ ' ■; ^; . BAD Docket 7816

20984Λ / 0901

As a result of the procedures used in designing the system Is it possible to identify the function that is faulty and thereby identify the circuit board performing this function. - '..'.

PRECISE DESCRIPTION

The system shown generally in Figs. 1A and IB is now in each .. explains to illustrate the operation of the invention. The input channel A 104 is shown in more detail in FIG. 2A, and the maintenance control Λ 1Q2A is in Fig.> In one

individually illustrated.

Input channel A. FIGS . 2Λ and 2B show the circuit diagram of a circuit serving as an example for executing the functions of an input channel and the signals present in the circuit during operation. The circuit is for illustrative purposes only. The circuit diagram of FIG. 2A does not, however, indicate the physical allocation of the functions which are carried out on the circuit board modules. As will be seen, the circuit of Fig. 2A is repeated in the wiring diagram of Figs. 4a and 4B to enable incorrect functions due to circuit faults to be identified so that the circuit boards performing those functions can be interchanged. , -

Docket 7816 20 9844/0901

The input channel A 104 receives data via a data input signal line 1ö8 (Pig. 2A), stores the data temporarily in an A ^ Reglster 200 and then transfers it to an O register 201 so that further data can arrive via the line 108 and in the A- Register 200 can be stored. The data consist of binary 1-uria O bits in any order and grouping. Here, for example, the registers 200 and 201 each comprise a plurality of flip-flops 202 etc. and 203 etc. for storing a plurality of binary characters, each consisting of a plurality of bits. When the central processing unit 101 is ready, the information in the S register 201 is taken from the data bus trunking of the cable 110, and the B register 201 is now free and can be filled again from the A register 200. In this way, the input device 105 can input information into the A register 200 at one speed and the central processing unit 101 can extract data from the B register 201 at another speed, that is, _# the input device 105 ^u * ^{1 (i} the central processing unit 101 work independently of each other.

A group of "bistable" flip-flops 209 to 21Λ controls the input and extraction of data in - .. that or from the A register 200 and into or from the B controller 201 in order to delete data by forcing a cooperation between the independent input device 105 and the central processing unit 101. Each of the flip-flops 209 to 214 has a 0-bit output, a 1-bit output, a setting input S and one or more Blickstcilleirigänge R. if a is a 1-Blt signal representative appears at the set input, η V appears - ₇ οι / - '209844/0901>"^ Docket 7816 ■ _\; ,. ^; .- -v, BÄDOBIfflNAL-

a signal representing a 1-bit at the 1-bit output. When a * 1-bit representing signal appears at a reset input, ' a 1-bit signal appears at the O-bit output of the Plipflops, - All flip-flops are triggered by a 1-bit signal on the Reset input line of cable 110 at the same time In. the idle state brought. AND circuits 215 to 221 are provided, each of which occurs when signals representing a 1-bit are present on (see lines 24 and 25, page 12) to an output signal one of the inputs of the Plipflops 209 to 214 send »The Inverter-" Terminal 222 receives a signal that is either a 0 or a 1 bit and returns it to the opposite position which is then fed to the reset input of the response flip-flop 211. The delay postures. 223 to 226, 242 and 243 ' delay the signals fed to their inputs in order to avoid the occurrence of conflicts in the in Flg. 2B. The exact amount of these delays is generally not critical. It is only critical where it is shown in FIGS. 2A and 2B has been expressly stated.

The operation of the circuit of FIG. 2A will now be described below described with reference to Fig. 2B. The AND circuit 290 is in the activated in the manner explained below to the data input bus of the cable 108 to the OR circuit 241 to connect. When the input device 105 puts data on the data input trunk of the cable 108, it also sends a signal for data signal input see 1 direction of cable 108 at time 275 to indicate that information on the data input collection of the Cable 108 have been molded. Vienn is believed that this is the

Docket 7816

The first data group (character) received is * the gate circuit 206 is actuated in order to transmit the data through the OR circuit 241 sum A register 200 au. The blookdate flip-flop 209 and the A- "full flip-flop 210 are set in the order named (and the A-controller 200 is set back) in order to prevent the entry of further information and to indicate that the A-register 200 If it is assumed that the B register 201 is initially empty, as indicated by the B full flip-flop 212, the torso posture 207 is actuated to transfer the data from the A register 200 to the B register 201 The B-full flip-flop 212 is set to indicate that it contains data, and the A-full flip-flop 210 is then reset to indicate that the Α register is again empty and ready for further information to be received ready. The response flip-flop 211 has been set simultaneously with the A full flip-flop 210 to give a signal on the response line of the cable 108 and thereby indicate to the input device 10 $ that the data has been received on the data input bus of the cable 108 and can now be taken from this line. When that happens, how to do it. Time is indicated 276 by the removal of the signal from the data signal input line of the cable 108, the response flip-flop is reset 211 and thus causes the resetting of the block data flip-flop 209 via the AND circuit 216. Venn further information from the input device 105 to the Are available, they are placed on the data input trunk of cable 108 and a signal is sent on the data signal input line of cable 108 and entered into the A register 200 as described above.

■ '"" ■■■ ■ -'"'■·' ■ • ■ ■; -.::va -'O. - ■■ 2 0 9 8 4 Λ / 0 9 0 1 - ':

Docket 7816 ■ "'" ■' ■■ '.

If the B-full Fllpflop 212 is set to indicate that the B-register 201 includes data, a signal of the cable 109 # is displayed on the operation request Aüsgangsleitung communicated to the central Verarbeitungaeinheit 101 ■■ "means that data from the B - ^ Register 201 are available.

If at time 278 the central processing unit 101 is ready Is-t>. To receive this information, it sends a signal to the operator input line of the cable I09, whereby the CPU servicing flip-flop 215 is set.

After the flip-flop 213 has been set and such a signal has reached its 1-bit output, the inverter circuit 230 makes a determined by the delay circuit 226 Delay the AND circuit 219 ineffective.

When a clock signal occurs on the clock signal input line of cable IO9 at time 279 actuates the data control flip-flop 21Λ the gate circuit 208 to activate the im

Docket 7816

0984Λ / Π90 1 ^ DORfGiNAL

B - Register 201 contains information about the data output bus of the cable 109 to the central processing unit 101 to be transferred. After that, that will Data control flop 214 reset, and after a delay determined by the delay latch 243 become the B full flip-flop 212, the CPU service flip-flop 213 and the B register 201 reset. ϊίύη will just be described operation is repeated.

It is further assumed that the circuit arrangement described so far is normally present. To illustrate the invention, an additional circuit arrangement, shown in dashed lines in FIG. 2A, is required Data input line 244 of cable 110 is inserted. A signal on the simulated data signal input line of cable 110 indicates that data is present on bus 244. This information is received from the maintenance controller A 102A via the AND circuit 291 with the exclusion of information from the input device XO ¹ J when a signal on the simulation mode line of the cable 110 activates the AND circuit and the AND circuit via the inverter circuit 229 Circuit 290 makes ineffective. The AND circuit 22? makes when signals appear on the simulated data signal transmission line of cable 110 and the simulation mode line 0c3 D ocket 7816 .- ■ '■■ ^'

-..-. ; ■■■■■■■ ^ r, a, ^; : · Ι

■■■■ .. ■■■■■ "- ■■■ ⁰ ^ ORHNALl:

20 9844/0 901 "'

Cable 110 via the OR circuit 240 and the AND circuit 215 die, gate circuit 206 effective in the same way as it is described above in connection with input device 105 has been. The signal on the simulation mode line of the Cable 110 blocks the AND circuit 2 ^ 51 because the inverter circuit 229 uses the signals on the simulated data signal input line of the cable 110 allows the input channel A 104 to the exclusion of all signals that may be on the The data signal output line of the cable 108 is present. The signal on the timing control line of cable 110 is typically, ■ thus the signal from delay line 242 through the AND circuit 228 can reach. If the maintenance controller A 201Λ is used to operate the input channel A 104, it is machinal expediently, the AND circuit 228 to cause the output signal of delay circuit 242 to block (by eliminating of the signal from the clock control line of cable 110) to display the states of flip-flops 209 to 214 and registers 200 and 201 ' to investigate «■

The maintenance controller A 102A is given access to the selection of normally available input signals to the input channel A 104, which are indicated by circles with the numbers "1" through "7", in order to select normally available output signals, represented by the circles with the designations "AS", "Ale", "C14", "C22", "Dip"., - "EU" and "E25" (Fig. 4) are identified. As will be explained in detail in connection with FIGS. 4A and 4B, the output signal labels identify the circuit board, Docket 7816 ■ '.' ■■ '. *' ■■.

BAD0RK3INÄL

209844/0901

•. , ■:. ■ -18-:

on which the function indicated in FIG. 2A is executed Circuit is located.

An exemplary embodiment of the Wa Steuerurig A 102A will now be described with reference to FIG. Although there are several alternative sources of the binary supplied to input channel A, the exemplary embodiment described here receives them either from the central processing unit 101 or from manually operated switches 32T to 52β, which are assigned to a battery;> 20. Likewise, the binary output characters received from the input channel A can be transmitted to places other than the central processing unit 10 (see Fig. 2) and the console lamps 10;} (see Pig. IA) ... For the present example it is assumed that that the central processing unit 101 supplies clock control signals A and B from its read-only memory, which are fed to the gate circuits 301 and 305 so that the gate circuits JO3 can first supply a binary input character and then the gate circuit 501 can receive a binary output character. Binary input characters, which consist of four signals, namely jerk signal, clock control signal, simulation mode signal and simulated data input signal, are fed from the memory data register in the central processing unit 101 to flip-flops 304 to J507. A character is also transmitted to register 512 via cable 2513. If the signals represent a 1-bit, do ·; corresponding of the fiipflops J04 to 307 and the -.Flipflopetellon \ of the register 312 are set to the 1-bit state in order to receive signals ^ .f Docket 7816.;. . .. \ ^; - ^: '.. ■■;' ■.,.

20S844 / 0901

the corresponding "output lines in the cable 110 leading to the input channel 104. If a signal representing an O-bit is supplied by the memory data register," the corresponding inverter circuit OB to 307 represents the associated flip-flop 204 to 307 into the ffl-bit position. These lines, together with the clock signal input and operator response input lines from the central processing unit 101, form the binary input signal pattern that is used by the input channel A 104 for troubleshooting.

The maintenance control A 102A receives binary output characters from the output main line 113. These characters are transmitted via the gate 301 to the storage data register of the central processing unit 101 together with an additional parity block, which is sent to check spots by a parity generator 302 as a function of the binary. Output character on line 112 is generated. . "-....

How it works

The mode of operation of the invention will now be described in connection with FIGS. 4A and 4B described, which contain a wiring diagram represent the connection between the elements for performing the circuit diagram & function of Fig. 2A Circuit boards and, their location represents. The deficit numbers of the blocks in Pig. 4A and 4B ■ correspond to those used in Fig. 2Λ. Where a block in FIGS. 4A and 4B does not have such a designation This is due to the germs of the circuits used Docket γΒΐ-6-.

BADORHSfNAL 20984A / 090 1

and not due to the functions required in Fig. 2A. Z, B, are each of the delay circuits used erx (D) ohtni- • see financial statements (RT) in order. Occasionally a block leads in Pig ·. 4a and 4B perform several of the functions mentioned in Fig. 2A, and in other cases several blocks are required in Figs. 4A and 4B, by a single one represented by a single block in FIG. 2A Function. For example, in Figures 4A and 4B there are two ANDs (A) necessary, to perform the operation of a single flip-flop in Figure 2A.

The following table A shows the functions that go through identifies the letter in the upper left 'block of Figures 4A and 4B will:

Table A. and A. Delay (driver / vaccinee) D. Or / inversion N register PH Ohmic termination RT Time Delay TD

The output of each block in Figures 4A and 4B is represented by either a positive (+) or a negative (-) sign indicating the 1-bit signal word. Each Gohaltuncska ^ which carries the blocks symbolically shown in FIGS. 4A and 4B, Docket 7B16 ■

209844/0901

is identified by a four-character card name. For example, one can find in Pig. 4A, the OR circuit 229 on the Schaltwngskarte A1B2 "Besides, identified in Fig. ^S U \ and 4B each Logikblöck by its own consisting of awei or three characters name, for example-did-or Schaltuns 229 through B2. There can be several logic blocks on a circuit card. SB contains the card A1B2 the log blocks E2, Bo, G3 * C4, C5 and E10.

In the following work description, binary input characters marked as follows *

Rules of the cable “10% and 110

ί 2345.67. ■

and binary output characters are given in the following order ι

the Sainniell eitunp; 11 ^

AS Al 8 C23 Ct4 D28 D10 E25-Et4

Back / 3 te l l

According to FIG.>, The B-clock control supplies a signal from the memory in the central processing unit 101 to actuate the gate circuit ~ J> Oj, so that three binary ßincane; fed from top to bottom:

Reset test 1

0 0 10 0 0 1

1100001 "■■■ '...

00 ₁ 0001. ■ »■« «■« «.

Docket 781G ' '

20 9844/0 90 1

As you can see, there is only one data bit in the first column for the simulated data input line of cable 110 is shown, where it is understood that several such lines can be provided. The binary output character on the output lines of the> Manifold 11j5 must of course completely consist of O-Blts, .because the third binary input character supplied is a 1-bit has contained in the reset position 2. In any case, according to Pig. 3 the binary starting point through the occurrence of a B-clock signal from the Pestwertspeieher in the central processing unit 101, which causes the output binary character along with a parity bit to be entered into the Memory data register is entered.

■ .'- ■ - - ■ "» ■

After that, the above operation is given for each of the below Repeated further tests, with the initial character listed in each character.

Reset test 2 1 1 0 0 0 0 1

1 1 0 1 0 0 1 "1 10 0 10 1 010 0 0 0 1 0 0 10 0 0 1

Reset test; 110 0 0 0 1

ι 1 οι ο ο τ ■ ■. ;

110 0 10 1 0 1 0 0 001 0 1 0 0 0 0 1

0 0 0 0 0 0 1 ^{; /} ** \

209844/0901

0 0 10 0 0 0 Docket 7816

Back part test

0010011 ι ι 0 0 or 1

• 1 10 1 0 11

00 1 0 0 0 1

Residual inspection 0 0 10 0 1 1

1 10 0011 110 10 1 1 110 1 0 11 11 0 0 1 1 1 110 0 0 11 0 01 O 0 0 1

Reset check 6 0 0 1 0 0 1 1 0 10 0 0 11 0 0 0 0 0 11 110 0 0 11 0 0 0 0 0 1 1 0 0 1 0 0 0 1

Reset check 7 0 010 0 01 0 001001 ooi öoο 1

Docket 7o16

20984.4 / 0901

The binary output characters; from all seven reset exams -are then, according to their recording in Öder-Poria, with each other ties. The Qder-VeFverbindimg can also be done by recording the output characters in the same register, so that after the seventh Check the register contains a 1-bit in every position in which one or more of the output characters contained a 1-bit. if the Reset circuit of the ^ input channel A 104 in the correct operating state was, each of the binary output characters should have contained all zeros, and the OR function of the six output characters should also only consist of zeros. If in any place the binary output character linked in or form has a 1-bit, the position and the number of 1-Blts indicate the circuits, which are responsible for the failure. The table below B indicates the circuits that caused the failure. In Table B does not list all possible variations of the in-or-form linked characters are listed because only those characters have been selected that would occur as a result of a single error (as opposed to a multiple error).

Table B ,

Back t e11 test Output character pattern

0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Docket 7816

Error list

No error detected A8 +, Bö-, A4-, hj> +, B> f-Ai8 + i B18-, Λ16-C25 +, D2> -, C21-, C20 +,

, C1β +> C17

© AD0RK31NAL

u / 0 90

RÜc lcate J. 1 pru fun g ~ Fchlerliste;

Au slangs ?, Ρ1 n he nirr us t. e r

O 0 1.1 0 0 0 0 CH +, DH-

0 0 0 0 10 0 0 D28 +, E2 & -, D27-

0 0 0 0 0 1 0 0 DIO +, £ 10-

00 0 0 0 0 10 E25 + / F25-, E2>

0 0 0 0 0 00.1 EH +, FH-

0 0 110 0 0 1 ci> -, era +, cn +, cio +

0 0 110 10 1 C9-, C8 + ', C7 +, C6 +, C5 ~ * C4 +, C ^ -,

That on the name of the logical block in the error list The following sign indicates the direction in which the circuit has failed »E.g. a" + "sign means that this has been met - ;. · Circuit output signal a negative signal instead of a positive one. Signals should have been. .

If a 1-bit appears in any position of the binary output character shown in Table B, the error ends because the location of the error has been determined. For example, if a T-bit appears in the second column (A18), this is Logic block Al ν B18 or A16 the cause. By removing the circuit boards A1F2 and A1G3 that carry these circuits, this error is corrected and the electronic data processing system can work normally again. If, on the other hand, the exit character r.:; ·· consisted of O bits, the error has not yet been determined.,. vjorden. In this case, however, it has been established that the reset circuit is operational and can then be used for further "v" function of the input channel A 104. Docket 7816

209844/0901

Progres s ive s test: ■ -. '' - ".

After the reset circuit arrangement was switched off as a source of error- it is possible to use additional input characters -yorsu-

see in order to determine the error in the logic circuit arrangement with the help of the reset circuit. With some sequences of input patterns it is advantageous to first reset the logic circuit arrangement and then to supply further binary input characters without intervening resets. For each sequence of binary input characters there is a correct binary output character and a group of incorrect binary output characters which indicate the respective failure modes Reset circuit. Λ ^k

According to FIG. 3, the B-clock control signal causes the read-only memory the central processing unit 101 that the data from the Storage data registers are passed through the gate circuit / 3OJ5, so in connection with the clock signal input signal and the operating speaker input signal, which also come from the memory data register, two binary input characters on the cables

109 and 110 to Flg. 4A and 4B to send / as follows:

Progressive Exam I. '. ""' ■ '"- ■

ο ο to ο ο 1 ■. / ■■■ '.

110 0001
Docket 7816

- ■■. '■. ■■'. ■■■ / ..; BADORfQlNAL

209844/0901

Danaeh causes an A clock control signal from the pest value memory in the central processing unit 101 that a binary output character appearing on the "Log" output signal line 115 passes through gate 301 and in the memory data register the central processing unit 101 is stored. This output binary character is then combined with the following Table G compared using one from the central Processing unit 101 performed operation by a printout process for subsequent independent comparison with the failure list or by display on the console lamps 103 for comparison with a failure list by the operator.

Table C.

test

From gangs drawing pattern

1 11 0 0 1 0 1

0 0 10 0 10 1 1010 0 1 0 1 Ό 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 1 01 10 010 1 0-1 110 10 10 1

List of errors

No error detected A4 +, A>, B6-, AS A16 +, A18-, A15-, B18-, B18 + C5 +, C4-, C>

C6-, C7-, C8-, 09+ C10-, - C11-, C12-, C13 + C14-, D14 +, G27-, G26 +, G25 +, G24 +, G22 B15- »C17 +" ---- C2>, C21 +, C20-, C19- / C18-

Docket 7816

BAD OFUOINAL

209844/0901

Test; Error list .

Out of rank pattern
1 1 1 10 10 1 D15 +, E6-

1 1 1 O OO 0 1. E10 +, D10 1 1 1 0 0 1 0 0 ET4-, F14 +

110 0 0 10 1 D2> i-

If, according to the first line of this table, the binary output character does not show any errors, the next test in the series is namely the progressive test 2 carried out. If, on the other hand, one of the If any of the above characters occurs, the source of the Error detected using Table C above, the troubleshooting operation finished and the defective circuit card (or circuit cards) replaced.

Subsequent progressive tests are also carried out, and that binary output character that is obtained from each sequence of binary input characters for each test results is used to determine '.' whether an error has been found and whether the next debugging test should be carried out. Every time one finds the Signs that represent errors do not result in any further checks carried out if all of the following tests are not found executed after an error, the error was either volatile * or several balancing errors have occurred. The remaining Progressive exams are:

Docket 7816 .

BAD.QRieiNAL 2098U / 0901

1SIMf

-29- - ■ '"

1 1 .0 0 0 0 1 1 1 # % φ φ 1

ΐ ι φ φ 1 φ ί «io- ί> θ ο α

3. ·

0 0 10 0 11

1 1 0 # O 1 1 11 0 10 Π

1 1 cO 0 Ω 1 1

ο St. 0 1 1 i> J'C # 11 U φ # .4? #) U Λ 1- -C Φ jl ^ Prüfui > H > © ^a ff 7

O Ö 1 Ö fl O 1 0 O 0 1 0 Φ 1 The failure lists for selected binary output characters that result during each progressive test can be seen in the following tables D to I / correspond to tests 2 to 7:

Docket 7616

209844/0901

Il 1 1 φ tt ft

ι Ii ι # φ i ι ■ '# ■ 0 110 11 ι ι Table E Examination?

1 1 1 0 1, 0 1 0 1110 1110 Table P test; 4th

Ausfiangszelchenmustcr 1110 110 1 ι ο © φ # i ϊ © ι 1 111 © ti # H 1 0 0 0 0 10 1

Table G.

Exam 5

Output character pattern

1 0 0 0 0 1 0 1 1 1 1 0 1 1 j 1 1 1 i JO 1 1 äO 1 1 1 0 0 0 1 # 1 Docket? 816

Kei®

srrnitlbelit

Keim Denier «rattelt

, 022+

Table H '. Check 6 output characters 1 0 1 10 10 0 1 1 1 0 0 0 0 0 10 10 0 0 0 0

Table I Test 7
From & angszeichenmuster

0 0 0 0 0 0 0 0 00 0 0 1 0 0 0

Error list

No error detected B15 + D15-

Error list

No error detected C27 + # C26-

Eg it has been shown how an existing unit in an electronic data processing system, such as the input channel Λ 104 A, can be quickly checked in order to determine the location of errors without additional great technical effort being required. With this method, not only the logic circuits are quickly tested, but also the associated control devices, in particular the reset circuit, which makes it possible to use the tested circuit when testing the remaining circuits that have not yet been tested. The binary input and output characters used are obtained individually for each circuit by assuming a set of binary input signals and then determining the possible binary output characters that result from each possible failure of circuits on the path of the assumed binary input character. It's Docket 7616- '

BATH
2 0 9 8 A Λ / 0901

not -necessary to use any modification of input characters as long as each output signal of each logical block once by means of a binary input signal is checked. So if that goes through logical blocks affected by each binary input character the remaining unchecked logical blocks give the remaining binary input characters that are necessary., In the above Operation shows the following table J that the binary input characters check every circuit ι

Table J

More logical A the end More logical A the end More logical A A. block block block A3 R. 1 011 R. 1 EG 1 A4 1 R. 012 R. 1 E10 1 R. A8 R. 1 co 1 R. E14 R. 1 A15 5. 1 014 R. 1 EI8 2 2 A16 1 R. 017 1 R. El 9 2 CVl A18 R. 1 018 R. 1 E2Ö 2 2 A29 - - 019 R. 1 E21 2 2 B1 - - 020 R. 1 E2 J5 2 R. B2 - - mm: 021 1 R. E25 R- 2 B3- R. - _: 023 R. 1 E28 2 R. B6. 2 R, 1 026 2 7th FI4 1 R. BI5 6th 1 027 7th 2 F25 2 R. B18 1 R, 1 Dl mm G18 5 4th 1 R. Dj5 - R- GI9 5 4th 04 R. 1 .DI0 R. 1 G20 4th 05 1 R. D14 1 R. G21 4th 5 c6 R. 1 D1 <j 1 6th G22 5 1 07 R. 1 Ό23 1 R. G24 1 5 Cb ' R. 1 D25 - .2 1 VJl 09 1 R. D27 2 R. G26 1 5 010 R. 1 D28 R. 2 G27 ! 3 1

Table J shows that each logical block ¹ is tested both at its training as well as on its state Eln-out in one of the numbered tests or in the RückstellprUfung R. The dashes refer to logical blocks that are outside the test area and cannot be tested.

Docket 7B1 6

209844/0901

152417S

Bim 3? © .i "t; © i? 4äs ¥ tei * jRatorsäa. Zmm BfrfciyJjptoelia. © Ines theorem of Sliiipaass * -» Nä ilus ^ fflgsseietten ¥ © rs £ ind © t eins luboils Steil i Table J, «fre- iäer ■ lo ^ isöhe Blosk i »d © r -zii prilfeindej

j, all mossllQhoii Mmamllwigen von lainSrea i aaagalleferfc "-iiM the see from every mS.glfchen Ans- lßlircn ifoisgaiigszoioliioa vierdsn'developed, The PrU-those." Jas Fersa ^ en-Each logisGiiciio Blocks found jji one, "Mst then i , such as »B * table J,

To avoid duplicates, - the essential.-binary '32ii: the initial characters and the resulting binary output characters can be selected * by excluding all but one pair for each logical block. Such a procedure can be carried out by appropriate programming of the electronic

'■■ - ■■ - - ■ - *.

l see patent processing systas, - so that there are all variations;

binary input characters and the resulting binary developed by making it all possible

Docket 7Ö16

20B844 / C19Ö1

Claims (1)

■ - 34 - \ I PATENT CLAIM Priieiiirrichtung in electronic Datenveraituttgsaiuagen for the automatic detection of faulty components with a test sample source a memory for. Storage of the expected output pattern and a comparative utid display device, characterized in that the test device also consists of a number of input and output circuits (241, 202, 203, 209, -to 214; FIG. ZA) which are part of the to testing functional unit (z. B. 104; Fig _{. 5.} 1), the steaerut {102) of the test device is connected to these circuits via special cables (110, 113), reset signals before the test pattern signals to the. Resetting circuits transmits, checks them first and, if they work correctly, further checks the logic circuits of the functional unit to be tested with these circuits. : '■' "BADORiüSMÄl 2,984 / 090 1 Blank page