DE19524925A1 - Address conversion system for memory management unit - Google Patents

Abstract

The address conversion system allows a virtual address of a virtual address space, containing at least one page address, to be converted into a corresponding real address of a real address space, containing at least one page address. The virtual and real pages each correspond to a base page or a multiple of a base page and may have different sizes. The virtual address is used to address a memory with a number of entries, each designated by a label entered in a label field and having a data field holding at least one real page address and a page size identification field for the real page. When the label held in the label field corresponds to the virtual address the real page address held in the data field and the real page size read out.

Description

The invention relates to a method for implementing a virtual address into a real address (also physi address). An application example of the invention is the memory management unit (hardware) also MMU (Memory Management Unit) called, among others the address in virtual memory into an address of the physical or real memory is implemented.

MMUs (Memory Management Units) are the hardware ones Basis for virtual storage, address spaces, paging and Protection mechanisms. They are therefore for all applications significant that operate with large amounts of data (esp especially in distributed systems or supercomputers) and / or Security properties on complex structures Objects.

Conventional MMUs typically share virtual address spaces usually in 4 KB or 8 KB pages. The Ab formation of virtual on real addresses happens  neither with multilevel page tables or one Inverted page table. Usually the address still set by a TLB (Translation Lookaside Buffer) or virtual cache accelerated.

Inverted Page Tables (and also many multi-level Page Table procedures) conventionally leave only one uniform page size too.

With conventional page tables, a virtual address is implemented in several stages. Each level works with a page table, the entries of which either refer to page tables of the next level or (in the last level) to data pages. Page tables and data pages generally have predefined sizes 2 ⁱ .

A conversion font of a virtual (binary) address v using a page table with the address p is considered below with reference to FIG. 3. For this purpose, v is split into a higher-order part u (consisting of a certain number of higher-order bits) and a non-significant part v '(consisting of the lower-order bits). An entry in the page table is then selected by means of u, which includes, among other things, a new address p ′.

Inverted page tables consist of one entry per tile of real memory, each of which contains the virtual address of the assigned page of the virtual address space. Is accessed using a hash function (see Fig. 4).

When the virtual address v is converted into the real address r, the low-order part w is taken over directly. The higher-value part u is mapped to a value p by the hash function, which both identifies the presumed tile in the real memory and is used for indexing the inverted page table. If the corresponding entry contains the correct virtual address u, there is a hit. Otherwise (not shown in FIG. 4), further tiles must be examined by means of rehash or chaining, until a hit is obtained or a decision is made on page fault.

Hashed page tables (see FIG. 5) are a variant of the IPT, although not every entry is permanently assigned to a physical page, but each entry contains the physical address of the corresponding page.

For cost reasons, not every memory access of a program that parses the MPT or IPT or HPT the. This overhead is done with the help of a special Avails address translation caches, a transla tion Lookaside Buffers (TLB). Usually there will be more than 90% of all address conversions at zero cost TLB hit done. Only with a TLB miss will they Parsed page tables.  

Conventional TLBs typically range from 32 to 256 Entries, each of which is the address translation of a Page describes d. H. a page address of the real has memory. They are partially fully associative, but often only 2 or 4-way associative.

Conventional n-way associative TLBs operate via only with a uniform page size.

The invention has for its object an address implementation process to create multiple page sizes supported in the virtual and real address space.

In particular, on the basis of Hashed Page Tables (HPTs) or Inverted Page Tables (IPT) an MMU constructed using multiple page sizes supports. Variants should also be possible for others Page tables can be used.

To solve this problem, a method with the Features of claim 1 and claim 4 proposed. Advantageous embodiments of these process variants are specified in the subclaims.

The method according to the invention is used for implementation a virtual one having a page address part Address of a virtual address space that is divided into several virtual pages with virtual page addresses under is divided, the virtual pages one or many times a base page of a given size and can be of different sizes in one side real address of a real address Raums, which consists of several real pages with real pages addresses is divided, with the real pages or multiples of the base page are different  can be great. It applies that the size of a virtual page equal to the size of the associated rea len side. Different virtual pages can be of different sizes; the same applies to the real ones Pages. For all sides (real and virtual) applies that it is a single or multiple of a base page are.

A memory is created using the virtual address addressed several memory entries. It points each memory entry is a checkbox for one Tag and a data field for at least one Page address part of a real page address and a Page identification field for the size of the real page with the real page address stored in the data field on.

If the marking of the marking field matches of an addressed memory entry is replaced with the virtual page address part of the virtual address real page address based on the content of the Data field and the page identifier field determined.

When examining the virtual address for About in line with the marking of the marking field each addressed memory entry will in particular the relevant number of the most significant bits of Marking and virtual address compared. In the "relevant number" is the difference of the Bit length of the virtual address and the 2 logarithm by the page identification field of the respective Memory entry specified page size.

It is preferred in the event that none of the markers against the checkboxes of the addressed memories  sluggish with the virtual page address part of the virtual Address matches using the virtual base page address part of the virtual address a page table parsed. In the event of a hit, the page delivers Table the real page address part of the real address and a value for the size of the real page. The vir current page address part of the virtual address, the real page address part of the real address as well as the value for the size of the real page are in the markie field, the data field or the page identifier field an entry of the memory (TLB) registered.

In a variant of the above method, the real and virtual pages a maximum of one Size on (maximum size). The pages can be the same or smaller than the maximum size. With this ver one will drive using the virtual address Inverted or hashed page table with entries parsed. Each entry in the page table has a mar for a virtual page address part Data field for a real page address of the real one Address as well as a page identifier field for a the size represent the real page with the real page address part sending value. By means of the maximum pages size of the corresponding maximum page address part of the vir current address or an image of the same a group of page table entries, in particular selected a cluster of entries. If they match one of the markings in the checkboxes of the Entries of the indexed group of the page table with the by the page size of the page identifier field of each certain entry certain page address of the virtual address is based on the in the data field of the relevant entry of the Page Table saved real page address part, the size of the maximum page and  in the page identifier field of this entry stored value the real address is determined.

Instead of an inverted or hashed page table also a translation lookaside buffer with one of the Number of entries of a group of the same association activity can be used.

Below are execution with reference to the figures examples of the invention explained. In detail show:

An access to a simple Hashed Page Table approximately example by means of a virtual address according to a first exporting Fig. 1 is a pictorial representation,

Fig. 2 is a pictorial representation of associative k hashed page table management, for example by means of a virtual address to a first one of an access to a,

FIG. 3 is an illustration of access to a more stage page table,

Fig. 4 is an illustration of accessing an inverted page table and

Fig. 5 is an illustration of access to a hashed page table.

In the case of a mixed-page-size TLB for a fixed-page-size page table, a page table mechanism with a fixed page size of 2 ^s , for example IPT or HPT, should be specified. These pages are called basic pages in the following.

Furthermore, a TLB is required, which allows different sized pages. Permissible TLB page sizes are the size of the base page and a multiple of 2 ^{s + x} , where x = 0, 1,. . . X can be. These pages are called compound pages.

Each page table entry is expanded by a (data) field t, which defines the TLB page identifier. The base page is part of a 2 ^{s + t} composite page.

Assume that a TLB miss occurs when accessing via the virtual address se v. Then the page table is parsed with vv mod 2 ^s as a virtual page address. In the event of a hit, the physical address p of the base page and the TLB page identifier t are provided.

A conventional TLB would now be one of the TLB entries with

loaded, d. H. exactly described the base page.

Instead, according to the invention, one of the TLB entries becomes With

loaded. ("Mod" is the mathematical modulo function that describes the integer remainder c of a division a / b: a mod b = c.) This means that (larger) compound pages in the TLB also only show one entry per compound page and no longer per base page, ie no longer up to 2 ^t entries. (The current page size can not only happen in the TLB by storing t, but also by derived values, e.g. by a bit mask 2 ^{s + t} - 1.) In contrast, there are so many entries for the in the page table composite page as it has base pages.

In a variant of the above method, p denotes not the physical address of the base page, but that of the compound side:

Compound pages in real memory no longer need to be aligned for 2 ^{s + t} .

In a second variant, the size factor of a composite page is no longer specified as a two-logarithm, but directly. A composite page then has the size 2 ^s t. Each page table entry also contains a field u, which indicates the relative distance of the base page within the page. u can have the values 0, 1,. . . assume t - 1. The TLB entry then looks like this:

(Instead of p - 2 ^s u, as provided in the first variant, p can denote the physical address of the page.)

This can be physically and virtually related Base pages are summarized without the ent standing compound side is a power of 2 as Size factor of a base page and without it must be aligned.

Each of the mixed-page TLBs described above can be also apply to page tables that are already under Allow pages of different sizes (third variant). The can be useful, for example, if the bandwidth the possible page sizes in the TLB is larger than for the page tables.

Realization options

• a) The Paris table page is now also the (variable) size s and thus the current one Base page size supplied.
• b) t alone defines the page size:
• c) Compound pages can only be used for one form certain base page size, for example only for the largest page size that the page table Mechanism allows.

In the following, a k-associative mixed-page HPT will be explained, whereby a simple HPT is first described for better understanding. The largest possible page size is 2 ^S , where S is the bit length of the field w of the S least significant bits of v (see FIG. 1). In this case, -2 ^{s is to describe} a bit string with leading ONE and the last s bits as ZERO, ie a bit string whose s least significant bits are ZERO and whose remaining (more significant) bits are ONE. Conversely, (2 ^s -1) is to describe a bit string with the ZERO and the last s bits as ONE, ie a bit string whose higher-order bits are each ZERO and whose s least significant bits are ONE. AND describes the bitwise logical AND operation.

If v ′ = v AND (-2 ^s ), then the real address r is p + (w AND (2 ^s -1)).

It is important here that with u only such bits of the vir current address v used to address the HPT that are not allowed with a permitted page size belong to tenoffset.

In the k-associative HPT, on the other hand, the hash function not only selects one entry, but a cluster of k entries (see FIG. 2, in which the indexing 0, 1, 2,..., k-1 is selected).

The k entries of the cluster are checked, as shown in FIG. 2. If the cluster entry i results in a hit, ie if the query v _i ′ = v AND (-2 ^si ) returns the value “true”, p _i and s _{i of} this entry are used to form the real address. If there is no hit, the address conversion fails.

With this method z. B. the powers of 2 from 2 ^s down to 2 ^s / k as sizes of a composite page possible, the hit rates are never worse than with simple HPTs.

Smaller page sizes than 2 ^s / k are also possible, but lead to clashes when used heavily, since the k-associative HPT can only accept a maximum of k pages from a 2 ^s- sized area at the same time.

The procedure can be carried out using the methods used at Hashed Page Tables rehash and link methods can be combined.

The associativity can be achieved by completely parallel A cluster is processed. Sequential or partially parallel processing is also possible.

The associativity can be accessed via Rehash / Link Clusters to be expanded.

The Ver. Described above using a mixed-page HPT driving is on a k-way associative TLB turns.

The description follows from the above facts, if you associate the k-associative HPT with the k-way selective TLB replaced. The role of the cluster is then  through the selected set consisting of k entries (Sentence, line) of the TLB.

Claims (5)

1. A method for converting a virtual address having a page address part of a virtual address space, which is divided into several virtual pages with virtual page addresses, the virtual pages being multiples or multiples of a base page of a predetermined size and can be of different sizes, into one page Address part real address of a real address space, which is divided into several real pages with real page addresses, the real pages are single or multiples of the base page and can be of different sizes, in which

• - A memory with several memory entries is addressed by means of the virtual address, each memory entry having a marking field for a marking and a data field for at least one page address part of a real page address and a page identification field for the size of the real page with the real page address stored in the data field , and
• - If the marking of the marking field of a memory entry matches the virtual page address part of the virtual address, the real page address is determined on the basis of the content of the data field and the page identification field.

2. The method according to claim 1, characterized in that that when examining the virtual address in accordance with the mark of the markie field of each addressed memory entry the relevant number of most significant bits of  Marking and virtual address compared the, the relevant number resulting from the diffe limit of the bit length of the virtual address and the Log of two by the page identifier field of the respective memory entry Results in page size. 3. The method according to claim 1 or 2, characterized in that

• in the event that none of the markings of the marking fields of the addressed memory entries matches the virtual page address part of the virtual address, a page table is parsed by means of the virtual base page address part of the virtual address,
• - That the page table delivers the real page address part of the real address and a value for the size of the real page in the event of a hit and
• - That the virtual Seitenadreßteil the virtual len address, the real Seitenadreßteil the real len address and the value for the size of the real page in the marker field, the data field or the page ID field of an entry of the memory are written.

4. Method for converting a virtual address space having a page address part of a virtual address space, which is subdivided into several virtual pages with virtual page addresses, the virtual pages being multiples or multiples of a base page of a predetermined size, not exceeding a predetermined maximum size and of different sizes can be, in a real address having a page address part of a real address space, which is divided into several real pages with real page addresses, the real pages being multiples or multiples of the base page, not exceeding the maximum size and can be of different sizes the

• - an inverted or hashed page table with multiple entries is parsed using the virtual address,
• - wherein each entry has a marking for a virtual page address part, a data field for a real page address of the real address and a page identification field for a value representing the size of the real page with the real page address part and
• a group of entries of the page table is selected by means of the maximum page address part of the virtual address corresponding to the maximum page size or an image thereof, and
• - If one of the markings of the marking fields of the indexed entries of the page table matches the page address part of the virtual address determined by the page size of the page identifier field of the respective entry, based on the real page address part stored in the data field of the relevant entry of the page table, the size of the maximum page and the real address is determined from the value stored in the page identifier field of this entry.

5. The method according to claim 4, characterized in that instead of an inverted or hashed page table a translation lookaside buffer with one of the  Number of entries of a group of identical aces sociativity is used.