DE19580604T1 - Widerstandsfabrikation - Google Patents

Widerstandsfabrikation

Info

Publication number
DE19580604T1
DE19580604T1 DE19580604T DE19580604T DE19580604T1 DE 19580604 T1 DE19580604 T1 DE 19580604T1 DE 19580604 T DE19580604 T DE 19580604T DE 19580604 T DE19580604 T DE 19580604T DE 19580604 T1 DE19580604 T1 DE 19580604T1
Authority
DE
Germany
Prior art keywords
resistance fabrication
fabrication
resistance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19580604T
Other languages
English (en)
Inventor
John G Richards
Hector Flores
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ChipScale Inc
Original Assignee
ChipScale Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ChipScale Inc filed Critical ChipScale Inc
Publication of DE19580604T1 publication Critical patent/DE19580604T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/20—Resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C1/00—Details
    • H01C1/14—Terminals or tapping points or electrodes specially adapted for resistors; Arrangements of terminals or tapping points or electrodes on resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C17/00—Apparatus or processes specially adapted for manufacturing resistors
    • H01C17/006—Apparatus or processes specially adapted for manufacturing resistors adapted for manufacturing resistor chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02371—Disposition of the redistribution layers connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate
DE19580604T 1994-06-09 1995-06-01 Widerstandsfabrikation Withdrawn DE19580604T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US25772694A 1994-06-09 1994-06-09
PCT/US1995/006929 WO1995034083A1 (en) 1994-06-09 1995-06-01 Resistor fabrication

Publications (1)

Publication Number Publication Date
DE19580604T1 true DE19580604T1 (de) 1997-05-07

Family

ID=22977494

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19580604T Withdrawn DE19580604T1 (de) 1994-06-09 1995-06-01 Widerstandsfabrikation

Country Status (8)

Country Link
US (1) US6121119A (de)
JP (1) JPH10508430A (de)
KR (1) KR100358446B1 (de)
AU (1) AU2659995A (de)
DE (1) DE19580604T1 (de)
GB (1) GB2302452B (de)
HK (1) HK1011454A1 (de)
WO (1) WO1995034083A1 (de)

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US6882030B2 (en) 1996-10-29 2005-04-19 Tru-Si Technologies, Inc. Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate
US6498074B2 (en) 1996-10-29 2002-12-24 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
JP3537447B2 (ja) * 1996-10-29 2004-06-14 トル‐シ・テクノロジーズ・インコーポレイテッド 集積回路及びその製造方法
US6448153B2 (en) * 1996-10-29 2002-09-10 Tru-Si Technologies, Inc. Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
US5904496A (en) * 1997-01-24 1999-05-18 Chipscale, Inc. Wafer fabrication of inside-wrapped contacts for electronic devices
AT405591B (de) * 1997-10-03 1999-09-27 Schaffler & Co Heizelement und verfahren zu dessen herstellung
DE19755753A1 (de) * 1997-12-16 1999-06-17 Bosch Gmbh Robert Widerstandsbauelement und Verfahren zu seiner Herstellung
US6680668B2 (en) * 2001-01-19 2004-01-20 Vishay Intertechnology, Inc. Fast heat rise resistor using resistive foil
US6717254B2 (en) 2001-02-22 2004-04-06 Tru-Si Technologies, Inc. Devices having substrates with opening passing through the substrates and conductors in the openings, and methods of manufacture
US6753199B2 (en) * 2001-06-29 2004-06-22 Xanoptix, Inc. Topside active optical device apparatus and method
US6787916B2 (en) 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
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US7612443B1 (en) 2003-09-04 2009-11-03 University Of Notre Dame Du Lac Inter-chip communication
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DE102005004160B4 (de) * 2005-01-28 2010-12-16 Infineon Technologies Ag CSP-Halbleiterbaustein, Halbleiterschaltungsanordnung und Verfahren zum Herstellen des CSP-Halbleiterbausteins
US20090032871A1 (en) * 2007-08-01 2009-02-05 Louis Vervoort Integrated circuit with interconnected frontside contact and backside contact
DE102010055935B4 (de) 2010-12-23 2014-05-15 Epcos Ag Verfahren zum Verbinden mehrerer ungehäuster Substrate
DE102011109007A1 (de) 2011-07-29 2013-01-31 Epcos Ag Verfahren zum Herstellen eines elektrischen Bauelements und elektrisches Bauelement
US9620473B1 (en) 2013-01-18 2017-04-11 University Of Notre Dame Du Lac Quilt packaging system with interdigitated interconnecting nodules for inter-chip alignment
JP6302644B2 (ja) * 2013-11-11 2018-03-28 株式会社ディスコ ウェーハの加工方法
EP3499552A1 (de) * 2017-12-14 2019-06-19 Nexperia B.V. Halbleiterbauelement und verfahren zur herstellung
US10770432B2 (en) * 2018-03-13 2020-09-08 Stmicroelectronics S.R.L. ASICS face to face self assembly
CN109659104B (zh) * 2018-12-28 2021-06-08 广东爱晟电子科技有限公司 一种高可靠双面异质复合电极热敏芯片

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Also Published As

Publication number Publication date
WO1995034083A1 (en) 1995-12-14
GB2302452A (en) 1997-01-15
GB9623265D0 (en) 1997-01-08
JPH10508430A (ja) 1998-08-18
GB2302452B (en) 1998-11-18
US6121119A (en) 2000-09-19
HK1011454A1 (en) 1999-07-09
KR100358446B1 (ko) 2003-01-29
AU2659995A (en) 1996-01-04

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Legal Events

Date Code Title Description
8139 Disposal/non-payment of the annual fee