DE19681574T1 - System und Verfahren zum Erhöhen der Funktionalität am PCI-Bus - Google Patents

System und Verfahren zum Erhöhen der Funktionalität am PCI-Bus

Info

Publication number
DE19681574T1
DE19681574T1 DE19681574T DE19681574T DE19681574T1 DE 19681574 T1 DE19681574 T1 DE 19681574T1 DE 19681574 T DE19681574 T DE 19681574T DE 19681574 T DE19681574 T DE 19681574T DE 19681574 T1 DE19681574 T1 DE 19681574T1
Authority
DE
Germany
Prior art keywords
pci bus
increasing functionality
functionality
increasing
pci
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19681574T
Other languages
English (en)
Inventor
Ravi Nagaraj
Aniruddha Kundu
James Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE19681574T1 publication Critical patent/DE19681574T1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
DE19681574T 1995-09-26 1996-09-18 System und Verfahren zum Erhöhen der Funktionalität am PCI-Bus Withdrawn DE19681574T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/534,187 US5805842A (en) 1995-09-26 1995-09-26 Apparatus, system and method for supporting DMA transfers on a multiplexed bus
PCT/US1996/014939 WO1997014100A1 (en) 1995-09-26 1996-09-18 A system and method for increasing functionality on the peripheral component interconnect bus

Publications (1)

Publication Number Publication Date
DE19681574T1 true DE19681574T1 (de) 1998-10-01

Family

ID=24129034

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19681574T Withdrawn DE19681574T1 (de) 1995-09-26 1996-09-18 System und Verfahren zum Erhöhen der Funktionalität am PCI-Bus

Country Status (8)

Country Link
US (1) US5805842A (de)
KR (1) KR100271336B1 (de)
AU (1) AU7112596A (de)
BR (1) BR9610950A (de)
DE (1) DE19681574T1 (de)
GB (1) GB2319642B (de)
HK (1) HK1011228A1 (de)
WO (1) WO1997014100A1 (de)

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Also Published As

Publication number Publication date
GB9803706D0 (en) 1998-04-15
GB2319642B (en) 2000-09-13
KR19990063741A (ko) 1999-07-26
AU7112596A (en) 1997-04-30
KR100271336B1 (ko) 2000-11-01
BR9610950A (pt) 1999-01-12
GB2319642A (en) 1998-05-27
WO1997014100A1 (en) 1997-04-17
US5805842A (en) 1998-09-08
HK1011228A1 (en) 1999-07-09

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8125 Change of the main classification

Ipc: G06F 13/28

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8139 Disposal/non-payment of the annual fee