DE19726088C1 - Performance increase method for multi-processor system - Google Patents

Abstract

The method involves distinguishing between accessible and blocked processes which are arranged in separate queues of a multi-processor system with common main memory and processor-specific cache memories. Each processor is associated with its own queue for accessible processes, while a central queue is provided for the blocked processes. The blocked processes are distinguished between long-term and short-term blocked processes, and the short-term blocked processes are arranged in separate processor-specific queues.

Description

The invention relates to process management processes Multiprocessor systems according to the preamble of the An saying 1 and a correspondingly designed multiprocessor sysstem according to claim 3.

It is common knowledge that when expanding a Multiprocessor system not with the achievable useful performance every additional processor increases linearly. That was different causes, which are both software and hardware-related could be. Software-related causes exist e.g. B. in the lack of parallelism of the program sequences and in the possible waiting times for competing access instances of shared resources because of the accesses must be serialized by assigning locks. On the Hardware side arise despite the use of private Cache expiration delays when needed data in Cache memories are not present, this effect still is amplified when the assignment between one is made leading process and the executing processor different.

One of the tasks of the operating system of a multiprocess sorsystems is there for optimal use of the Sy to worry about. This particularly affects the administration the computational and the blocked processes and the groove natural process processor affinity by adding a Processor always the same process for as long as possible is arranged.

The tried and tested method for monoprocessor systems blocked and ready processes in central queues  manage leads to multiprocessor systems with the number of the processors linearly increasing losses caused by the Waiting times for the serialization of the accesses locking blocks are conditional.

To reduce these losses, therefore, has already been proposed beat, one for each processor by its own Lock protected queue for computational processes instead of the central queue while the blocked processes remain in the central queue be performed. But this has the disadvantage that for every pro the very frequent state transition "blocked" "ready to compute" continues with the need to request global lock is connected.

Furthermore, it is known the potential of the natural pro zeß processor affinity to use in that when used a central queue for the computational processes a free processor from the queue only such pro processes that have been allocated in the recent past were assigned to this processor. Such an approach is required but a relatively time-consuming search of the control room queue, which in turn extends the duration of the lock usage and thus increases losses.

Other known solutions have a central control room queue for computer-ready processes for each processor an individual queue for computer-ready processes high affinity for the respective processor - one see US 5,261,053. It is also known to have two for each processor to provide separate local queues, one of which the computer-ready processes while blocking Processes are placed in the second queue den - see US 5,506,987.

The object of the invention is the useful performance of a multi processor system through appropriate measures against the be  known systems to increase and especially the loss increased significantly with increasing number of processors reduce.

This is achieved in the method according to claim 1 by that in the blocked processes between one only briefly long-term blocking and the longer-lasting blockage a distinction is made and those temporarily blocked Processes also in processor-specific queues  be performed. This means that a process automatically stays that long bound to a processor until it blocks in the long term and with a high probability the affinity for previous processor loses. An affinity test is a process to a processor becoming free dispensable. A global lock only needs to be included End of a long-term blocking of a process to be requested, and since long-term blockages the resulting losses are rare largely negligible.

To because of the processor-specific queues for the Computational processes of unjustified idle states To avoid one of the processors, according to claim 2 usual allocation procedure from the processor-individual Queue broken when idle one predetermined period of time persists. In this case catches up the idling processor starts a process ready for computing the queue of the most busy pro at the moment cessors.

One for the mode of operation according to claims 1 and 2 designed and with the corresponding advantages Multi processor system results from the characteristics of Claim 3.

Details of the invention are described below with reference to an in the drawing shown embodiment closer described. Show in detail

Fig. 1 shows a multiprocessor system with four processors and a schematic representation of the queue structure,

Fig. 2 is a Flußdiagrammm for explaining the assignment of the output from a processor to process the queues and Fig. 3 is a flowchart for explaining the allocation of an idle processor with a process.

Fig. 1 shows the queue structure for a multiprocessor system with four processors CPU. According to the invention, each of these processors is assigned two individual queues LWS-R and LWS-W, namely an LWS-R for computational processes and an LWS-W for processes blocked for a short time. Long-term blocked processes, on the other hand, are managed in a global central queue GWS-W. All queues are protected by locks in a known manner, but only one lock is required for the processor-specific queue pairs LWS-R / LWS-W.

The assignment of the individual processes to the individual control queues is explained using the flow chart of FIG. 2. The starting point is the delivery by a processor CPU. Is it a computational process because z. B. a time slice has expired or the process has been displaced by a higher priority, then this is hooked into the processor-specific local queue LWS-R for computational processes. If, on the other hand, the process is blocked, the reason for the block determines which queue takes over the process. Is the blocking short-term because the end of the blocking is foreseeable soon, e.g. B. the end of a disk input / output, then the mounting in the local queue LWS-W for blocked processes. However, if the end of the blockage is not foreseeable, such as. For example, when waiting for a message, it is a long-term block and the process must be put on the global queue GWS-W for blocked processes.

If the blocking of a process ends, then it becomes a process from the local queue LWS-W for blocked processes  always in the queue LWS-R for computing ready processes of the same processor CPU mounted. The Process-processor affinity is therefore preserved. Processes the global queue GWS-W, however, are each in the LWS-R on hold for computational processes of the least CPU loaded.

As a rule, when a processor becomes free, it becomes CPU a process from the own queue LWS-R for computing prepared processes assigned, which according to a given Strategy is done, e.g. B. priority or after "First-in-first-out" principle.

However, in order to avoid unjustified idle states of a processor, the flowchart in FIG. 3 is used. As soon as a processor determines that its queue LWS-R is empty for computational processes, monitoring is started for the period T _W. If no new process is made available by the own queue LWS-R for computational processes within this monitoring period, it is checked whether the corresponding queues LWS-R of the other processors are also empty. If this is the case, external access takes place, ie the processor fetches a process that is ready for computing from the queue of the processor with the highest load.

The utilization of a processor CPU can be an example of this measured how often he waits per unit of time queue LWS-R has accessed another processor. Each the smaller the number of these external accesses, the higher the processor is busy.

Claims (3)

1. Process for the management of processes in multiprocessor systems with shared main memory and process-specific cache memory, a distinction being made between compute-ready and blocked processes, which are placed in separate queues, and each processor (CPU) has its own queue (LWS-R) is assigned for processes ready for computing, while a central queue (GWS-W) is provided for the blocked processes, characterized in that a distinction is made between long-term and short-term blocked processes in the blocked processes and that the short-term blocked processes are separated into separate process-specific queues (LWS-W) for short-term blocked processes. 2. The method according to claim 1, characterized in that each processor (CPU) checks when it is freed whether its own queue (LWS-R) is empty for computational processes, that a processor (CPU), its own queue (LWS-R ) for computational processes is empty until a computational process from its own queue (LWS-R) is available for computational processes or a specified period of time (T _W ) has elapsed, and that if a computational process has not occurred within this period (T _W ) a computer-ready process from the queue (LWS-R) for computer-ready processes of the most heavily loaded processor (CPU) in the system. 3. Multiprocessor system with shared memory and processor-specific cache, in which between right processes that are ready and blocked are distinguished, which are placed in separate queues, and at each processor (CPU) has its own queue (LWS-R)  is allocated for computational processes, while for the processes blocked a central queue (GWS-W) is seen characterized, that in addition to the processor-specific queues (LWS-R) one processor each for processes ready for computing individual queue (LWS-W) for short-term blocked Processes of the associated processor (CPU) is provided, while the central queue (GWS-W) for longer term blocked processes is provided.