DE19935700A1 - Circuit arrangement for personal computer with several graphics processor for reduction of electromagnetic field interference between screens - Google Patents

Abstract

The circuit arrangement is such that each graphic processor has a clock, and a genlock input or output. The clock inputs of all the graphic processors are connected to a common oscillator, or have individual oscillators with one of the graphic processors arranged as a master. The master uses its genlock signal as a controller genlock input to the remaining slave processors. An Independent claim is made for a personal computer (PC) with several graphic processors for simultaneous control of more than one monitor, where the master graphics card has a clock input from a reference oscillator, with the remaining slave graphics cards clocked via a voltage controlled oscillator in a phase lock loop (PLL) circuit.

Description

The invention relates to a circuit arrangement for a Personal computer with multiple graphics processors, each especially with a screen using digital-to-analog converter Control the electron beam tube.

A personal computer usually has a graphics card or circuit for processing and displaying all data, which are important for the screen output. Graphic card ten or circuits consist essentially of a Gra fikprocessor, its own RAM and a Digi tal-analog converter.

Screens mainly work with electron beam tubes (CRT - Abbreviation for Cathode Ray Tube), where a Electron beam through magnetic or electric fields like this is deflected that the beam line by line the presen area of the screen.

For example at CAD workstations or in control centers from The amount of information cannot be partially generated by power plants display satisfactorily with a screen. For this type Applications are therefore required for computers with several Screens can be controlled.

There are various approaches to this:

• a) The graphics circuit of the graphics card passes the data of the working memory by means of suitable readout methods to at least two digital-to-analog converters (DAC-Digital / Analog Converter), the data stream directed to the various DACs being preferably programmable, for example by separated programmable image readers (frame buffer readers); see. Image 1).
  However, there are also solutions with only one image reading memory (frame buffer reader), the content of which is distributed to at least two DACs by dividing the data stream output and then routing it to adjacent screens ( Figure 2). This multi-screen controls with only one graphics processor are not the subject of the invention.
• b) The personal computer has several graphics cards, which programmatically supply several screens with parts of the screen output ( Figure 3).
• c) The personal computer is equipped with a special graphics card on which there are several graphics processors, each with separate working memories. An interface is regularly provided between the bus of the personal computer and the graphics processors so that the data from the bus are correctly distributed to the various graphics processors. As an interface z. For example, a 'bridge' can be used ( Figure 4). As with the solution b) with several graphics cards, the driver of the graphics card controls the graphics processors separately, which supply the screens with a largely freely programmable screen output.

If screens with electron beam tubes are arranged side by side and / or one above the other in multi-screen operation on a personal computer, their deflection units, these are plate systems with electrical or magnetic fields for aligning the electron beam, can influence each other (as illustrated in Figure 5 using the example of magnetic fields) .

If all screens with the same refresh rate and the same line frequency are operated, tre due to the mutual influence of the image shield static distortions (dents / pillows / tons / Color error). The distortions can be seen on modern picture shield using the setting options for correction largely eliminate the image geometry. If so despite the same refresh rate and the same line change selfrequency the analog image signals are out of phase, these distortions cannot be corrected permanently, since the phase position changes the next time the personal computer is started ters changes.

If the screens have independent lines or images such as refresh frequencies are operated, the distortion not using the setting options for correction compensate for the image geometry. With big differences between Show the line and / or refresh rates annoying flicker effects, while at lower sub distinguished barrel distortions and / or pillow errors with ge ringer frequency through the screen output. Moreover it can occur with different line or picture repetitions sequences occur that the deflection units, audible noises develop that are perceived as unpleasant.

In television studio technology, it has long been necessary that the various recording and playback devices work fre quenz- and phase-synchronized, so that no annoying artifacts occur when electronic cutting, fading and switching between the various devices. A so-called genlock signal ( Fig. 6) exists in studio technology for synchronization, which is led to all devices via signal lines. A generator for a master signal provides the genlock signal, to which all other devices adjust their internal oscillators.

Many of them own for use in television studio technology known GPUs today have a genlock input. This remains when using the graphics processors in graphics cards for personal computers are regularly blank, there is a synchronization between personal computers and devices studio technology because of the usually perfect whose line and refresh rates are not useful and would be technically impossible.

EP 0 734 011 A2 describes a system of personal computers known, in particular a system of digital-to-analog converters (RAMDAC) to store data from an image read memory (frame Buffer) on a screen. If with this System related or related to each other the following pictures of at least two personal computers to your Screens are transmitted, errors occur because of the different personal computers do not work synchronously. To solve this problem, according to EP 0 734 011 A2 Image read-only memory (frame buffer) configured as the master provides a field signal that occurs with each vertical sync event changes its state in the master image read memory. The picture memory (frame buffer) of the other personal computers configured as a slave and their synchronization units sample the field signal of the master image memory.

The invention is based on the object, a circuit to create order of the type mentioned at the beginning with the Multi-screen operation is possible on a personal computer, where distortions can be permanently corrected as well annoying flickering and audible noise from the Deflection units can be avoided.

This object is achieved by circuit arrangement gene with the combinations of features according to claims 1 and 4 solved.  

The solution according to claim 1 is based on the idea that the right Occasional genlock capability of the graphics processors of graphics cards for personal computers to use several graphics processors frequency synchronous and with defin ter phase position to operate.

By using the un for graphics cards for personal computers Genlock ability used can be surprisingly simple Way with little circuitry measures annoying flickering and / or image distortion screen output on neighboring screens can be avoided.

In a preferred embodiment of a graphics card for multi- screen operation ( Figure 7) there are two or more graphics processors on a circuit board. All graphics cards regularly have their own analog outputs and each operate a screen with an electron beam tube. Since it is not out of the question that screens with electron beam tubes with digital signals of flat panel technology will be controlled by the graphics card in the future, a D / D converter (protocol converter) can be seen instead of the A / D converter his.

All clock inputs of the graphics processors are with one common oscillator connected. With the same programming the internal register of the graphics processors is guaranteed provides the analog output signals of each graphic processor-assigned analog / digital converter frequency syn work chronically. There are several graphics cards in the perso nalcomputer it is appropriate for each graphics processor because to provide an oscillator. This separate oszilla gates can be frequency-synchronized with a PLL circuit operate.

One of the graphics processors is circuit-wise Master executed. This graphics processor generates for the  other GPUs a genlock signal that their Genlock inputs is supplied. The rest of the graphics processo ren are programmed so that the genlock signal lines puts the meter in a defined state. This one more Measure ensures that the various graphics processing ren both frequency-synchronized and with defined phases location work.

In one embodiment of the invention according to claim 2 between the genlock output rule of the graphics processor connected as master and each genlock input of the other graphics processors at least one adjustable time delay element is switched ( Figure 8). This makes it possible to specifically shift the phase position of the screen output of the screens operated in parallel. This measure can also handle difficult cases of mutual interference between the screens.

If two adjustable time delay elements ( Figure 9) are connected upstream of each genlock input of the other graphics processors, the first time delay element can change the phase position in steps in such a way that the time delay is a multiple of a line time, while the second, downstream delay element has an adjustable delay one Can make a fraction of a line time. As a result, the phase positions can be set so precisely that an additional correction using the setting options on the screen is completely unnecessary.

In technical terms, the delay times (ms range) required to change the phase position are relatively high. At the same time, it is necessary to set the delay time exactly (ns range). The two delay elements therefore combine the relatively high delay in the first with a fine delay in the second delay element. The first delay element responds to HS (Horizontal Syn chron), while the second delay element responds to the oscillator clock (pixel clock). This means that the screen output can be positioned vertically with the first delay element and horizontally with the second delay element ( Figure 9).

The solution according to claim 4 is that the graphics processors used have their own oscillators ( Figure 10). In this case, the oscillator of the first graphics processor is switched as a reference oscillator, while the other graphics processors are designed as tracking oscillators (VCO = Voltage Controlled Oscillator) in a PLL (phase lock loop) circuit. The task of the PLL (Phase Lock Loop) circuit is to adjust the frequency of the tracking oscillators so that they exactly match the frequency of the reference oscillator, and so precisely that the phase shift does not run away. In this solution too, the first graphics processor works in terms of circuitry as a master with a defined and fixed frequency, while the tracking oscillators of the other graphics processors work in slave mode. The reference frequencies are the HS / VS frequencies of the master, the tracking frequencies are the HS / VS frequencies of the slave. This alternative solution is particularly important if the graphics processors used do not have a genlock input.

The arrangement is also in this embodiment of the invention of one or two time delay elements in each PLL circuits useful to get a more accurate input position of the phase positions. The delay line which are preferably in front of the VS inputs of the phase detectors switched. It is in this embodiment of the invention expedient, a first delay element with high delays switch in front of the VS input, which is n times the HS clock rate is delayed and behind it a second, very precise one  Delay element for short time delays, which with the Oscillator clock (pixel clock) works.

The invention is not based on the exemplary embodiments limits, where all graphics processors on one common board are arranged. It is also possible that Distribute circuits across multiple graphics cards that over a pipeline system are interconnected. The coupling The boards are both described using the genlock technique as well as with the help of the PLL circuits and combinations of the two techniques possible.  

Overview of the English terms in Figures 1-11

Claims (8)

1. Circuit arrangement for a personal computer with several ren graphics processors, each controlling a screen with electron beam tube, in particular via digital-analog converter, characterized in that each graphics processor has a clock - and a genlock input or output, the clock inputs of all Graphics processors are connected to a common or an oscillator, one of the graphics processors is designed as a master, the master for the other graphics processors designed as slaves providing a genlock signal at its gen lock output, which the other graphics processors use via their genlock -Inputs to be led. 2. Circuit arrangement according to claim 1, characterized net that between the genlock output of the as master designed graphics processor and each genlock input the other graphics processors designed as slaves at least one, in particular adjustable time delay is switched. 3. Circuit arrangement according to claim 2, characterized net that between the genlock output of the as master designed graphics processor and each genlock input the other graphics processors designed as slaves two particularly adjustable time delay elements are switched, the first adjustable time delay the phase position by a multiple of a time delay time, while the second adjustable delay the phase position by a fraction of a time delayed.   4. Circuit arrangement for a personal computer with several graphics processors, each via digital-analog Converter to a screen with an electron beam tube control, characterized in that each graphics process Sor has a clock input with an oscillator is connected, with a graphic working as a master processor is clocked by a reference oscillator, wäh rend the other graphics processors working as slaves each of tracking oscillators in a PLL (phase lock Loop) circuit can be clocked. 5. Circuit arrangement according to claim 4, characterized net that each PLL circuit with a phase detector at least one input for the reference frequency (s) and an input for the tracking frequency (s) and one Output for the control voltage of the tracking oscillator has, the output with the input of the span voltage-controlled tracking oscillator is connected. 6. Circuit arrangement according to claim 4 or 5, characterized ge indicates that at least in each PLL circuit a time delay element is arranged. 7. Circuit arrangement according to one of claims 1 to 6, there characterized in that at least two graphics processors ren are arranged on a common board. 8. Circuit arrangement according to one of claims 1 to 6, there characterized in that the graphics processors on ge separate boards are arranged.