DE19983859T1 - Cachesystem mit Doppelschnittstelle und zwei Stufen mit Pipeline - Google Patents

Cachesystem mit Doppelschnittstelle und zwei Stufen mit Pipeline

Info

Publication number: DE19983859T1
Authority: DE; Germany
Prior art keywords: pipeline; levels; cache system; double interface; double
Prior art date: 1998-12-31
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Withdrawn

Application number

DE19983859T

Other languages

English (en)

Inventor

John Wai Cheong Fu

Dean A Mulla

Gregory S Mathews

Stuart E Sailer

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

Intel Corp

Original Assignee

Intel Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1998-12-31

Filing date

1999-12-29

Publication date

2002-02-28

1999-12-29 Application filed by Intel Corp filed Critical Intel Corp

2002-02-28 Publication of DE19983859T1 publication Critical patent/DE19983859T1/de

Status Withdrawn legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
- G06F12/0897—Caches characterised by their organisation or structure with two or more cache hierarchy levels

DE19983859T 1998-12-31 1999-12-29 Cachesystem mit Doppelschnittstelle und zwei Stufen mit Pipeline Withdrawn DE19983859T1 (de)

Applications Claiming Priority (2)

Application Number	Priority Date	Filing Date	Title
US09/223,847 US6272597B1 (en)	1998-12-31	1998-12-31	Dual-ported, pipelined, two level cache system
PCT/US1999/031179 WO2000039764A1 (en)	1998-12-31	1999-12-29	A dual-ported pipelined two level cache system

Publications (1)

Publication Number	Publication Date
DE19983859T1 true DE19983859T1 (de)	2002-02-28

Family

ID=22838194

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE19983859T Withdrawn DE19983859T1 (de)	1998-12-31	1999-12-29	Cachesystem mit Doppelschnittstelle und zwei Stufen mit Pipeline

Country Status (7)

Country	Link
US (1)	US6272597B1 (de)
CN (1)	CN1154049C (de)
AU (1)	AU2220500A (de)
DE (1)	DE19983859T1 (de)
GB (1)	GB2359910B (de)
TW (1)	TW454161B (de)
WO (1)	WO2000039764A1 (de)

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DE10002120B4 (de) *	1999-02-13	2006-04-20	International Business Machines Corp.	Adressumsetzpufferanordnung und Verfahren für den Betrieb einer Adressumsetzpufferanordnung
US6470437B1 (en) *	1999-12-17	2002-10-22	Hewlett-Packard Company	Updating and invalidating store data and removing stale cache lines in a prevalidated tag cache design
US6625714B1 (en) *	1999-12-17	2003-09-23	Hewlett-Packard Development Company, L.P.	Parallel distributed function translation lookaside buffer
US6427188B1 (en) *	2000-02-09	2002-07-30	Hewlett-Packard Company	Method and system for early tag accesses for lower-level caches in parallel with first-level cache
US6647464B2 (en)	2000-02-18	2003-11-11	Hewlett-Packard Development Company, L.P.	System and method utilizing speculative cache access for improved performance
US6427189B1 (en) *	2000-02-21	2002-07-30	Hewlett-Packard Company	Multiple issue algorithm with over subscription avoidance feature to get high bandwidth through cache pipeline
US6729652B2 (en)	2001-12-26	2004-05-04	Cloud-Rider Designs	Vehicle mud flap
US6862028B2 (en) *	2002-02-14	2005-03-01	Intel Corporation	Bin pointer and state caching apparatus and method
US20030163643A1 (en) *	2002-02-22	2003-08-28	Riedlinger Reid James	Bank conflict determination
US7143239B2 (en) *	2003-08-07	2006-11-28	Hewlett-Packard Development Company, L.P.	Cache structure and methodology
US7334108B1 (en)	2004-01-30	2008-02-19	Nvidia Corporation	Multi-client virtual address translation system with translation units of variable-range size
US7278008B1 (en) *	2004-01-30	2007-10-02	Nvidia Corporation	Virtual address translation system with caching of variable-range translation clusters
US7296139B1 (en)	2004-01-30	2007-11-13	Nvidia Corporation	In-memory table structure for virtual address translation system with translation units of variable range size
US7769950B2 (en) *	2004-03-24	2010-08-03	Qualcomm Incorporated	Cached memory system and cache controller for embedded digital signal processor
US7123496B2 (en) *	2004-05-10	2006-10-17	Intel Corporation	L0 cache alignment circuit
US8886895B2 (en) *	2004-09-14	2014-11-11	Freescale Semiconductor, Inc.	System and method for fetching information in response to hazard indication information
US7434009B2 (en) *	2004-09-30	2008-10-07	Freescale Semiconductor, Inc.	Apparatus and method for providing information to a cache module using fetch bursts
US20080022265A1 (en) *	2006-06-30	2008-01-24	Morris Robert P	Methods, systems, and computer program products for generating and using object modules
US20080005727A1 (en) *	2006-06-30	2008-01-03	Robert Paul Morris	Methods, systems, and computer program products for enabling cross language access to an addressable entity
US20080005719A1 (en) *	2006-06-30	2008-01-03	Morris Robert P	Methods, systems, and computer program products for providing a program execution environment
US20080005528A1 (en) *	2006-06-30	2008-01-03	Morris Robert P	Methods, Systems, and Computer Program Products for Using a Structured Data Storage System to Provide Access to Addressable Entities in Virtual Address Space
US20080005752A1 (en) *	2006-06-30	2008-01-03	Robert Paul Morris	Methods, systems, and computer program products for generating application processes by linking applications
US20080127220A1 (en) *	2006-06-30	2008-05-29	Robert Paul Morris	Methods, systems, and computer program products for creating an input-value-specific loadable instance of an application
US20080005728A1 (en) *	2006-06-30	2008-01-03	Robert Paul Morris	Methods, systems, and computer program products for enabling cross language access to an addressable entity in an execution environment
US20080005529A1 (en) *	2006-06-30	2008-01-03	Morris Robert P	Methods, Systems, and Computer Program Products for Providing Access to Addressable Entities Using a Non-Sequential Virtual Address Space
US7734890B2 (en) *	2006-10-06	2010-06-08	Okralabs Llc	Method and system for using a distributable virtual address space
WO2008047180A1 (en) *	2006-10-20	2008-04-24	Freescale Semiconductor, Inc.	System and method for fetching an information unit
US20080120604A1 (en) *	2006-11-20	2008-05-22	Morris Robert P	Methods, Systems, And Computer Program Products For Providing Program Runtime Data Validation
CN100428209C (zh) *	2006-12-22	2008-10-22	清华大学	一种自适应的外部存储设备io性能优化方法
US20080320459A1 (en) *	2007-06-22	2008-12-25	Morris Robert P	Method And Systems For Providing Concurrency Control For Addressable Entities
US20080320282A1 (en) *	2007-06-22	2008-12-25	Morris Robert P	Method And Systems For Providing Transaction Support For Executable Program Components
US20090249021A1 (en) *	2008-03-26	2009-10-01	Morris Robert P	Method And Systems For Invoking An Advice Operation Associated With A Joinpoint
US8166229B2 (en) *	2008-06-30	2012-04-24	Intel Corporation	Apparatus and method for multi-level cache utilization
CN101770437B (zh) *	2008-12-30	2013-05-29	中国科学院电子学研究所	实现同步双端口存储器ip的并行读写的装置及方法
US8904115B2 (en) *	2010-09-28	2014-12-02	Texas Instruments Incorporated	Cache with multiple access pipelines
CN102591817B (zh) *	2011-12-30	2014-12-31	中山大学	一种多总线桥控制器及其实现方法
US10198358B2 (en) *	2014-04-02	2019-02-05	Advanced Micro Devices, Inc.	System and method of testing processor units using cache resident testing
CN107038125B (zh) *	2017-04-25	2020-11-24	上海兆芯集成电路有限公司	具有加速预取请求的独立流水线的处理器高速缓存

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Publication number	Priority date	Publication date	Assignee	Title
US5023776A (en) *	1988-02-22	1991-06-11	International Business Machines Corp.	Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage
JP2703418B2 (ja) *	1991-04-24	1998-01-26	株式会社東芝	中央演算処理装置
US5442766A (en) *	1992-10-09	1995-08-15	International Business Machines Corporation	Method and system for distributed instruction address translation in a multiscalar data processing system
US5510934A (en) *	1993-12-15	1996-04-23	Silicon Graphics, Inc.	Memory system including local and global caches for storing floating point and integer data
EP0840231A1 (de) *	1996-10-31	1998-05-06	Texas Instruments Incorporated	Mikroprozessor mit mehrstufigem Cachespeicher
US6119222A (en) *	1996-12-23	2000-09-12	Texas Instruments Incorporated	Combined branch prediction and cache prefetch in a microprocessor
US6101579A (en) *	1997-03-07	2000-08-08	Mitsubishi Semiconductor America, Inc.	Multi-port memory device having masking registers
US6044478A (en) *	1997-05-30	2000-03-28	National Semiconductor Corporation	Cache with finely granular locked-down regions
US6065091A (en) *	1997-05-30	2000-05-16	Via-Cyrix, Inc.	Translation look-aside buffer slice circuit and method of operation
US5930819A (en) *	1997-06-25	1999-07-27	Sun Microsystems, Inc.	Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache

1998
- 1998-12-31 US US09/223,847 patent/US6272597B1/en not_active Expired - Lifetime
1999
- 1999-12-15 TW TW088121954A patent/TW454161B/zh not_active IP Right Cessation
- 1999-12-29 GB GB0112694A patent/GB2359910B/en not_active Expired - Fee Related
- 1999-12-29 DE DE19983859T patent/DE19983859T1/de not_active Withdrawn
- 1999-12-29 AU AU22205/00A patent/AU2220500A/en not_active Abandoned
- 1999-12-29 CN CNB998153621A patent/CN1154049C/zh not_active Expired - Fee Related
- 1999-12-29 WO PCT/US1999/031179 patent/WO2000039764A1/en active Application Filing

Also Published As

Publication number	Publication date
GB0112694D0 (en)	2001-07-18
AU2220500A (en)	2000-07-31
CN1333906A (zh)	2002-01-30
GB2359910A (en)	2001-09-05
WO2000039764A9 (en)	2000-12-07
US6272597B1 (en)	2001-08-07
WO2000039764A1 (en)	2000-07-06
TW454161B (en)	2001-09-11
CN1154049C (zh)	2004-06-16
GB2359910B (en)	2003-12-17

Legal Events

Date	Code	Title	Description
2002-02-28	OP8	Request for examination as to paragraph 44 patent law
2002-05-02	8125	Change of the main classification	Ipc: G06F 12/08
2012-03-29	R119	Application deemed withdrawn, or ip right lapsed, due to non-payment of renewal fee	Effective date: 20110701

Publication	Publication Date	Title
DE19983859T1 (de)	2002-02-28	Cachesystem mit Doppelschnittstelle und zwei Stufen mit Pipeline
DE69929246D1 (de)	2006-02-02	Katheterschaft mit mehreren leitungen und verstärkung
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DE69914119D1 (de)	2004-02-19	Verbesserungen an, oder bezüglich, Rohrkupplungen
DE59903690D1 (de)	2003-01-16	Drehriegelverschluss mit zugeinrichtung
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DE69840960D1 (de)	2009-08-20	Cachespeicherersetzungsverfahren mit verriegelung
DE69714079T2 (de)	2003-02-27	Weiche, textilartige webstoffe mit elastikähnlichen eigenschaften
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DE69925063D1 (de)	2005-06-09	Tastatur mit Rückbeleuchtungsanzeige
DE69812223D1 (de)	2003-04-24	Blockierungsfreier Pipeline-Cachespeicher
DE69910860D1 (de)	2003-10-09	Cache-Speicherkohärenzprotokoll mit Schwebe- (H) und vorigen (R) Zuständen
ID28238A (id)	2001-05-10	Peranti pemroses benang dan penggunaannya
NL1013523A1 (nl)	2000-05-10	Wisselklep met afsluit- en expansiefuncties.
DE69715491D1 (de)	2002-10-24	Cache-Struktur mit mehreren Modi
DE69502901D1 (de)	1998-07-16	Verbesserungen an, oder bezüglich, Rohrkupplungen mit Haltegliedern
DE69801656D1 (de)	2001-10-18	Flugzeugradteil mit korrosions- und verschleissbeständigkeit
DE59913043D1 (de)	2006-04-06	Mikroskop mit auflichteinkopplung
DE69822343D1 (de)	2004-04-15	Okklusionsanordnung mit volkommener reproduzierbarkeit