DE2756915A1 - SEMI-CONDUCTOR ARRANGEMENT, IN PARTICULAR FOR A NON-DESTRUCTIVE READABLE MEMORY CELL - Google Patents

Description

275691b

Applicant: International Business Machines

Corporation, Armonk, N.Y. 10504 moe / sue

Semiconductor arrangement, in particular for a non-destructively readable memory cell

The invention relates to a semiconductor device according to the preamble of claim 1. Your preferred one Field of application are memory arrangements with random access and in particular non-destructive readable memory cells, depending on the respective memory information in one of two possible states, namely a stable and a quasi-stable state can be brought about.

US Pat. No. 3,439,236 is cited for the prior art relating to a similar structure of a semiconductor device. It deals with an oscillator component that is based on the so-called volume effect and its structure with an insulating-layer field effect transistor is comparable. The associated semiconductor device sees a couple of N diffusion regions with an N-conductive region connecting them in a P-conductive substrate. over the diffused channel area there is an insulated gate. This semiconductor device can be calibrated in two different operating modes operate that of the operation of an insulated gate field effect transistor of the enhancement type and the depletion type correspond. In the depletion mode, a DC voltage potential is applied between source and drain, via which a electric field is formed which is above the value characteristic of the respective semiconductor material Threshold voltage is so that current oscillations are generated between the source and drain. Via one to the gate electrode connected signal source is then applied a negative bias voltage, via which the negative charge carriers

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from the N-conductive diffusion area, that of the channel area an insulated gate field effect transistor, are repelled. The number of existing in the channel area Charge carriers (electrons) are thus reduced in the sense of a ver j among. Will the concentration of majority carriers in the N-conductive diffusion region is reduced below a critical value, so that the product of the number

of electrons / an ³ multiplied by the length of the N-conductive

11 2 'gen diffusion range (in cm) becomes smaller than approximately 10 / cm, the vibrations stop. In enrichment mode j is a DC voltage source between source and; Drain generates an electric field which is below the critical value characteristic of the respective semiconductor material. As a result, no current oscillations occur. : The signal source connected to the source and drain then applies a positive bias voltage to the gate electrode, whereupon additional negative charge carriers are attracted into the N-conductive diffusion region. It is in this way lifted 'the concentration of charge carriers (electrons) in the N-type diffusion region over a critical value, so that the product of the number of electrons / cm multiplied nut of the length of the conductive N-

11 2 diffusion area (in cm) is greater than approximately 10 / cm, current oscillations occur again between source and drain. Despite a comparable structure, the mentioned Reference to the state of the art completely different operating states utilized, in particular this semiconductor arrangement is not suitable for use as a memory cell which the arrangement can assume two different states under the same pretensioning conditions an indication that the surface of the channel region I must be isolated from the substrate.

Furthermore, on the state of the art, refer to the article "Deep Channel MOS Transistor ", by J. Berger in the journal IEEE Transactions on Electron Devices ^ Vol. ED-22, No. 6, YO 976 016

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June 1975, pages 314 to 319, pointed out. There will be a treated by means of ion implantation built-up MOS transistor, which can be read out as an integrating non-destructive The photo sensor is used in conventional MOS integration technology can build up. This semiconductor device uses both P and N conductive buried channel regions between source and drain. A gate electrode is in insulated form over the implanted channel regions intended. With zero voltage at the gate electrode, the channel region is of the same conductivity type as the source and Drain located beneath an ion-implanted area of opposite conductivity type, conductive, so that a current can flow between the source and drain. If a negative potential is applied to the gate electrode, become all minority charge carriers present in the depletion zone attracted towards the boundary layer, so that the channel becomes non-conductive due to depletion. The charge storage area (i.e. the implanted area of the same Conductivity type like the substrate) can now store a large amount of positive charge. Because this area is not is connected to the substrate, the charge storage area remains depleted until thermally (or by light) generated minority carriers are available in sufficient quantities. With increasing positive charging of the charge storage area the channel region is gradually shielded from the electric field influence impressed by the gate electrode and slowly become a leader. As will be explained in more detail later, the semiconductor arrangement to be specified it is not necessary to physically form a surface area of the same conductivity type as the substrate. This reference also contains how even in that previously discussed, no indication of such an arrangement with a single buried channel area can be operated in a stable state using an inversion layer.

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The object of the invention is to provide one for the construction of a To specify a memory cell suitable semiconductor arrangement which can assume a stable and a quasi-stable state, wherein in particular a non-destructive reading of the memory cell and the lowest possible power consumption should be guaranteed. Furthermore, the semiconductor arrangement to be specified should be simple in structure and with the conventional one integrated processes.

To solve this problem, the invention provides the measures characterized in claim 1. Advantageous configurations and developments of the invention are characterized in the subclaims. In summary, a memory element with a stable and a quasi-stable state is provided according to the invention with a single MOS field effect transistor structure. In the channel region, the field effect transistor structure has a doping region lying on the surface and connecting the source and drain doping regions, of the conductivity type opposite to that of the substrate. The first storage state is characterized in that a thin inversion layer "is formed on the surface of the Do-> tierungsgebietes in the channel region under which a conductive channel between the source and drain j remains. In order to impress the second storage state, an oppositely polarized voltage pulse is superimposed on the basic bias voltage at the gate electrode, which initially displaces the movable minority charge carriers present in the inversion layer and, when returning to the basic bias voltage ratio, also displaces the remaining movable majority charge carriers from the lower area of the doping area in the The channel region is displaced, so that a deep depletion zone, cleared of all free, movable charge carriers, remains between source and drain, ie a non-conductive channel is present. This state is quasi-stable and can result from the accumulation of minority charge carriers in relation to the doping region

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In the canal area, after some tent, back to the first state regress. On the other hand, this first storage state can be polarized identically to the basic bias voltage by superimposing it Pulse voltage can be specifically written to the gate electrode.

The invention is explained in more detail below on the basis of exemplary embodiments with the aid of the drawings.

Show it:

Figs. 1A, 1B, 1C are schematic cross-sectional representations

the semiconductor arrangement as well as an illustration of the two distinguishable states, namely in the case of a conductive channel (FIG. 1B) as well as in the case of a non-conductive channel (Fig. 1C) ι

Figs. 2A to 2D representations of the belt models for the

both channel states according to Figures 1B and 1C;

Figs. 3A, 3B band models for the conditions at

Switching from conductive to non-conductive

; tendency state (Fig. 3A) or from the non-lead

tend to the conductive state (Fig. 3B);

Figs. 4A, 4B a first example of the read / write

conditions when driving at the gate electrode ;

Figs. 5A, 5B another example of the write /

Reading conditions when driving the arrangement at the source electrode;

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Fig. 6 is a schematic illustration for explanation

amendment of the application of such a semiconductor device in a memory cell circuit and

Fig. 7 is a plan view of the integrated Aus

management of a memory cell circuit according to FIG. 6.

1A shows a schematic cross-sectional illustration through a MOS transistor 1 with a buried channel which, because of its memory properties, can be used as a dynamic memory cell that can be read out non-destructively. The transistor 1 can be of a type that uses a ring configuration for the source, drain and channel. Although this is not the only embodiment, such a transistor with an annular configuration of its zones is not subject to the influence of leakage currents from the substrate into the channel region, as would be the case with arrangements with an open channel. This will be discussed in more detail later. The surface of the channel region of the substrate for proper operation should enter semiconductor _device: In any case, should be isolated for. In FIG. 1A, the buried channel region of the N conductivity type is arranged between the Ν + -conductive source and drain regions 3 and 4, which in turn are formed in a P-conductive substrate 5. The I buried channel 2 connects source 3 and drain 4 and is separated from a gate electrode 6 by a thin insulating or oxide layer 7. The structure shown for the transistor 1 can be produced by means of conventional semiconductor production processes using conventional photolithography and etching as well as diffusion and ion implantation processes. To give an example, the substrate 5 may be made of a semiconductor material, e.g. B. silicon exist, the inigun g with an Acceptorverunre, z. B.

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Sodium or boron is doped, so that there is a specific resistance of 10 to 20 Ω.αη for the substrate. the associated concentrations of sodium or boron are about 7 10 to 1.4 χ 10 atoms / cm. Source 3 and Drain are in the usual way by means of diffusion of a donor substance, z. B. Phosphorus, at a concentration of 10 Atoms / cm. The buried channel 2 is preferably by means of ion implantation of phosphorus atoms with

11 2 a dosage of 5 χ 10 atoms / cm at 160 keV in an produced in a known manner before the formation of the gate electrode 6. For the resulting implantation results a maximum at a depth of approximately 1500 X with an area thickness of approximately 600 A *. If necessary, can the buried channel region can also be formed by means of diffusion or other doping methods. The gate electrode 6 can be made of metal, e.g. B. consist of aluminum, or in another way, e.g. B. with polycrystalline silicon formed will. The resulting structure can be used as a MOS device referred to as a buried channel, the one enclosed at the surface and separated from the substrate has isolated (further) channel.

A storage element must have at least two distinguishable from one another To be able to exhibit states. In addition, there must be the possibility of each of the states under the same Maintain conditions indefinitely or at least for a sufficiently long time relative to the switching frequencies. The semiconductor device discussed here falls into the second category in that one of its states is quasi-stable i

is and finally returns to the other possible stable state. The stable state for the proposed Semiconductor arrangement is indicated in the schematic cross section according to FIG. 1D. Those corresponding to FIG. 1A Reference numerals are chosen to be the same.

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As shown in Fig. 1B, the gate electrode 6 and the substrate 5 of each such element are applied to a DC bias of -10 V. Assuming that this bias is applied for a relatively long time, under these conditions, the surface of the substrate 5 and an inversion layer 8 is formed in the buried channel 2 adjacent to the insulating layer 7. This inversion layer 8 has the opposite conductivity type to the buried channel 2 and thus the same conductivity type as the substrate 5. The presence of such an inversion layer 8 indicates the equilibrium state or the stable state of the component 1. The inversion layer 8 results from the fact that holes are attracted into the depleted channel region and accumulate on the surface to form a P-conductive surface inversion layer. The remaining part of the implanted region 2 remains N-conductive and connects the N + -conductive source and drain regions 3 and 4. The component denoted by 1 in FIG. 1B is accordingly in the conductive or ON state, so that a current flows between areas 3 and 4 can take place. Under the specified bias conditions, the total voltage at the gate electrode 6 is over the insulating layer 7 ^; fall, since the applied electric field is terminated as a result of the positive charges present in the inversion layer 8. . ;

If one assigns the ON state, i. H. the conductive state, the binary meaning "1", becomes a more negative bias of the gate does not remove the P-conductive surface inversion layer 8 and the arrangement remains conductive.

Another possible state is the OFF state or the non-conductive or quasi-equilibrium state, which is based on is illustrated by Fig. 1C. Fig. 1C is similar to Fig. 1B except that buried layers 2 and the inversion layer 8 are not shown and that «in

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Depletion area 9 between areas 3 and 4 extends. The depletion area 9 does not contain any movable charge carriers, since these have disappeared as a result of the formation of the depletion region 9. More agile because of the non-existence Charge carriers cannot have any current between areas 3 and 4 flow so that the element 1 is in the non-conductive state.

In order to form such a depletion region 9, the negative bias on the gate electrode 6 becomes positive Voltage pulse superimposed. This positive voltage displaces the positive mobile charge carriers in the Inversion layer 8 are present. As a result, they remain in a lower concentration relative to the positive charge carriers existing negative mobile charge carriers. Will the positive pulse voltage on the original If the negative bias level is reduced, the remaining ones will be negative mobile charge carriers are also displaced, so that the area in question is mobile from all Load carriers is impoverished. Under these conditions, the electric field applied across the gate bias ceases on the positive charge carriers near the outer boundary of the depletion region 9, so that practically the entire voltage drop across the depletion region 9 in the silicon substrate 5 appears. The element labeled 1 is now in the non-conductive or quasi-stable state, in which no current flow takes place because there are no more mobile charge carriers in the depletion area. This non-conductive State is characterized as a quasi-stable state, since after a certain time that at room temperature up to a few Minutes, holes or positive charges j will get into the depletion area and the component 1 j thereby returning to the stable state illustrated in FIG. 1B, in which on the surface of the substrate 5 in the implanted channel region 2 an inversion layer 8 occurs.

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Around the non-conductive state illustrated in FIG. 1C to change to the conductive state, a negative impulse can be superimposed on the bias voltage. By hole injection or other mechanisms, e.g. B. recombination arrive Holes in the depletion area 9 are accelerated towards the surface of the substrate 5 and collect there to: renewed formation of an inversion layer 8. The electric field applied via the bias now ends at the Inversion layer 8} the component 1 is thus again in the state illustrated in FIG. 1B, so that a current flows can take place via negative movable charge carriers between source 3 and drain 4.

FIG. 2A illustrates a ribbon model for the one shown in FIG. 1B ^;

light state of equilibrium or the state of surface inversion shown. In Fig. 2A is perpendicular the JE \ stays awhile potential and horizontally the depth shown in the silicon substrate I. A conductive area is shown separated from the silicon by a dielectric or an oxide layer. j The reference numerals given in FIG. 2A correspond to those j of FIG. 1B. It thus corresponds to the area on the left _{ side of the gate electrode 6, while on the very right the P-conductive area of the substrate 5 is to be assumed. These two j regions are separated from one another by a dielectric 7. j The inversion layer 8 is at the interface 10 between! the dielectric 7 and the substrate 5 shown. The inclined line 11 in FIG. 2A indicates that the predominant voltage drop across the dielectric 7 occurs in this equilibrium state or in the state of surface inversion.

The further ribbon model shown in FIG. 2B for the state illustrated in FIG. 1B illustrates the relationships along the section line 2B-2B indicated in FIG. 2A and shows the energy distribution between source 3, drain 4 and buried channel 2. From FIG. 2B can be seen because fl because of

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the relatively low potential barrier in the channel region 2 between source 3 and drain 4 already when a very small voltage difference a current can flow.

Figure 2C shows a band model for the deep depletion state corresponding to Fig. 1C. Under the influence of the bias voltage V and after a positive pulse is applied to the gate electrode the element of FIG. 1C has that in FIG. 2C indicated character of the belt model. It should be noted that the slope 11 in Fig. 2C is not so steep as in Fig. 2A, from which it is clear that in this deep state of depletion only a small proportion of the applied Voltage across the dielectric 7 drops. By applying a positive potential to the gate electrode 6 the positive charges 8 in FIG. 2A are displaced and, in addition, negative mobile charge carriers are displaced by the transition from the positive voltage is removed to the negative bias value. The inclined belt edges 12 and the Fermi levels 13 indicated in FIG. 2D indicate that the greater proportion of the applied gate voltage drops over the depletion region in the silicon substrate 5.

The band model shown in FIG. 2D corresponds to that of FIG. 2B and explains the channel state in accordance with FIG. 1C. It shows the relationships along the ι section line 2D-2D indicated in FIG. 2C. 2D clearly shows the presence of i a high potential barrier in channel area 2, which indicates | indicates that channel 2 in the arrangement of Fig. 1C: is non-conductive. A comparison between FIGS. 2B and 2D j thus shows that two states, one conductive and another non-conductive, achieved with the component discussed here; can be. The addition ΐ illustrated with reference to FIG. 2B stand is stable, with the component remaining in the conductive state as long as the required bias voltages on; Component are maintained. However, the state illustrated in FIG. 2D is quasi-stable and increases

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after a period of time, typically several minutes, the relationships shown in the ribbon model of FIG. 2B as a result of leakage currents, recombinations or other phenomena.

With reference to Fig. 3A, the relationships are to be explained by means of the band models shown there, if the The component shown in FIG. 1B is switched from its conductive to the non-conductive state (FIG. 1C). As has already been mentioned, the switching takes place by applying a positive pulse to the gate electrode 6 of component 1 in Fig. 1D. Regarding the assignments of the left and right parts of the band models, refer to the Comments on FIGS. 2A and 2C are referred to. The middle band model in Fig. 3A shows an intermediate state of the device when a positive potential is applied to the gate electrode 6 is created. The positive gate voltage causes the ribbons to bend downward, eliminating the accumulated Holes 8 are displaced and free electrons are collected in the implanted channel 2. Although not particularly in Fig. 3A It should be noted that the transition of the positive pulse back to the original bias level causes the free electrons in the buried channel to be displaced and thus the ligaments under the influence the negative preload, as shown in the right belt model 3A, bent upwards. The component is therewith switched from conductive to non-conductive state.

3B shows the corresponding relationships in the band model when switching from the non-conductive to the conductive State under the influence of a negative pulse on the gate electrode 6. The assignment of the left and right Ribbon model areas for the corresponding structural areas of the semiconductor arrangement is again in the already mentioned Way to adopt. The left band model of FIG. 3B shows the component in the quasi-equilibrium state in which

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the buried channel 2 is completely depleted of all charge carriers and the applied potential predominantly over the silicon substrate falls off. The electric field is induced at the positive charge points near the limit of the End of the impoverishment area. By applying a negative potential, the ligaments are bent upwards, which is a result indicates that there is a higher voltage drop across the silicon. The resulting higher electric field accelerates the existing holes to the interface 11 between the Dielectric 7 and the silicon substrate 5. At the same time, as a result of recombination and leakage current processes existing negative mobile charge carriers displaced from the same interface 10. The transition from that through The potential superimposed on the pulse to the normal negative bias results in a downward bending of the ligament, which suggests that a lesser proportion of the applied potential drops across the silicon while the greater Share across the dielectric 7 drops. The applied electric field ends in the area of the positive charge carriers » which have accumulated at the oxide / semiconductor interface! and which there as an inversion layer 8 in the stable state of equilibrium remain. Thus, by applying a negative pulse to the gate electrode 6, the device becomes switched from the non-conductive to the conductive state. Referring to Fig. 4A, a circuit is explained, which contains the component of Fig. 1A and allows reading and writing of this component by using positive and negative control signals for switching on and off to the gate; Electrode can be applied. According to FIG. 4A, respectively Bias voltages of -10 V are applied to the gate electrode 6 and the substrate 5. The source 3 is as at ground potential ' shown lying, while the drain 4 via a resistor 14 j and a battery 15, which is used as a voltage source for the flow of current between source 3 and drain 4 when the component 1 ι is used, is at ground potential. One for sensing that which occurs across resistor 14 in the conductive state

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Read line 16 serving for a voltage drop is provided in parallel with resistor 14. To the switching state of the component 1, positive and negative write pulses can be sent to the gate electrode 6 in the manner shown in FIG. 4B of the component 1 are applied. As already in connection with the earlier FIGS. has been explained, the component 1 can be switched from the non-conductive to the conductive state by applying the negative voltage pulse 17 to the Gate electrode 6 is applied. If the component 1 is conductive, it can by applying a positive voltage pulse 18 to the gate electrode 6 can be made non-conductive. With conductive component 1, the current flow via source 3, the buried channel 2 and the drain 4 take place. A voltage drop across resistor 14 can then occur over the read line 16 can be sensed. In the case of a non-conductive component 1, on the other hand, no such current flow occurs.

FIG. 5A shows a circuit similar to that in FIG. 4A, in which only the write and read pulse! voltages are applied to the source 3 instead of to the gate electrode 6 \ . As is known, for a field effect transistor, when applied, the voltage at the gate can be determined opposite voltages at the source achieve the same mode of operation. In the circuit shown in FIG. 5A, a positive voltage pulse 19 corresponding to FIG. 5B is accordingly applied to source 3, whereby component 1 becomes conductive, while component 1 becomes non-conductive when a negative voltage pulse 20 is applied. If the component 1 is conductive, a positive read pulse 21 as shown in FIG. In this connection it should be noted that the non-conductive states in the circuits according to FIGS. 4A and 5A are quasi-stable states, so that after a certain time, which is relatively long and is a few minutes, this state in the

Equilibrium state corresponding to the conducting state and explained in more detail above transforms. Under normal operating conditions, however, it can be assumed that the (quasi-stable) non-conductive state is impressed or refreshed in each case by new information input to the to maintain respective memory information for the desired time. Usually this refresh operation by reading out the arrangement, sensing the respective state and rewriting the same state made in the component.

Fig. 6 shows a schematic circuit diagram in which a component of the type shown in Fig. 1A is used in connection with a memory circuit. In addition to the component According to FIG. 1A, this circuit contains an addressing FET, the gate and source of which are each marked with the word and bit lines are connected within the framework of an associated memory array. The one shown in FIG. 6 and designated by 22 The memory cell contains a MOS transistor 1 of the type described in more detail above. The MOS transistor 1 comprises a buried one Channel 2, a source 3, a drain 4, a gate electrode 6 and a dielectric 7. The source 3 is shown in FIG. 6 as Shown formed together with an addressing transit gate 23. The addressing transistor 23 contains a source diffusion region 24 and a gate electrode 25 which is arranged between the diffusion regions 3 and 24 and from which underlying channel region is separated by a dielectric 26. The diffusion region 24 is over the connection 27 is connected to the bit line 28, while the gate electrode 25 of the transistor 23 via the connection 29 with j is coupled to the word line 30 of the memory arrangement. The addressing FET 23 operates to normally is non-conductive until a corresponding potential from the pulse source 31 via the word line 30 to its gate electrode 25 arrives. As soon as the addressing FET 23 has become conductive, pulses from the pulse source

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reach the diffusion region 24 via the bit line 28 and the connection 27. Since the addressing transit gate 23 is now conductive is, a current flows into the common diffusion area 3, so that with impressing the potential ratios im Frame of the based on FIGS. FIGS. 5A and 5B, illustrated schemes, bring the transistor 1 into one of its two possible states and this state can be read out again. It should be noted in this context that a circuit the in Fig. 6 and in Figs. 4A and 5A, allows a non-destructive readout. Based on the The embodiment shown with a single memory cell is of course the expansion to a complex memory cell array I. with many memory cells and further selection lines according to the memory size required in each case possible.

In Fig. 7 6 is a plan view of an integrated embodiment of the memory cell of Fig. In a bit-organieierten j memory arrangement shown, the outer boundaries of the channel region (so-called. Recessed oxide) of the memory device from the substrate by <dielectric or Oxidisolationsgebiete j isolated are. It is clear from FIG. 7 that the topological design shown there is not the ring-shaped structure arrangement of the semiconductor arrangement mentioned in connection with the description of FIG. 1A, but a structure arrangement which would be referred to as a structure with an open channel whose channel surfaces are just insulated from the substrate by said dielectric isolation regions. The channel areas of both the memory component 1 and the addressing FET 23 can be delimited by the dielectric isolation areas at the channel area boundaries, the dielectric isolation areas being able to be produced in a manner known per se by pit etching and refilling.

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In the plan view of FIG. 7, the reference numerals corresponding to FIG. 6 are used. The one referred to as the bit line Select line is represented by diffusion strip 24. Furthermore, the word lines 30 are closed running transversely thereto recognize which form the gate electrodes 25 for the addressing FET 23. Adjacent to the gate electrode is in the substrate 5 a common diffusion region 3 can be seen in each case. Furthermore, the gate electrode 6 is for the actual memory components can be seen, which is preferably used as a silicon gate over the ion-implanted regions 2 and adjacent is arranged to the (drain) diffusion regions 4 in the substrate. The shaded areas in Fig. 7 are intended to be the dielectric Indicate isolation areas of the substrate 5. It is therefore clear that the channel area 2 as well as the channel under the gate electrode 25 at the ends in each case through the dielectric isolation regions in the substrate 5 of this are isolated so that leakage current paths that the deep depletion state would destroy are excluded. Of course, the structure arrangement indicated schematically in FIG. 7 can be used also run with vertical structural door arrangements instead of horizontally side by side elements 1 and 23.

The activation of a typical memory device 1 will cause Ipositive and negative voltage changes of about 5 V across l take about 2 microseconds to complete. Read signals with an amplitude of about 2 V were considered sufficient determined. However, these parameters are not critical and there can be wide variation depending on the particular Circuit design and the semiconductor materials used ι be realized. !

So much for the exemplary embodiments of N-channel components have proceeded, of course, the proposed measures can be taken with appropriate polarity reversal of the voltages and Build up conductivities with P-channel components as well.

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Finally, it should be noted that because of the proportionate long holding time of the non-conductive or quasi-stable state as well as because of the mechanisms that ultimately a Bring about transition to the stable state, the above-described, benign arrangements also as photon counters and light integrators! Can find use. On a transparently trained Light hitting the gate electrode will penetrate to the depletion layer on the semiconductor surface and there electron-hole pairs for each incident photon. The holes collect on the silicon surface and the electrons, in the duct area and are therefore available for a line operation. The photon-generated formation of charge carriers This adds up so that one can quantitatively draw conclusions about the respective photon dosage from the conductivity of the channel. For each such electron-hole pair generation and separation, the polarization voltage has an accelerating effect on the reduction of the deep state of depletion in the canal area. The maximum number of thus detectable photons corresponds to the number of those in the deep depletion state j electrons withdrawn from the gate.

The invention thus provides a single-element memory with a non-destructive read-out operation. As a result 'of the relatively long hold time only minor require- ments to j are any refresh provided. Since the size '

I of the read signal is determined from the width / length ratio of the memory component, its area size is only determined by the photolithographic tolerances. In addition, only a very low continuous power loss is consumed.

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Claims (10)

PATENT CLAIMS / 1. ) Semiconductor arrangement, in particular for a memory cell that can be read out non-destructively, with a MOS field effect transistor structure composed of source and drain doping regions of the opposite second conductivity type, arranged at a distance in a semiconductor substrate of a first conductivity type, between which there is a channel region over which by a dielectric a gate electrode is arranged separately, characterized in that in the channel region a doping region (2) connecting the source and drain doping regions (3, 4), extending from the surface of the substrate (5) into the latter and being closed off from the substrate material of the second conductivity type is provided, depending on the respective bias voltage setting or change on the gate electrode (6) and on the substrate (5), two distinguishable electrical conductivity states of the channel region can be set, of which the first (Fig. 1B) through the Vo In the presence of a surface inversion layer (8) which does not cover the entire depth of the doping region (2) provided in the channel region, with the conductive channel underneath and of which the second (Fig. 1C) is characterized by the presence of a deep depletion zone (9) which covers the entire depth of the doping region in the channel region. ' 2. Semiconductor arrangement according to claim 1, characterized in that with the gate electrode (6) pulse voltage sources for the provision of counter-phase pulses for setting the distinguishable conductivity states are coupled. ORIGINAL INSPECTED 3. Semiconductor arrangement according to claim 1, characterized in that that with the source doping region (3) pulse voltage sources to provide anti-phase Pulses for setting the distinguishable conductivity states are coupled. 4. Semiconductor arrangement according to at least one of the preceding claims, characterized in that the MOS field effect transistor structure in a per se known Way is designed as an annular structure with an annular channel area. 5. Semiconductor arrangement according to at least one of claims 1 to 3 _f, characterized in that the MOS field effect transistor structure is formed in a manner known per se with an elongated so-called. Open channel region, the channel region boundaries being closed by isolation regions. 6. Semiconductor arrangement according to claim 5, characterized in that the delimiting the channel region Isolation areas composed of dielectric isolation areas arranged in depressions in the semiconductor substrate, in particular oxide areas exist. 7. Semiconductor arrangement according to at least one of the preceding ' preceding claims, characterized in that In the same semiconductor substrate an additional MOS field effect transistor structure, known per se, is provided as an addressing field effect transistor (23), the drain doping area of which is formed by the source doping area (3) of the first semiconductor arrangement, and its source doping area (24) and its Gate electrode (25) are each connected to the selection lines of the memory cell in question.
YO 97 * oifi ROnR? Tf / 0 7 7? 275691b 8. Semiconductor arrangement according to at least one of the preceding claims «characterized in that with the drain doping region (4) circuit means for determining the conductivity state of the Channel area are coupled (Fign. 4Ά, 5A). 9. Semiconductor arrangement at least according to claim 1, characterized in that the doping region (2) of the second conductivity type provided in the channel region is an ion-implanted doping region with a penetration depth of approximately 1500R. 10. Semiconductor arrangement at least according to claim 1, characterized in that for their operation provided a substrate of the P conductivity type a negative basic bias voltage is applied to the gate electrode and to the substrate, which in the first of the two states as a result of the resulting accumulation of movable minority charge carriers an inversion layer forms on the surface that the other state is imprinted Basic bias voltage at the gate electrode a positive pulse is superimposed on this movable minority charge carrier displaced from the canal area, whereupon the restoration of the basic preload conditions also the remaining majority carriers from the deep depletion zone that thus comes about and characterizes the second state be suppressed, and that to rewrite the A temporary negative pulse is superimposed on a state of the basic bias, which is an accumulation of minority carriers in a comparative causes a thin surface inversion layer with the conductive channel subsequently remaining underneath. YO 976 016 80982fr / 0772