DE2937952A1 - NON-VOLATILE STORAGE ARRANGEMENT - Google Patents

Description

The invention relates to a non-volatile memory arrangement with a multiplicity of floating gate memory elements arranged in rows and columns and each formed in a semiconductor body or cells, each with a source zone, a drain zone, and one in between and channel region adjoining both the source region and the drain region with a PN junction, one above of the semiconductor body is insulated from it via a part of the channel zone adjoining the drain zone lying, a leading edge above the drain zone and a rear edge above the channel zone possessing floating gate and each with one above the floating gate and isolated from it and the semiconductor body arranged over the entire channel zone with a front flank above the drain zone and a rear flank control gate extending above the source zone. In particular, the invention relates to a new arrangement electrically variable or switchable floating gate cells.

Computers and related techniques have long required non-volatile read-only memory (ROM) cells. Accordingly, many components have been created which more or less meet the requirements meet well. The increasing complexity of the computer and the associated elements now has a need for electrical changeable or switchable read memories which are programmed (or "written to") and if necessary, can be reprogrammed (deleted and written) in the field. There are already components with non-volatile characteristics, which are intended to fulfill the aforementioned tasks. These components but have - as will be explained below - significant shortcomings that overcome those of the invention underlying task.

0300U / 0786

At one end of the spectrum of semiconductor memories is the class of floating gate avalanche metal oxide semiconductor components (FAMOS = Floating-Gate-Avalanche-Metal-Oxide-Semiconductor), while at the other end of this spectrum by the genus of metal-nitride-oxide-semiconductor components (MNOS = Metal-Nitride-Oxide-Semiconductor) is represented. The advantages of both component types result from their independence from any external stream to maintain a stored one Information in the event of a drop in performance; since these components are therefore independent in the above manner no further charging of the components is required. That means a considerable saving Energy.

The components of the floating gate family normally have source and drain regions of one conductivity type. These regions are usually formed in a substrate of the other conductivity type and on the surface thereof. Between the source and drain zone is on the substrate surface the gate structure is formed by applying a thin first insulating oxide layer. On the oxide layer is a conductive layer (the floating gate) is applied and then one that completely surrounds and opposes the floating gate the rest of the component insulating second insulating layer is formed. The second layer of insulation is applied then a second conductive layer (the control gate) is applied. These in U.S. Patents 3,500,143 and 3 755 721 explained floating gate components have the disadvantage that high fields to achieve the required for the Appearance of a charge on the floating gate required avalanche breakdown. Furthermore, it must entire component for erasing a charge present on the floating gate with energy from the ultraviolet or X-ray region of the spectrum are flooded. It is therefore extremely difficult to find a single "Word" without affecting the charge in the rest of the

030014/0786

To delete the component, so that the component must be completely reprogrammed as a rule. Another A significant disadvantage is that known components of the above type at low voltages a Have a tendency to Zener breakdowns at the drain-substrate junction. After all, after a relatively small one Number of charges and discharges (entering and deleting) known components a radical change in the Determine threshold or lock voltage with the result that in many cases the respective memory is replaced must become.

The invention is based on the object of creating a non-volatile memory arrangement of the type mentioned at the beginning, the individual cells of which are easily accessible for programming, reprogramming or reading and are equally easy how MNOS components are written to or deleted can. The solution according to the invention is that the control gates of the memory elements are connected together in a predetermined row that the source and Drain zones of each memory element in the given row are at the same time the drain zones or source zones of the respective adjacent memory element and that the source and drain zones of the memory elements in a predetermined Column are interconnected.

According to the invention, the structure of a non-volatile Floating gate type memory which is easy to manufacture in the form of an x-y matrix in which a single element at the intersection of a given row and a given column for programming, reprogramming and reading is easily accessible. The individual elements are also in the arrangement according to the invention characterized in that they can be written to or erased with the same ease as MNOS components are to be written or deleted.

030014/0786

In contrast to the teaching of the older registration
DE-OS 2 854 669 of the applicant avoids the uniformity or uniformity of the gates with one another and with respect to the channel zones in the subject matter of the invention. Rather, the floating gate according to the invention is shifted to the edge of the channel zone adjoining the drain zone in such a way that it extends with the so-called leading flank or edge over part of the drain zone. The control gate is insulated from the floating gate but brought into alignment with it in the part extending over the drain zone, while the other edge of the control gate extends over the edge (rear edge or rear edge) of the floating gate that is located at a distance and extends across the source-channel junction. The control gate is therefore distributed on two levels or arranged in two levels.

According to the invention, the electric field distributions in each storage element should be made such that each of these individual cells by a voltage applied between its control gate and its drain zone, but not through a voltage of similar polarity and magnitude as between its control gate and its source zone, "described" can be. The drain zone of an individual element can therefore be the same zone in the arrangement according to the invention be, which serves as the source zone of an adjacent individual element in the arrangement, so that the invention Storage arrangement is compact and with a high component density to be produced.

In the case of the electrically programmed according to the invention The floating gate readout memory arrangement extends the leading edge of the actual floating gate over the drain channel -Junction and extends over the drain zone, while the associated control gate all over the Channel zone with a rear flank extending over the source zone is sufficient. Settling the trailing edge of the

030014/0786

Floating gates from the source zone makes it possible to control the gate of each individual element in a given Series to be connected to a common line. In addition, the source and drain zones of a component can at the same time represent the drain and source zones of the next adjacent components of a row on either side. The common source-drain zones of the respective columns are connected together so that one becomes addressing memory arrangement arises.

Further details of the invention are explained on the basis of the schematic representation of exemplary embodiments. Show it:

1 shows a cross section of an individual element to be used in an xy arrangement;

2 shows a cross section through another floating gate component to be used in an xy arrangement; and

FIG. 3 shows a cross section of an xy arrangement of individual elements according to FIG. 1.

First of all, it should be noted that the subject of the invention of course with the help of insulators other than sapphire, such as spinel or beryllium oxide is to be carried out, albeit in the following statements, in particular with reference to FIG. 3 silicon-on-sapphire components (SOS) to be explained; however, sapphire is preferred. It should also be noted that a P-channel structure is described, but this one is only to be regarded as an exemplary embodiment, since the conduction type of the various component parts is of course in the Is to be exchanged within the scope of the invention.

030014/0786

1 shows a semiconductor component 10 having an insulating substrate 12 made of sapphire, spinel or beryllium oxide. As is known in SOS technology, a monocrystalline silicon layer is first deposited or formed on the sapphire substrate 12, divided into individual islands and then doped or implanted with impurities of one conductivity type in order to produce source zones 14.1 and drain zones 14.3 with channel zone 14.2 in between , wherein the channel zone is to be doped with impurities of the other conductivity type. In the illustrated embodiment, the source zone 14.1 and the drain zone 14.3 are P ⁺ -conducting, while the channel zone 14.2 has N ~ -line. After the islands have been produced, a gate oxide layer is formed on each and a polycrystalline silicon layer (polysilicon) is formed on top of this. The poly-silicon layer is intended to represent the floating gate 16. This is arranged so that its leading edge extends over the drain / channel junction and its trailing edge ends above the channel zone.

The control gate 20 is made above the floating gate 16. This is done first according to the shape of the floating gate 16, an oxide coating 22 is formed thereon. The result is that the on the floating gate 16 to be applied part of the control gate 20 is further away from the channel zone than the rest of the control gate 20. Subsequently, a second doped layer forming the control gate 20 is applied to the insulating oxide coating 22 Poly-silicon layer formed so that the leading edge of the control gate 20 is aligned with the leading edge of the floating gate 16, while the trailing edge of the control gate 20 covers the source / channel transition and extends beyond the source zone and in an area above from this ends. The entire component is then coated with a field oxide 30. To contact the

030014/0786

various component parts formed as above become contact openings for exposing corresponding parts produced by source zone 14.1, control gate 20 and drain zone 14.3. Then each of these component parts an electrical contact attached, as they have been designated in the drawing with 24, 26 and 28, respectively are.

Fig. 2 shows a structure according to the invention, in which Production of solid silicon was assumed. In which a predetermined dopant concentration having, solid silicon body 32, certain areas forming the source zones 34 and drain zones 38 are provided, which each enclose a channel zone 36 between them. When manufacturing, it is applied to the surface of the prepared Silicon body 32 applied a gate oxide layer 18 and formed thereon the floating gate 16, the so is made to extend partially across the drain / channel junction. The floating gate 16 is then with an insulating profile depicting the raised profile resulting from the presence of the floating gate 16 Field oxide layer 22 provided. Then the control gate 20 is formed so that one of its edges with the The edge of the floating gate 16 covering the drain / channel junction is in alignment, while the other edge of the floating gate is aligned 16 extends over the source / channel transition into the area above the source zone. It will also a field oxide 30 is provided for covering the control gate 20, and it becomes metallic - through the latter Conductors or contacts 24, 26 and 28 with direct ohmic contact to the source zone 34, to the control gate 20 and to the drain zone 38.

3 shows the cross section through a number of components of a matrix arrangement of memory elements shown in the individual elements similar to Fig. 1 and

030014/0786

2 and similar rows of components in the doped strips 52 in front of and behind the cutting plane and 54 are formed. The exemplary embodiment is, of course, described for the case of an SOS component similar or corresponding matrix arrangements can also be produced starting from solid silicon will.

In the exemplary embodiment according to FIG. 3, a monocrystalline silicon layer 14 is deposited on the surface of the substrate 14 made of sapphire and finally divided into P- and N -conductive zones in a known manner by doping. According to the drawing, floating gates 22 are arranged above the N ~ -conducting channel zones and insulated from them. In addition, in a manner similar to that shown and described with reference to FIGS. 1 and 2, a control gate 20 is arranged above the floating gate 22 so as to be insulated from the former. In the arrangement according to FIG. 3, all control gates 20 of each row are connected to a terminal 40 _{with the aid of a common line and connecting lines R 1 to R-, while}

all P zones 52 of a given column are connected to one another and switched to terminals 42 to 50 via connecting lines C to C.

If in the connecting lines ** -C _? corresponding cell a charge should be "written" can after
Above, all cells are "block-erased" in the direction of their highly conductive state by applying a negative voltage or a pulse to terminal 40 and a positive voltage or a pulse via terminals 42 to 50 to connecting lines C ₁ to C -

+ Ib

is given. As a result, a positive pulse is applied to all P diffusion lines. For the subsequent "writing" of the R ₃ C ₂ -ZeIIe in a low-conducting state, a negative pulse is given to terminal 44 and a positive pulse to terminal 40.

0300U / 0786

All other connections or terminals are earthed. In this way, the ^{floating gate corresponding to} _{the connecting lines R 2} ^C _{2 is} loaded with holes, while the neighboring cells ( ^R i- ^C i ^{and R} 3 ~ ^C 3 ^ remain unaffected. All cells of a given row - with the exception of the R ^ C ₃ -ZeIIe - are not influenced, because the respective source and drain regions are of these cells at the ground potential, and gates floating is not sufficient, the electric field intensity between the control electrode and the respective drain region for loading the But the RC ₃ -ZeIIe. remains unaffected because the full write voltage lies between its control gate and its source zone and not between the control gate and the drain zone R ^ C ₃ -ZeIIe is smaller under the given conditions than would be (at least) necessary to load this floating gate with holes.

An exemplary embodiment for producing an arrangement according to the invention is described below. Be it pointed out that other methods of producing the arrangement may also be suitable. In particular, can a method can be used in place of the SOS technique referred to in the following description which is based on solid silicon.

A substrate made of sapphire with a broad, flat main surface is provided, and an intrinsically conductive silicon layer 14 with a layer thickness of approximately 0.5 to 0.6 micrometers is deposited on this. The layer 14 is then divided up in islands to be doped or implanted, for example, with phosphorus, in a suitable manner, in order to introduce N-dopants and then, after masking, ^{to delimit P +} strips 52. At-

0300U / 0786

finally, this structure can be doped or implanted with, for example, boron in a known manner in order to form the P strips. The resulting structure shown in cross section in FIG. 3 then has alternating P ⁺ and N− strips 52 and 54, respectively.

After the P ⁺ and N ~ strips have been formed in the layer 14, a gate oxide layer corresponding to the gate oxide 18 of FIGS grown on the silicon layer 14 for about 30 minutes. The floating gate made of polycrystalline silicon is then formed on the gate oxide layer. This is done with the aid of a low pressure chemical vapor deposition process and is continued until the floating gate 16 (FIGS. 1 and 2) reaches a thickness of about 200 nm. This polysilicon layer is then masked in such a way that one of its edges ^{overlaps the transition between a P +} stripe 52 and an N ~ stripe 54. The mask is intended to define both boundaries of the floating gate 16, with one edge overlapping a drain / channel transition and the other edge ending or lying somewhere above the channel zone. The polysilicon layer is then etched away with the aid of hot ethylenediamine pyrocatechol and water solution at a temperature close to the boiling point of the etchant. As a result, both the leading edge and the trailing edge of the floating gate 16 according to FIGS. 1, 2 and 3 are limited.

Subsequently, a second oxide layer up to a thickness of grown about 80 to 90 nm, for example with the aid of wet oxygen (steam) at 900 ° C for a period of time of about 40 minutes. The net result of this process step is that immediately above of the floating gate an oxide layer with a thickness of

030014/0786

about 80 to 90 nm arises, which are not covered by the floating gate 16 to a thickness of about 100 nm above Area of the canal zone is tapered.

The process continues by depositing a polysilicon layer over the now stepped oxide to produce the control gate 20 (FIGS. 1 and 2). This is first deposited by depositing a polysilicon layer up to a thickness of about 600 nm with the aid of a known chemical low-pressure vapor deposition process. This second polysilicon layer is then masked and etched with the aid of the same type of solution as described with reference to the etching of the floating gate 16. In this case, the masking is carried out in such a way that an edge of the control gate 20 is aligned with the corresponding edge of the floating gate 16. To complete the arrangement, a further silicon oxide layer is then deposited onto the entire structure to a thickness of approximately 600 nm. This oxide layer can also be produced by chemical vapor deposition and - if it is deemed necessary - the last oxide coating can be compacted in an oxide atmosphere. The structure is then masked to form contact openings. This is followed by etching of the openings up to all control gates 20 and all P ⁺ strips or zones 52 with subsequent metallization in such a way that all control gates 20 of a given row are connected and each P ⁺ strip 52 is connected via a connecting line C ₁ , C ₂ , C ₃ , C ₄ and C _{5 is switched} to terminals 42, 44, 46, 48 and 50, respectively.

When using the structure described with reference to FIG with a matrix of floating gate memory cells arranged in rows and columns, it is clear to the person skilled in the art

030014/0786

that with the assignment and circuit according to the invention the source and drain zones of a specific one, which are provided with a specific floating gate / control gate combination Cell in a given row as drain zone or source zone of the next adjacent cell on both sides of the given row. In addition, there is insulation between the individual in the structure according to the invention Cells are not required, which saves a considerable amount of "floor space" and increases the packing density becomes possible.

030014/0786

Blank page

Claims (1)

Dr.-lng. Reimar König ■ Dipl.-Ing. Klaus Bergen Cecilienallee 76 A Düsseldorf 3O Telephone 452OO8 Patent Attorneys 18th September 1979
33 092 B RCA Corporation, 30 Rockefeiler Plaza,
New York, NY 10020 (V.St.A.) "Non-volatile memory array" Claim ^: Non-volatile memory arrangement with a multiplicity of floating gate memory elements arranged in rows and columns, each formed in a semiconductor body, each with a source zone, a drain zone, an intermediate zone and both to the source zone and to the drain zone with a PN junction adjacent channel zone, a floating gate above the semiconductor body insulated from it above a part of the channel zone adjoining the drain zone, a front edge above the drain zone and a rear edge above the channel zone, and with a floating gate each above the floating gate and isolated from this and the semiconductor body arranged over the entire channel zone with a front flank above the drain zone and a rear flank above the source zone extending control gate, characterized in that the control gates (20) of the memory elements are interconnected in a predetermined row, that the source and drain zones (5 2) each memory element in the given row is at the same time the drain zone (52) or source zone (52) of the respectively adjacent memory element and that the source and drain zones (52) of the memory elements are interconnected in a given column. 0300U / 0786