DE3169774D1 - Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache - Google Patents

Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache

Info

Publication number
DE3169774D1
DE3169774D1 DE8181400062T DE3169774T DE3169774D1 DE 3169774 D1 DE3169774 D1 DE 3169774D1 DE 8181400062 T DE8181400062 T DE 8181400062T DE 3169774 T DE3169774 T DE 3169774T DE 3169774 D1 DE3169774 D1 DE 3169774D1
Authority
DE
Germany
Prior art keywords
cache
memory
processors
data processing
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181400062T
Other languages
English (en)
Inventor
Pierre Charles Augustin Bacot
Michel Isert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE3169774D1 publication Critical patent/DE3169774D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1652—Handling requests for interconnection or transfer for access to memory bus based on arbitration in a multiprocessor architecture
    • G06F13/1663—Access to shared memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
DE8181400062T 1980-01-22 1981-01-19 Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache Expired DE3169774D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8001351A FR2474201B1 (fr) 1980-01-22 1980-01-22 Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache

Publications (1)

Publication Number Publication Date
DE3169774D1 true DE3169774D1 (en) 1985-05-15

Family

ID=9237760

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181400062T Expired DE3169774D1 (en) 1980-01-22 1981-01-19 Method and device to control the conflicts posed by multiple accesses to a same cache-memory of a digital data processing system comprising at least two processors each possessing a cache

Country Status (5)

Country Link
US (1) US4426681A (de)
EP (1) EP0032863B1 (de)
AT (1) ATE12708T1 (de)
DE (1) DE3169774D1 (de)
FR (1) FR2474201B1 (de)

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Also Published As

Publication number Publication date
EP0032863B1 (de) 1985-04-10
EP0032863A1 (de) 1981-07-29
FR2474201A1 (fr) 1981-07-24
FR2474201B1 (fr) 1986-05-16
US4426681A (en) 1984-01-17
ATE12708T1 (de) 1985-04-15

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Legal Events

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8339 Ceased/non-payment of the annual fee