DE3172469D1 - Process for patterning a layer, for forming a contact through hole - Google Patents

Process for patterning a layer, for forming a contact through hole

Info

Publication number
DE3172469D1
DE3172469D1 DE8181300607T DE3172469T DE3172469D1 DE 3172469 D1 DE3172469 D1 DE 3172469D1 DE 8181300607 T DE8181300607 T DE 8181300607T DE 3172469 T DE3172469 T DE 3172469T DE 3172469 D1 DE3172469 D1 DE 3172469D1
Authority
DE
Germany
Prior art keywords
patterning
hole
forming
layer
contact
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181300607T
Other languages
English (en)
Inventor
Makoto Nakajima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3172469D1 publication Critical patent/DE3172469D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
DE8181300607T 1980-02-14 1981-02-13 Process for patterning a layer, for forming a contact through hole Expired DE3172469D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1685880A JPS56114319A (en) 1980-02-14 1980-02-14 Method for forming contact hole

Publications (1)

Publication Number Publication Date
DE3172469D1 true DE3172469D1 (en) 1985-11-07

Family

ID=11927908

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181300607T Expired DE3172469D1 (en) 1980-02-14 1981-02-13 Process for patterning a layer, for forming a contact through hole

Country Status (4)

Country Link
US (1) US4354897A (de)
EP (1) EP0034483B2 (de)
JP (1) JPS56114319A (de)
DE (1) DE3172469D1 (de)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5871628A (ja) 1981-10-23 1983-04-28 Fujitsu Ltd 半導体装置の製造方法
JPS58204176A (ja) * 1982-05-24 1983-11-28 Kangiyou Denki Kiki Kk 化学的蝕刻方法
JPS59214240A (ja) * 1983-05-09 1984-12-04 Fujitsu Ltd 半導体装置の製造方法
US4508815A (en) * 1983-11-03 1985-04-02 Mostek Corporation Recessed metallization
US4484979A (en) * 1984-04-16 1984-11-27 At&T Bell Laboratories Two-step anisotropic etching process for patterning a layer without penetrating through an underlying thinner layer
US4719498A (en) * 1984-05-18 1988-01-12 Fujitsu Limited Optoelectronic integrated circuit
IT1213230B (it) * 1984-10-23 1989-12-14 Ates Componenti Elettron Processo planox a becco ridotto per la formazione di componenti elettronici integrati.
US4693783A (en) * 1984-12-31 1987-09-15 Gte Laboratories Incorporated Method of producing interconnections in a semiconductor integrated circuit structure
US4645562A (en) * 1985-04-29 1987-02-24 Hughes Aircraft Company Double layer photoresist technique for side-wall profile control in plasma etching processes
JPH0758718B2 (ja) * 1985-10-18 1995-06-21 三洋電機株式会社 化合物半導体装置の製造方法
US4702000A (en) * 1986-03-19 1987-10-27 Harris Corporation Technique for elimination of polysilicon stringers in direct moat field oxide structure
US4818725A (en) * 1986-09-15 1989-04-04 Harris Corp. Technique for forming planarized gate structure
JPH01255265A (ja) * 1988-04-05 1989-10-12 Nec Corp 半導体装置の製造方法
JPH02125422A (ja) * 1988-11-02 1990-05-14 Nec Corp 半導体装置の製造方法
JPH03266437A (ja) * 1990-03-16 1991-11-27 Toshiba Corp 半導体装置の製造方法
JP2932940B2 (ja) * 1994-06-08 1999-08-09 株式会社デンソー 薄膜抵抗体を有する半導体装置の製造方法
US5746884A (en) * 1996-08-13 1998-05-05 Advanced Micro Devices, Inc. Fluted via formation for superior metal step coverage
AU2002303842A1 (en) * 2001-05-22 2002-12-03 Reflectivity, Inc. A method for making a micromechanical device by removing a sacrificial layer with multiple sequential etchants
US6559048B1 (en) * 2001-05-30 2003-05-06 Lsi Logic Corporation Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning
JP4718725B2 (ja) * 2001-07-03 2011-07-06 Ｎｅｃ液晶テクノロジー株式会社 液晶表示装置の製造方法
US7297639B2 (en) 2005-09-01 2007-11-20 Micron Technology, Inc. Methods for etching doped oxides in the manufacture of microfeature devices
US20090011158A1 (en) * 2007-03-18 2009-01-08 Nanopass Technologies Ltd. Microneedle structures and corresponding production methods employing a backside wet etch
CN104425229A (zh) * 2013-09-10 2015-03-18 中国科学院微电子研究所 鳍片制造方法
CN103681306B (zh) * 2013-12-30 2016-08-17 国家电网公司 一种平缓光滑侧壁形貌的氮氧硅刻蚀方法
CN105225943B (zh) * 2015-10-26 2018-03-06 中国科学院微电子研究所 一种氧化硅的各向异性湿法腐蚀工艺中控制倾角的方法
US20210396989A1 (en) * 2018-11-26 2021-12-23 Corning Incorporated Methods for forming patterned insulating layers on conductive layers and devices manufactured using such methods

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3544401A (en) * 1967-05-16 1970-12-01 Texas Instruments Inc High depth-to-width ratio etching process
NL6903930A (de) * 1969-03-14 1970-09-16
JPS50134579A (de) * 1974-04-13 1975-10-24
DE2534043A1 (de) * 1975-07-30 1977-02-03 Siemens Ag Verfahren zur herstellung von loechern in auf halbleiterkoerpern befindlichen isolatorschichten
DE2723499A1 (de) * 1977-05-25 1978-12-07 Licentia Gmbh Verfahren zum herstellen eines fensters in einer isolierschicht bei halbleiteranordnungen
JPS6056286B2 (ja) * 1977-11-08 1985-12-09 富士通株式会社 半導体装置における電極窓の形成方法
DE2754066A1 (de) * 1977-12-05 1979-06-13 Siemens Ag Herstellung einer integrierten schaltung mit abgestuften schichten aus isolations- und elektrodenmaterial
DE2804830A1 (de) * 1978-02-04 1979-08-09 Bosch Gmbh Robert Verfahren zur herstellung einer halbleiteranordnung
US4148133A (en) * 1978-05-08 1979-04-10 Sperry Rand Corporation Polysilicon mask for etching thick insulator
DE2823855A1 (de) * 1978-05-31 1979-12-06 Fujitsu Ltd Verfahren zum herstellen einer halbleitervorrichtung

Also Published As

Publication number Publication date
EP0034483B1 (de) 1985-10-02
EP0034483B2 (de) 1988-11-02
JPS56114319A (en) 1981-09-08
US4354897A (en) 1982-10-19
EP0034483A3 (en) 1983-06-08
EP0034483A2 (de) 1981-08-26

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Legal Events

Date Code Title Description
8363 Opposition against the patent
8366 Restricted maintained after opposition proceedings
8339 Ceased/non-payment of the annual fee