DE3233414A1 - Circuit arrangement for detecting wrong or multiple usage in address-bus-controlled data systems - Google Patents

Abstract

In address-bus-controlled data systems with several modules (K1 to Kn) provided with one address decoder (A1 to An) each, wrong or multiple usage of a module is to be prevented. The invention achieves this by means of a central evaluating circuit (Z) with a threshold switch, the input of which is connected via a first collective line (KLA) to the outputs of each address decoder (A1 to An) and to the first input in each case of an AND gate (V1 to Vn) allocated to it and receives from each address decoder one acknowledgment pulse each in cyclic sequence in the case of the correct recognition of its associated address. The output of the central evaluating circuit is connected via a second collective line (KLS) to the second inputs in each case of the AND gates (V1 to Vn). It inhibits the affected AND gates, and thus the data transmission of the associated modules, both when the acknowledgment pulse from the associated channel decoder is missing due to wrong usage and with a faulty amplitude of this acknowledgement pulse due to multiple usage. <IMAGE>

Description

The invention relates to a circuit arrangement for

Detection of incorrect or multiple assignments in the case of address bus-controlled DMensystmen in which - controlled by address decoders - the data is serial or parallel are delivered to a data bus. A multiple or incorrect assignment of a The assembly is recognized in a central evaluation circuit and blocks during this Time the data outputs.

The object of the invention is to provide a circuit arrangement that which firstly prevents two or more assemblies from being on one at the same time Data bus work, which can lead to considerable damage to the hardware and secondly, it signals an incorrect assignment.

An obvious solution to this problem would be a digital recognition circuit that has the disjunctive form true = is equivalent to.

As can be seen from the above relationship, such a one leads Special decoder for an extensive wiring network with a large number of components.

The invention is based on the knowledge that it is used for Detection of multiple occupancy instead of digital multiple decoding is sufficient, Centrally control the voltage level in the respectively activated time slot.

The incorrect assignment to be distinguished from the multiple assignment is, however decentrally recognizable.

Based on this knowledge, the object of the invention is carried out those shown in claim 1 Features solved. Advanced training of the invention are characterized in the subclaims.

The advantages achieved by the invention are that for each assembly to be protected just a diode and a resistor, a link that blocks the data output pulse and any signaling equipment to be used are needed. Furthermore, all modules to be protected work on just one Collective line which leads to a central evaluation circuit and which in the case of the Incorrect or multiple assignment of a module via another collecting line Returns the signal to all modules at the same time. Another advantage is that only those systems are blocked that are affected by incorrect or multiple occupancy are.

The invention is explained in more detail below with reference to three figures.

1 shows a basic circuit diagram of an address bus-controlled System with the central evaluation circuit, Fig. 2 is an exemplary embodiment of the Invention based on an assembly which is designated as a channel card in FIG. 2, Fig. 3 shows an embodiment of the shown in Fig. 1 only as a circuit block central evaluation circuit.

1 shows the principle of the invention using the example of a non-hierarchical one Time division multiplex system with a data flow recommended by the CCITT of 34.368 Mbit / s, the data of 24 coded stereo broadcast signals as well as additional channel-specific signals and system-necessary information is transmitted. Each of the same assemblies K1 to Kn processes the data of a stereo signal with the associated channel-specific Parameters.

Via the control bus that can be seen on the left in Fig. 1 and the address bus the data pending in parallel is queried and stored here cyclically active on the data bus shown on the right in FIG. 1 for the duration of a time slot at.

The central evaluation circuit Z recognizes the first collecting line KLA whether exactly one module during a free slot with the output address is addressed and gives the result to all via the second collective line KLS Assemblies K1 to Kn back.

Fig. 2 shows the circuit arrangement according to the invention using the example of the assembly K1.

The address decoder A1 delivers when the channel address is recognized Acknowledgment pulse via a first bus line KhA to the central evaluation circuit Z. If there are no further acknowledgment pulses at the outputs KA2 at the same time ... yarn, the evaluation circuit Z is at the output (second collecting line KLS) a logical "1", which is the input of the channel evaluation M2.1 for multiple occupancy and that of the AND link V1 for the duration of the pulse from the address decoder A1 opens. This switches the data to the data bus and the display 2.1 signals the trouble-free operating status.

If the address decoder A1 does not recognize an address during a cycle, i.e. there is an incorrect assignment and no acknowledgment pulse is given, signaled the display 1.1 via the channel evaluation M1.1 for incorrect assignment of this state and there are no data from the module K to the data bus, because the AND link is already blocked via its first entrance. This also applies to all assemblies Kl to Kn.

An incorrect assignment (i.e. no valid address recognized) will be the result not only recognized in the central evaluation circuit, but already individually determined in each module based on the missing address for this module, but passed on to the central evaluation circuit.

If, on the other hand, two or more of the address decoders A7 to An deliver at the same time An acknowledgment pulse is received on the lines KAl ... KAn, this is only recognized by the central unit Evaluation circuit Z and blocks the output via the AND links V1 ... Vn of the data and only on those modules that benefit from multiple addressing are affected.

The displays M2.1 ... M2.n of all affected modules indicate this state.

Fig. 3 shows the circuit structure of the central evaluation circuit Z, with which the above-mentioned logical operation for recognizing the multiple occupancy can be realized.

The outputs KAI ... KAn of the address decoders of all modules are each Combined via a diode D 1 and a resistor R1 to form a common line KLA and switched to the input E1 of a threshold switch S. At the same time will a voltage UV across the resistor R2 to the input E1 of the threshold switch S supplied. At the input E2 of the threshold switch S there is a threshold voltage U2. If two or more assemblies are called at the same time, the value falls below the voltage u1 at the input E1 the voltage U2 at the input E2 of the threshold switch S. In this case, the output B1 of the threshold switch supplies S on the line KLS a signal: logical "O" = false, sent to all modules via lines gS1 ... KSn is supplied.

If only one assembly is addressed at a certain time, it If, for example, the line KAI is at zero potential, then the voltage U2 must be set so that that U2 <u1. The output B2 of the threshold switch S is then logical "1" = true.

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Claims (3)

Circuit arrangement for recognizing incorrect or multiple assignments in the case of address bus-controlled data systems (3) claims 1. Circuit arrangement for recognizing multiple or multiple assignments in address bus-controlled data systems with several assemblies each provided with an address decoder, d a d u r c h g e k e n n z e i c h n e t, d a B a) a central evaluation circuit (Z) with a Threshold switch is provided, b) the input via a first collecting line (eleven) with the outputs of each address decoder (A1 to An) and the first in each case Input of this associated AND operation (V1 to Vn) is connected and from each address decoder in the case of correct recognition of the address assigned to it receives an acknowledgment pulse in a cyclical sequence, c) the one with its output Via a second collecting line (KLS) with the respective second inputs of the AND links (V1 to Vn) is connected and both in the absence of an acknowledgment pulse from the associated Xanal decoder as a result of incorrect assignment as well as with incorrect amplitude of this acknowledgment pulse as a result of multiple occupancy, the affected AND links and thus the data transfer locks the assigned assemblies (Fig. 2). 2. Circuit arrangement according to claim 1, characterized in that d) that the outputs of the address decoders (EA1 to KAn) are connected in series a decoupling diode (I) with a resistor (R1) with the first bus line (K and the first input (El) of the threshold switch (s) are connected to the a voltage (Uv) is also supplied, e) that on the second Input (E2) of the threshold value switch has a threshold voltage (U2) which is exceeded the output of a logical "1" with the consequence of the release, which is below the limit the output of a logical "O" with the result that the individual address decoders are blocked associated AND-links triggers (Fig. 2, Fig. 3). 3. Circuit arrangement according to claim 1 and 2, characterized in that that for each module a channel evaluation for incorrect assignment (Mi,?) and multiple assignment (X2.1) provided with a downstream optical or acoustic display the channel evaluation for incorrect assignment (X1.1) only from the address decoder (Al), the channel evaluation for multiple occupancy (M2.1) also from the output of the central Evaluation circuit (Z) is controlled (Fig. 2).