DE3274021D1 - Automatic wafer alignment method, method for determining the location of edges and wafer alignment system - Google Patents

Automatic wafer alignment method, method for determining the location of edges and wafer alignment system

Info

Publication number
DE3274021D1
DE3274021D1 DE8282110263T DE3274021T DE3274021D1 DE 3274021 D1 DE3274021 D1 DE 3274021D1 DE 8282110263 T DE8282110263 T DE 8282110263T DE 3274021 T DE3274021 T DE 3274021T DE 3274021 D1 DE3274021 D1 DE 3274021D1
Authority
DE
Germany
Prior art keywords
wafer alignment
edges
location
determining
automatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8282110263T
Other languages
English (en)
Inventor
Lawrence S Green
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TRE SEMICONDUCTOR EQUIPMENT CORP
Original Assignee
TRE SEMICONDUCTOR EQUIPMENT CORP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TRE SEMICONDUCTOR EQUIPMENT CORP filed Critical TRE SEMICONDUCTOR EQUIPMENT CORP
Application granted granted Critical
Publication of DE3274021D1 publication Critical patent/DE3274021D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7088—Alignment mark detection, e.g. TTR, TTL, off-axis detection, array detector, video detection
DE8282110263T 1981-11-09 1982-11-06 Automatic wafer alignment method, method for determining the location of edges and wafer alignment system Expired DE3274021D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/319,782 US4475122A (en) 1981-11-09 1981-11-09 Automatic wafer alignment technique

Publications (1)

Publication Number Publication Date
DE3274021D1 true DE3274021D1 (en) 1986-12-04

Family

ID=23243631

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8282110263T Expired DE3274021D1 (en) 1981-11-09 1982-11-06 Automatic wafer alignment method, method for determining the location of edges and wafer alignment system

Country Status (4)

Country Link
US (1) US4475122A (de)
EP (2) EP0143893B1 (de)
JP (1) JPS58121628A (de)
DE (1) DE3274021D1 (de)

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Also Published As

Publication number Publication date
EP0079070A1 (de) 1983-05-18
US4475122A (en) 1984-10-02
EP0143893A1 (de) 1985-06-12
EP0079070B1 (de) 1986-10-29
JPS58121628A (ja) 1983-07-20
EP0143893B1 (de) 1988-06-08

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Legal Events

Date Code Title Description
8380 Miscellaneous part iii

Free format text: DER PATENTINHABER LAUTET RICHTIG: AMERICAN SEMICONDUCTOR EQUIPMENT TECHNOLOGIES, WOODLAND HILLS, CALIF., US

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee