DE3277710D1 - Clearing invalid addresses in cache memory - Google Patents
Clearing invalid addresses in cache memoryInfo
- Publication number
- DE3277710D1 DE3277710D1 DE8282304086T DE3277710T DE3277710D1 DE 3277710 D1 DE3277710 D1 DE 3277710D1 DE 8282304086 T DE8282304086 T DE 8282304086T DE 3277710 T DE3277710 T DE 3277710T DE 3277710 D1 DE3277710 D1 DE 3277710D1
- Authority
- DE
- Germany
- Prior art keywords
- cache memory
- invalid addresses
- clearing invalid
- clearing
- addresses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
- G06F12/0808—Multiuser, multiprocessor or multiprocessing cache systems with cache invalidating means
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/289,663 US4525777A (en) | 1981-08-03 | 1981-08-03 | Split-cycle cache system with SCU controlled cache clearing during cache store access period |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3277710D1 true DE3277710D1 (en) | 1987-12-23 |
Family
ID=23112533
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8282304086T Expired DE3277710D1 (en) | 1981-08-03 | 1982-08-03 | Clearing invalid addresses in cache memory |
Country Status (9)
Country | Link |
---|---|
US (1) | US4525777A (de) |
EP (1) | EP0072179B1 (de) |
JP (1) | JPS5823375A (de) |
KR (1) | KR880000299B1 (de) |
AU (1) | AU550924B2 (de) |
CA (1) | CA1173565A (de) |
DE (1) | DE3277710D1 (de) |
MX (1) | MX158195A (de) |
YU (1) | YU44081B (de) |
Families Citing this family (51)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2127189B (en) * | 1982-09-18 | 1986-11-05 | Int Computers Ltd | Automatic invalidation of validity tags in data store |
US4847902A (en) * | 1984-02-10 | 1989-07-11 | Prime Computer, Inc. | Digital computer system for executing encrypted programs |
US4755928A (en) * | 1984-03-05 | 1988-07-05 | Storage Technology Corporation | Outboard back-up and recovery system with transfer of randomly accessible data sets between cache and host and cache and tape simultaneously |
US4638431A (en) * | 1984-09-17 | 1987-01-20 | Nec Corporation | Data processing system for vector processing having a cache invalidation control unit |
US4695943A (en) * | 1984-09-27 | 1987-09-22 | Honeywell Information Systems Inc. | Multiprocessor shared pipeline cache memory with split cycle and concurrent utilization |
JPS6180438A (ja) * | 1984-09-28 | 1986-04-24 | Nec Corp | キヤツシユメモリ |
DE3686291T2 (de) * | 1985-05-29 | 1993-03-11 | Toshiba Kawasaki Kk | Cache-anordnung mit einem lru-verfahren und magnetscheibensteuereinrichtung mit einer solchen anordnung. |
US5241638A (en) * | 1985-08-12 | 1993-08-31 | Ceridian Corporation | Dual cache memory |
US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
JPH07113903B2 (ja) * | 1987-06-26 | 1995-12-06 | 株式会社日立製作所 | キャッシュ記憶制御方式 |
US5214770A (en) * | 1988-04-01 | 1993-05-25 | Digital Equipment Corporation | System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command |
EP0349123B1 (de) * | 1988-06-27 | 1995-09-20 | Digital Equipment Corporation | Mehrprozessorrechneranordnungen mit gemeinsamem Speicher und privaten Cache-Speichern |
US4920536A (en) * | 1988-10-14 | 1990-04-24 | Amdahl Corporation | Error recovery scheme for destaging cache data in a multi-memory system |
US5226146A (en) * | 1988-10-28 | 1993-07-06 | Hewlett-Packard Company | Duplicate tag store purge queue |
US5222224A (en) * | 1989-02-03 | 1993-06-22 | Digital Equipment Corporation | Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system |
JP2601951B2 (ja) * | 1991-01-11 | 1997-04-23 | 株式会社東芝 | 半導体集積回路 |
US5530835A (en) * | 1991-09-18 | 1996-06-25 | Ncr Corporation | Computer memory data merging technique for computers with write-back caches |
JPH06318174A (ja) * | 1992-04-29 | 1994-11-15 | Sun Microsyst Inc | キャッシュ・メモリ・システム及び主メモリに記憶されているデータのサブセットをキャッシュする方法 |
US5603005A (en) * | 1994-12-27 | 1997-02-11 | Unisys Corporation | Cache coherency scheme for XBAR storage structure with delayed invalidates until associated write request is executed |
US5717942A (en) * | 1994-12-27 | 1998-02-10 | Unisys Corporation | Reset for independent partitions within a computer system |
US5701313A (en) * | 1995-02-24 | 1997-12-23 | Unisys Corporation | Method and apparatus for removing soft errors from a memory |
US5511164A (en) * | 1995-03-01 | 1996-04-23 | Unisys Corporation | Method and apparatus for determining the source and nature of an error within a computer system |
US6279098B1 (en) | 1996-12-16 | 2001-08-21 | Unisys Corporation | Method of and apparatus for serial dynamic system partitioning |
US5875201A (en) * | 1996-12-30 | 1999-02-23 | Unisys Corporation | Second level cache having instruction cache parity error control |
US5960455A (en) * | 1996-12-30 | 1999-09-28 | Unisys Corporation | Scalable cross bar type storage controller |
US5822766A (en) * | 1997-01-09 | 1998-10-13 | Unisys Corporation | Main memory interface for high speed data transfer |
US5970253A (en) * | 1997-01-09 | 1999-10-19 | Unisys Corporation | Priority logic for selecting and stacking data |
US5860093A (en) * | 1997-01-21 | 1999-01-12 | Unisys Corporation | Reduced instruction processor/storage controller interface |
US7069391B1 (en) | 2000-08-30 | 2006-06-27 | Unisys Corporation | Method for improved first level cache coherency |
US6928517B1 (en) | 2000-08-30 | 2005-08-09 | Unisys Corporation | Method for avoiding delays during snoop requests |
US6857049B1 (en) | 2000-08-30 | 2005-02-15 | Unisys Corporation | Method for managing flushes with the cache |
US6697925B1 (en) | 2000-12-22 | 2004-02-24 | Unisys Corporation | Use of a cache ownership mechanism to synchronize multiple dayclocks |
US6785775B1 (en) | 2002-03-19 | 2004-08-31 | Unisys Corporation | Use of a cache coherency mechanism as a doorbell indicator for input/output hardware queues |
US8842127B1 (en) * | 2005-04-25 | 2014-09-23 | Apple Inc. | Text rendering with improved glyph cache management |
US8232860B2 (en) | 2005-10-21 | 2012-07-31 | Honeywell International Inc. | RFID reader for facility access control and authorization |
CN101765835B (zh) * | 2007-05-28 | 2013-05-08 | 霍尼韦尔国际公司 | 用于配置访问控制装置的系统和方法 |
US8598982B2 (en) * | 2007-05-28 | 2013-12-03 | Honeywell International Inc. | Systems and methods for commissioning access control devices |
US20110071929A1 (en) * | 2008-01-30 | 2011-03-24 | Honeywell International Inc. | Systems and methods for managing building services |
WO2010039598A2 (en) | 2008-09-30 | 2010-04-08 | Honeywell International Inc. | Systems and methods for interacting with access control devices |
WO2010099575A1 (en) | 2009-03-04 | 2010-09-10 | Honeywell International Inc. | Systems and methods for managing video data |
EP2408984B1 (de) | 2009-03-19 | 2019-11-27 | Honeywell International Inc. | Systeme und verfahren zur verwaltung von zugangssteuerungsvorrichtungen |
US9280365B2 (en) * | 2009-12-17 | 2016-03-08 | Honeywell International Inc. | Systems and methods for managing configuration data at disconnected remote devices |
US8707414B2 (en) * | 2010-01-07 | 2014-04-22 | Honeywell International Inc. | Systems and methods for location aware access control management |
US8787725B2 (en) | 2010-11-11 | 2014-07-22 | Honeywell International Inc. | Systems and methods for managing video data |
US9894261B2 (en) | 2011-06-24 | 2018-02-13 | Honeywell International Inc. | Systems and methods for presenting digital video management system information via a user-customizable hierarchical tree interface |
US10362273B2 (en) | 2011-08-05 | 2019-07-23 | Honeywell International Inc. | Systems and methods for managing video data |
US9344684B2 (en) | 2011-08-05 | 2016-05-17 | Honeywell International Inc. | Systems and methods configured to enable content sharing between client terminals of a digital video management system |
WO2013020165A2 (en) | 2011-08-05 | 2013-02-14 | HONEYWELL INTERNATIONAL INC. Attn: Patent Services | Systems and methods for managing video data |
WO2013101151A1 (en) * | 2011-12-30 | 2013-07-04 | Intel Corporation | Improved cache circuit having a tag array with smaller latency than a data array |
US10523903B2 (en) | 2013-10-30 | 2019-12-31 | Honeywell International Inc. | Computer implemented systems frameworks and methods configured for enabling review of incident data |
US10901908B2 (en) | 2019-01-16 | 2021-01-26 | International Business Machines Corporation | Storing data into a memory |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3735360A (en) * | 1971-08-25 | 1973-05-22 | Ibm | High speed buffer operation in a multi-processing system |
US3771137A (en) * | 1971-09-10 | 1973-11-06 | Ibm | Memory control in a multipurpose system utilizing a broadcast |
JPS5440182B2 (de) * | 1974-02-26 | 1979-12-01 | ||
US3967247A (en) * | 1974-11-11 | 1976-06-29 | Sperry Rand Corporation | Storage interface unit |
JPS51148334A (en) * | 1975-06-16 | 1976-12-20 | Hitachi Ltd | Buffer memory control method |
US4142234A (en) * | 1977-11-28 | 1979-02-27 | International Business Machines Corporation | Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system |
US4167782A (en) * | 1977-12-22 | 1979-09-11 | Honeywell Information Systems Inc. | Continuous updating of cache store |
US4169284A (en) * | 1978-03-07 | 1979-09-25 | International Business Machines Corporation | Cache control for concurrent access |
US4228503A (en) * | 1978-10-02 | 1980-10-14 | Sperry Corporation | Multiplexed directory for dedicated cache memory system |
US4245304A (en) * | 1978-12-11 | 1981-01-13 | Honeywell Information Systems Inc. | Cache arrangement utilizing a split cycle mode of operation |
JPS55134459A (en) * | 1979-04-06 | 1980-10-20 | Hitachi Ltd | Data processing system |
FR2472232B1 (fr) * | 1979-12-14 | 1988-04-22 | Honeywell Inf Systems | Dispositif et procede d'effacement d'antememoire |
US4322795A (en) * | 1980-01-24 | 1982-03-30 | Honeywell Information Systems Inc. | Cache memory utilizing selective clearing and least recently used updating |
US4439829A (en) * | 1981-01-07 | 1984-03-27 | Wang Laboratories, Inc. | Data processing machine with improved cache memory management |
CA1187198A (en) * | 1981-06-15 | 1985-05-14 | Takashi Chiba | System for controlling access to channel buffers |
US4403288A (en) * | 1981-09-28 | 1983-09-06 | International Business Machines Corporation | Methods and apparatus for resetting peripheral devices addressable as a plurality of logical devices |
US4442487A (en) * | 1981-12-31 | 1984-04-10 | International Business Machines Corporation | Three level memory hierarchy using write and share flags |
-
1981
- 1981-08-03 US US06/289,663 patent/US4525777A/en not_active Expired - Lifetime
-
1982
- 1982-03-17 AU AU81620/82A patent/AU550924B2/en not_active Ceased
- 1982-04-01 CA CA000400350A patent/CA1173565A/en not_active Expired
- 1982-04-14 MX MX192263A patent/MX158195A/es unknown
- 1982-06-03 JP JP57094130A patent/JPS5823375A/ja active Pending
- 1982-08-03 YU YU1691/82A patent/YU44081B/xx unknown
- 1982-08-03 DE DE8282304086T patent/DE3277710D1/de not_active Expired
- 1982-08-03 KR KR8203480A patent/KR880000299B1/ko active
- 1982-08-03 EP EP82304086A patent/EP0072179B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0072179B1 (de) | 1987-11-19 |
CA1173565A (en) | 1984-08-28 |
EP0072179A2 (de) | 1983-02-16 |
JPS5823375A (ja) | 1983-02-12 |
EP0072179A3 (en) | 1985-01-23 |
AU8162082A (en) | 1983-02-10 |
AU550924B2 (en) | 1986-04-10 |
KR840001368A (ko) | 1984-04-30 |
YU44081B (en) | 1990-02-28 |
US4525777A (en) | 1985-06-25 |
YU169182A (en) | 1985-03-20 |
KR880000299B1 (ko) | 1988-03-19 |
MX158195A (es) | 1989-01-16 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |