DE3322265A1 - Semiconductor device - Google Patents

Description

38 822

Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki-shi / Japan

Semiconductor device

The invention relates to a semiconductor device. In a conventional semiconductor device such as contains a vertical npn transistor, it is for the purpose of the saturation voltage VS between To keep the collector and emitter of this transistor at a small value and to limit the parasitic current, known to ring around a base region an η diffusion layer, which is generally known as η -collar is referred to as a collector area, and that a η -diffusion layer, which as Collector area is used, is generated in order to obtain an embedded η -area that corresponds to the reduction the collector resistance is used.

In a side pnp transistor semiconductor device, it is known to use the transistor area for the same purpose to be surrounded with an η collar.

Figure 1 shows a schematic cross section of a conventional semiconductor device with a vertical

pnp transistor. The same semiconductor device is shown in FIG. 2 in a schematic plan view. she has a p-substrate 2, an embedded η -layer 4, which is formed in the surface of this p-type substrate 2, and an η epitaxial layer 6, which over the p-substrate 2 and the embedded η -layer 4 is formed. A part of this epitaxial layer 6 is different from the rest Areas isolated by a ρ -Isolationsbereich 8. In the surface of the epitaxial layer 6 are a ρ region 10 and an η collar region 12 are formed. In the surface of the ρ-area 10 is, e.g. in the same Production stage ndt the η collar region 12, an η region 14 is formed. Electrodes 15, 16 and 17, which are hatched in Figs. 1 and 2, are in conductive contact with the ρ -region 10, the

η collar region 12 or the η region 14, namely through openings made in an insulating film 18 are. For the sake of simplicity of illustration, the insulating film 18 is omitted from FIG.

The emitter, base and collector of the vertical npn transistor of FIGS. 1 and 2 are represented by the η region 14, the ρ region 10 and the η and η layers 6 and 4 formed. In the semiconductor device of Figs. 1 and 2, a parasitic transistor exists. This consists of the ρ region 10 as the emitter, the η layer 6 as the base and the ρ-area 8 as the collector.

If the vertical npn transistor works in the saturation range, the parasitic pnp transistor has such an effect, that a fairly large parasitic current flows from the ρ region 10 via the η layer 6 to the ρ region 8.

An equivalent circuit diagram of the semiconductor device from FIGS. 1 and 2 is shown in FIG. It contains one npn transistor 20 whose base and collector are grounded to terminals V1 and V2 and whose emitter is grounded, and a pnp transistor 22, the emitter and base of which with the base and the collector of the npn transistor 20, respectively communicate while its collector is grounded. Transistors 20 and 22 correspond to the vertical one npn transistor on the one hand and the parasitic pnp transistor on the other hand from FIGS. 1 and 2. The connections V1 and V2 are electrodes 15 and 16.

If one takes a common base transistor for transistor 22 Current amplification factor al (* = 1), the current flowing to connection V1 is k »IB and the base current des Transistor 20 is IB, the parasitic current IP1, which is caused by transistor 22, after determined by the following equation:

IPl = al (k - I) IB (1)

If this parasitic current IP1 increases, it increases Potential of the substrate to ground. This leads to a latch-up effect and the parasitic one forms npn transistor through the ρ region 8 and two regions of the η epitaxial layer 6, which are on both sides of the ρ range 8 lie. This creates the possibility of malfunction of the vertical npn transistor.

4 and 5 show a schematic sectional view and a plan view, respectively, of a conventional semiconductor device with pnp transistor on the side. As with the semiconductor device of Figs. 1 and 2 are

here a p-substrate 2, an embedded η -layer 4, an n ~ epitaxial layer 6 and a ρ insulation region 8 are present. A ρ range 30, a ρ range 32, the the ρ region 30 surrounds and an η collar region 34, which in turn surrounds the ρ region 32, are on the Surface of the η epitaxial layer 6 is formed. In conductive connection with areas 30, 32 and 34 there are electrodes 35, 36 and 37, respectively.

The ρ region 30, the η epitaxial layer 6 and the ρ-area 34 form the emitter, base or collector of the lateral pnp transistor.

In this semiconductor device according to the riq. 4th and 5 a parasitic pnp transistor is formed, this being composed of the ρ region 32 as an emitter, the n ~ epitaxial layer 6 as a base and the ρ -Isolationsbereich 8 and the p-substrate 2 as a collector. While the lateral pnp transistor works in the saturation range, the parasitic pnp transistor leaves a considerably large parasitic current from the ρ region 32 via the η epitaxial layer 6 to the p-substrate and flow to the ρ region 8.

FIG. 6 shows the equivalent circuit diagram of the semiconductor device from FIGS. 4 and 5. This equivalent circuit diagram shows a pnp transistor 40, the base, emitter and collector of which is connected to the connections V3, V4 and V5, respectively a pnp transistor 42 with its base connected to the terminal V3, with its emitter connected to the terminal V5 and with its collector is due to mass. The transistors 40 and 42 correspond to the lateral pnp transistor and the parasitic one, respectively pnp transistor in FIGS. 4 and 5. The connections V3, V4, V5 correspond to the electrodes 37, 35 and 36, respectively.

Assuming a current gain factor of the
Transistor 42 in the base-emitter circuit of a.2
(»T), a current k'IB flowing from the terminal V3 and a base current of the transistor 40 of the size IB, the parasitic current IP2 results from the following equation:

IP2 β α2 - (k - I) IB. ₍₂ )

.. "■".

An increase in the parasitic current IP2 leads to the same problem as already discussed in connection with FIGS.
1 to 3 is described =

The invention is based on the object of a semiconductor device in which the flow of the parasitic current is suppressed and which is highly reliable is working.

The solution to this problem is with a semiconductor device achieved that a semiconductor substrate of a first conductivity type, a semiconductor layer of the opposite Conductivity type on this semiconductor substrate, one formed in the semiconductor layer

Transistor structure, a semiconductor region of the first conductivity type which is close to the transistor structure and
at least the surface region of the semiconductor layer is formed, and has means for electrically connecting this semiconductor region and the semiconductor layer.

The drawing shows in detail:

1 schematically shows a section through a conventional semiconductor device with a vertical transistor;

FIG. 2 is a plan view of the semiconductor device of FIG. 1;

3 shows the equivalent circuit diagram of the semiconductor device from FIGS. 1 and 2;

4 shows a schematic section through a semiconductor device conventional type with a lateral or lateral transistor;

5 shows the schematic plan view of the semiconductor device of Fig. 4;

6 shows the equivalent circuit diagram of the semiconductor device from FIGS. 4 and 5;

7 and 8 sectional illustration and plan view of a

A vertical transistor semiconductor device according to the present invention;
20th

9 shows the equivalent circuit diagram of the semiconductor device from FIGS. 7 and 8;

FIGS. 10 and 11 are a schematic sectional illustration and a plan view of a semiconductor device with a lateral transistor in a further embodiment of the invention;

12 shows the equivalent circuit diagram of the semiconductor device from FIGS. 10 and 11 and

13 and 14 a compared to the representations of the

Figs. 10 and 11 modified semiconductor device

in sectional or plan view. 35

Sectional view and plan view of a semiconductor device according to the invention according to FIGS. 7 and 8 included a vertical npn transistor. This semiconductor device is the same as that of FIGS. 1 and 2 Exception that a ρ region 70 is also formed in the surface zone of the η epitaxial layer 6, which is connected to the η collar area 12 and surrounds the ρ region 10. This ρ range 70 is with coupled to the η region 12 via an electrode 71 made at the location of the electrode 16 so that the ρ region 70 at the same potential as the η epitaxial layer 6 can be held.

In the semiconductor device shown in FIGS. 7 and 8, as already described earlier, a vertical npn transistor is produced by means of an η region 14, a ρ region 10 and an η epitaxial layer 6. This semiconductor device has a side PNP transistor in which the ρ region 10 is the emitter, the η epitaxial layer 6 is the base, and the ρ region 70 is the collector. During operation of the side pnp transistor, the additional current flowing away from the ρ region 10, which acts as the base of the vertical npn transistor, returns to the collector of the vertical npn transistor. . In addition, the semiconductor device in Fig 7 and 8 shown has a parasitic pnp transistor with the ρ region 10 as the emitter, the η epitaxial layer 6 as a base and the p-type substrate 2 and the ρ - region 8 as a collector such as at described earlier.

The equivalent circuit diagram of FIG. 9 is the same as that of FIG. 3 the exception that instead of the transistor 22 a multi-collector pnp transistor 72 is present, its first collector is connected to ground and whose second collector is connected to terminal V2. In other words,

the pnp transistor 72 corresponds to a combination of the side pnp transistor with the parasitic pnp transistor in Figs. 7 and 8.

The ratio of the current flowing from the ρ region 10 to the substrate 2 and to the ρ insulation region 8, namely the current IP3 flowing to the first collector of the transistor 72 to the current flowing from the ρ region 10 to the ρ region 70 flows, namely the current IF1, which flows through the second collector of transistor 72 flows can be represented by the following expression:

IP3 / IF1 = α4 / α3 ₍₃₎

Here, a3 is a current amplification factor of the lateral pnp transistor in base connection, aA is a current amplification factor of the parasitic pnp transistor in base connection, and a.3 and ct4 satisfy the following condition:

<x3 + <x4 <. 1 (4)

The base width of the lateral pnp transistor is determined by the distance between the ρ regions 10 and 70. The base width of the parasitic pnp transistor is determined by the distance between the ρ region 10 and the substrate or the ρ region 8. This makes it possible to specify a base width for the lateral pnp trans "* s ^J .or which has a sufficiently larger value than that of the parasitic pnp transistor, so that α.3 can be set to a value greater than a4. In In this case, a.4 receives a value that is sufficiently smaller than 1.

When the current k-iB into the terminal V1 and the current IB flows into the base of transistor 20, the following equation results:

IP3 + IFl = (a3 + ct4 ) (k - I) IB ( ₅ )

From the equations (3) and (5), the following equation can be obtained derive:

o3. a3

IP3 +. IP3 = o4 (l + ") (k-l) IB

a4 a4 .... (6)

The following equation can be obtained from equation (6):

IP3 = q4 · (k - I) IB (7) ι

The parasitic flow IP3 resulting from this equation (7). can be derived can be suppressed to a sufficiently smaller value than the parasitic current IP1 from equation (1) .· will . So even if the vertical npn transi-; disturbing in the saturation range is working in this way limits the parasitic current in the semiconductor device according to FIGS. 7 and 8 to a very small value, so that it does not affect the functioning of the vertical npn transistor.

10 and 11 are a schematic section and plan view a side pnp transistor semiconductor device according to another embodiment of the invention shown. This semiconductor device is similar to that in Figs. 4 and 5, but has the addition a ρ region that occurs in the surface of the n ~ epitaxial layer 6 and is connected to the η collar region in such a way that it surrounds the ρ region 30. This ρ region 80 is electrically coupled to the η region by means of an electrode 81 which, instead of the Electrode 37 is made so that the η region 80 is kept at the same potential as the n ~ epitaxial layer 6 can be.

As already described, the semiconductor device of Figs. 10 and 11 has a main PNP side transistor with ρ region 30, η epitaxial layer 6 and ρ region. This semiconductor device has an additional one lateral pnp transistor with ρ region 32 as emitter, η epitaxial layer 6 as base and ρ region 80 as a collector. When the additional lateral pnp transistor is in operation, the additional current flows from the ρ region 32, which is used as the collector of the main PNP side transistor serves, back to the base of this transistor. In addition, the semiconductor device shown in FIGS. 10 and 11 has η a parasitic pnp transistor with ρ region 32 as the emitter, η epitaxial layer 6 as the base and the substrate 2 and the ρ -Isolationsbereich 8 as a collector, as already described.

The equivalent circuit diagram of this semiconductor device shown in FIG is largely the same as that in FIG. 6, but with a instead of transistor 42 Mehrkollektpr-PNP transistor 82 occurs, the first of which Collector is connected to ground, while the second collector is connected to the connection V3. This transistor 82 corresponds to the combination of the additional lateral pnp transistor and the parasitic pnp transistor in Figs. 10 and 11.

The ratio of the current flowing from the ρ region 36 to the substrate 2 and from the ρ -Isolationsbereich 8 flows, namely the current IP4, which flows through the first collector of the transistor 82 flows to the current flowing from the ρ region 32 to the ρ region 80, namely the current IF2, the flowing through the second collector of transistor 82 is given by the following expression:

IP4 / IF2 = α6 / α5 ₍₈₎

where with α5 the current gain factor of the additional lateral pnp transistor in base circuit and with O.6 the current amplification factor of the parasitic pnp transistor are designated in the basic circuit, while ci5 and a6 satisfy the following expressions:

o5 + αδ <1 (9)

The base width of the additional lateral pnp transistor is determined by the distance between the ρ areas and 80 determined. The base width of the parasitic pnp transistor is determined by the distance between the ρ region and the substrate 4 or the ρ insulation region 8. It is therefore possible to set the base width of the additional lateral pnp transistor to a value which is sufficiently smaller than that of the parasitic pnp transistor. Thus a.5 can refer to a value that is sufficiently larger than a6.

In this case, a6 is given a value that is sufficiently smaller than 1.

k'IBI is the current flowing via terminal V3 while the base current of transistor 40 is IB1 and the emitter current of transistor 82 is IE while its base current is IB2. The following equations then apply:

IE = IP4 + IF2 + IB2 = (a5 + αβ) ΙΕ + IB2 ... (10)

k'IBl = IBl + IB2 + IF2 ... (11)

IF2 = O5 - .. IE ... (12)

IP4 = αβνΙΕ "... (13)

From equations (10) and (11) one obtains: 35

koIBl = IBl + IF2 + (1 - o5 - a6) IE ... (14)

Equations (12) and (14) result in: k'IBl = IBl + (1 - αβ) IE ... (15)

Equations (13) and (15) result in:

αβ

IP4 = - (Jc-I) -IBl ... (16)

1 - oc6

Since al is a value sufficiently smaller than 1, is also

- _Έ sufficiently smaller than 1. With IB = IB1, ι - <xo results

It can be seen from equations (2) and (16) that IP4 is sufficiently smaller than IP2. If in the in Fig. 10 11 and 11 also the side Main pnp transistor works in saturation range, the parasitic current is also suppressed to such a small value that it interferes with the functioning of the lateral Main pnp transistor not affected.

13 shows another variant of the semiconductor device 7 and 8. In this case, instead of the ρ region 70 from FIGS. 7 and 8, a ρ region becomes 90 is used, which surrounds the η collar region 12 and extends down to the embedded η layer 4. This ρ region 90 is connected to the η collar region 12 via an electrode 91. The ρ range 90 can can be formed in the same manufacturing stage as the ρ region 8.

In this embodiment, the additional current that flows sideways from the ρ region 10 flows, which acts as the base of the vertical npn transistor and as the emitter of the additional lateral pnp transistor, in the

p region 90; then the current is fed to the collector of the vertical npn transistor as a collector current. In other words, in this exemplary embodiment, the additional current suppresses the parasitic current an extremely small value, or that it flows into the substrate or the ρ region 8.

14 shows another modification of the semiconductor device of Figs. 10 and 11. This semiconductor device of FIG. 14 is the same as that in FIGS. 1Q and 11 except that a ρ-region 100 is used instead of the ρ region 80, which encloses the η collar region 34 and up to the embedded η layer 4 extends down. With the η collar area, the area 100 is conductive by means of an electrode 101 tied together. This ρ range 100 has the same effect as that 13, thus suppresses the parasitic current to a minimum.

The invention has been described above on the basis of specific exemplary embodiments, but this is not a limitation should be expressed in these forms of execution. For example, in the exemplary embodiments the η collar regions 12 and 34 and also the embedded η layer can be omitted. It is however, in these cases, the η-areas 70, 80, 90 and 100 then have to be at the same potential as the isolated one η epitaxial layer 6 to hold.

Although the ρ regions 70, 80, 90 and 100 are ring-shaped, they can be divided into numerous regions , and in such a case too, the parasitic current is suppressed to some extent. Of course, the opposite types of conductivity can be used instead of the conductivity types described.

In the described embodiments, the ρ are ranges 70, 80, 90 and 100 each formed directly in contact with the η collar regions 12 and 34; however, it is also possible to separate the individual η areas from the associated η collar areas.

Claims (1)

38 822 Tokyo Shibaura Denki Kabushiki Kaisha, Kawasaki-shi / Japan Semiconductor device claims ο semiconductor device with a semiconductor substrate a first conductivity type, a semiconductor layer of the opposite conductivity type on the semiconductor substrate and a transistor structure formed on the semiconductor layer characterized by a first semiconductor region (70; 80; 90; 100) of the first conductivity type, which is formed close to the transistor structure, and means (.71; 81; 91; 101) for the electrically conductive connection of the first semiconductor region (70; 80; 90; 100) with the semiconductor layer (6). 2, semiconductor device according to claim 1, characterized in that the transistor structure is a vertical transistor, which is composed of the semiconductor layer (6), a second semiconductor region (10) -the-first conductivity type that appears on the surface the semiconductor layer (6) is formed, and a third semiconductor region (14) of the opposite conductivity type, which is formed on the surface of the second half-rider area (10) consists. 3. Semiconductor device according to claim 2, characterized in that the first semiconductor region (70; 90) surrounding the second semiconductor region (10) is formed. 4. Semiconductor device according to claim 3, characterized in that a fourth semiconductor region (12) the opposite conductivity type, which has a higher concentration of impurities than the Has semiconductor layer (6), in the surface of the semiconductor layer (6) is fcrmiert and an electrode (71; 91) in the first and fourth semiconductor regions (70, 12; 90, 12) connects with each other. 5. The semiconductor device according to claim 3, characterized by a fifth semiconductor region (4) the opposite conductivity type with a higher concentration of impurities than the semiconductor layer (6), which is essentially formed in the surface of the semiconductor substrate (2). 6. Semiconductor device according to claim 5, characterized in that the first semiconductor region (90) is formed so that it extends down to the fifth semiconductor region (4). 7. Semiconductor device according to claim 6, characterized by a fourth semiconductor area (12) of the opposite conductivity type and with higher impurity concentration than the semiconductor layer (6) in the surface zone of the semiconductor layer (6) formed and conductive to the first semiconductor region (70; 90) by means of an electrode (71; 91) connected is. 8. The semiconductor device according to claim 1, characterized characterized in that the transistor structure as a lateral transistor made of the semiconductor layer (6) and a second and a third semiconductor area (30, 32) consists of the first conductivity type, which are separated from one another in the surface zone the semiconductor layer (6) are formed. 9. The semiconductor device according to claim 8, characterized characterized in that the second semiconductor region (32) encloses the first semiconductor area (30). 10. The semiconductor device according to claim 9, characterized in that ekennzeichne t that the first semiconductor region (80,100) the second semiconductor region (32) encloses. 11. The semiconductor device according to claim 10, marked-net by a fourth semiconductor region (34) of the opposite conductivity type and with a higher impurity concentration than the semiconductor layer (6) and an electrode (81; 101) through which the first and fourth semiconductor regions (80, 34; 100, 34) are connected to each other. 12. The semiconductor device according to claim 10, characterized by a fifth semiconductor region (4) of the opposite conductivity type and with a higher concentration of impurities than the semiconductor layer (6), which is essentially in the surface zone of the semiconductor substrate (2) is formed. 13. Semiconductor device according to claim 12, characterized in that it is characterized that the first semiconductor region (100) is formed down to the fifth semiconductor region (4). 14. Semiconductor device according to claim 8, characterized in that the first semiconductor region (80; 100) is designed as enclosing the second and third semiconductor regions (30, 32).