DE3380972D1 - Befehlsvorgriff in einem rechner. - Google Patents

Befehlsvorgriff in einem rechner.

Info

Publication number
DE3380972D1
DE3380972D1 DE8383306196T DE3380972T DE3380972D1 DE 3380972 D1 DE3380972 D1 DE 3380972D1 DE 8383306196 T DE8383306196 T DE 8383306196T DE 3380972 T DE3380972 T DE 3380972T DE 3380972 D1 DE3380972 D1 DE 3380972D1
Authority
DE
Germany
Prior art keywords
precaution
calculator
command
command precaution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8383306196T
Other languages
English (en)
Inventor
Russell W Guenthner
Kala J Marietta
Gary R Presley-Nelson
William A Shelly
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Bull HN Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull HN Information Systems Inc filed Critical Bull HN Information Systems Inc
Application granted granted Critical
Publication of DE3380972D1 publication Critical patent/DE3380972D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G06F9/3806—Instruction prefetching for branches, e.g. hedging, branch folding using address prediction, e.g. return stack, branch history buffer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute
DE8383306196T 1982-10-13 1983-10-13 Befehlsvorgriff in einem rechner. Expired - Fee Related DE3380972D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/434,197 US4594659A (en) 1982-10-13 1982-10-13 Method and apparatus for prefetching instructions for a central execution pipeline unit

Publications (1)

Publication Number Publication Date
DE3380972D1 true DE3380972D1 (de) 1990-01-18

Family

ID=23723211

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383306196T Expired - Fee Related DE3380972D1 (de) 1982-10-13 1983-10-13 Befehlsvorgriff in einem rechner.

Country Status (6)

Country Link
US (1) US4594659A (de)
EP (1) EP0106671B1 (de)
JP (1) JPS59132045A (de)
AU (1) AU573188B2 (de)
CA (1) CA1204219A (de)
DE (1) DE3380972D1 (de)

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JPH0769818B2 (ja) * 1984-10-31 1995-07-31 株式会社日立製作所 デ−タ処理装置
US5146570A (en) * 1984-10-31 1992-09-08 International Business Machines Corporation System executing branch-with-execute instruction resulting in next successive instruction being execute while specified target instruction is prefetched for following execution
US4761731A (en) * 1985-08-14 1988-08-02 Control Data Corporation Look-ahead instruction fetch control for a cache memory
US4763245A (en) * 1985-10-30 1988-08-09 International Business Machines Corporation Branch prediction mechanism in which a branch history table is updated using an operand sensitive branch table
JPH0743648B2 (ja) * 1985-11-15 1995-05-15 株式会社日立製作所 情報処理装置
US4755935A (en) * 1986-01-27 1988-07-05 Schlumberger Technology Corporation Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction
WO1987005417A1 (en) * 1986-02-28 1987-09-11 Nec Corporation Instruction prefetch control apparatus
EP0239081B1 (de) * 1986-03-26 1995-09-06 Hitachi, Ltd. Datenprozessor in Pipelinestruktur mit der Fähigkeit mehrere Befehle parallel zu dekodieren und auszuführen
US4888689A (en) * 1986-10-17 1989-12-19 Amdahl Corporation Apparatus and method for improving cache access throughput in pipelined processors
GB2200483B (en) * 1987-01-22 1991-10-16 Nat Semiconductor Corp Memory referencing in a high performance microprocessor
US4833599A (en) * 1987-04-20 1989-05-23 Multiflow Computer, Inc. Hierarchical priority branch handling for parallel execution in a parallel processor
US4991090A (en) * 1987-05-18 1991-02-05 International Business Machines Corporation Posting out-of-sequence fetches
JPS63317828A (ja) * 1987-06-19 1988-12-26 Fujitsu Ltd マイクロコ−ド読み出し制御方式
US4894772A (en) * 1987-07-31 1990-01-16 Prime Computer, Inc. Method and apparatus for qualifying branch cache entries
JPH0646382B2 (ja) * 1987-10-05 1994-06-15 日本電気株式会社 プリフェッチキュー制御方式
US5148525A (en) * 1987-11-30 1992-09-15 Nec Corporation Microprogram-controlled type bus control circuit
US4943908A (en) * 1987-12-02 1990-07-24 International Business Machines Corporation Multiple branch analyzer for prefetching cache lines
GB8728493D0 (en) * 1987-12-05 1988-01-13 Int Computers Ltd Jump prediction
US4876642A (en) * 1988-01-19 1989-10-24 Gibson Glenn A Rules and apparatus for a loop capturing code buffer that prefetches instructions
US5220669A (en) * 1988-02-10 1993-06-15 International Business Machines Corporation Linkage mechanism for program isolation
US4926323A (en) * 1988-03-03 1990-05-15 Advanced Micro Devices, Inc. Streamlined instruction processor
JP2722523B2 (ja) * 1988-09-21 1998-03-04 日本電気株式会社 命令先取り装置
US5067069A (en) * 1989-02-03 1991-11-19 Digital Equipment Corporation Control of multiple functional units with parallel operation in a microcoded execution unit
US5689670A (en) * 1989-03-17 1997-11-18 Luk; Fong Data transferring system with multiple port bus connecting the low speed data storage unit and the high speed data storage unit and the method for transferring data
CA2016068C (en) * 1989-05-24 2000-04-04 Robert W. Horst Multiple instruction issue computer architecture
US5179673A (en) * 1989-12-18 1993-01-12 Digital Equipment Corporation Subroutine return prediction mechanism using ring buffer and comparing predicated address with actual address to validate or flush the pipeline
AU7305491A (en) * 1990-01-29 1991-08-21 Teraplex, Inc. Architecture for minimal instruction set computing system
US5226130A (en) * 1990-02-26 1993-07-06 Nexgen Microsystems Method and apparatus for store-into-instruction-stream detection and maintaining branch prediction cache consistency
US5093778A (en) * 1990-02-26 1992-03-03 Nexgen Microsystems Integrated single structure branch prediction cache
US5163140A (en) * 1990-02-26 1992-11-10 Nexgen Microsystems Two-level branch prediction cache
US5230068A (en) * 1990-02-26 1993-07-20 Nexgen Microsystems Cache memory system for dynamically altering single cache memory line as either branch target entry or pre-fetch instruction queue based upon instruction sequence
DE69129872T2 (de) * 1990-03-27 1999-03-04 Philips Electronics Nv Datenverarbeitungssystem mit einem leistungsverbessernden Befehlscachespeicher
EP0471462B1 (de) * 1990-08-06 1998-04-15 NCR International, Inc. Verfahren zum Betrieb eines Rechnerspeichers und Anordnung
US5163139A (en) * 1990-08-29 1992-11-10 Hitachi America, Ltd. Instruction preprocessor for conditionally combining short memory instructions into virtual long instructions
US5454090A (en) * 1990-10-12 1995-09-26 Siemens Aktiengesellschaft Apparatus for furnishing instructions in a microprocessor with a multi-stage pipeline processing unit for processing instruction phase and having a memory and at least three additional memory units
US5226138A (en) * 1990-11-27 1993-07-06 Sun Microsystems, Inc. Method for selectively transferring data instructions to a cache memory
EP0496439B1 (de) * 1991-01-15 1998-01-21 Koninklijke Philips Electronics N.V. Rechneranordnung mit Mehrfachpufferdatencachespeicher und Verfahren dafür
US5285527A (en) * 1991-12-11 1994-02-08 Northern Telecom Limited Predictive historical cache memory
US5442767A (en) * 1992-10-23 1995-08-15 International Business Machines Corporation Address prediction to avoid address generation interlocks in computer systems
US5696958A (en) * 1993-01-11 1997-12-09 Silicon Graphics, Inc. Method and apparatus for reducing delays following the execution of a branch instruction in an instruction pipeline
US5511174A (en) * 1993-03-31 1996-04-23 Vlsi Technology, Inc. Method for controlling the operation of a computer implemented apparatus to selectively execute instructions of different bit lengths
US5870599A (en) * 1994-03-01 1999-02-09 Intel Corporation Computer system employing streaming buffer for instruction preetching
US5822576A (en) * 1997-03-26 1998-10-13 International Business Machines Corporation Branch history table with branch pattern field
JP2000172651A (ja) * 1998-12-03 2000-06-23 Nec Corp 非同期転送モード（ａｔｍ）セルパイプライン処理装置
EP1122246A1 (de) 2000-02-07 2001-08-08 Degussa AG Verfahren zur Epoxidierung von Olefinen
EP1122247A1 (de) 2000-02-07 2001-08-08 Degussa AG Verfahren zur Epoxidierung von Olefinen
EP1122248A1 (de) 2000-02-07 2001-08-08 Degussa AG Verfahren zur Epoxidierung von Olefinen
US6678817B1 (en) * 2000-02-22 2004-01-13 Hewlett-Packard Development Company, L.P. Method and apparatus for fetching instructions from the memory subsystem of a mixed architecture processor into a hardware emulation engine
DE50115570D1 (de) 2001-01-08 2010-09-09 Evonik Degussa Gmbh Verfahren zur Epoxidierung von Olefinen
US6608219B2 (en) 2001-06-13 2003-08-19 Degussa Ag Process for the epoxidation of olefins
US6596881B2 (en) 2001-06-13 2003-07-22 Degussa Ag Process for the epoxidation of olefins
US6600055B2 (en) 2001-06-13 2003-07-29 Degussa Ag Process for the epoxidation of olefins
US6749668B2 (en) 2001-06-18 2004-06-15 Degussa Ag Process for the recovery of combustible components of a gas stream
US6610865B2 (en) 2001-08-15 2003-08-26 Degussa Ag Process for the epoxidation of olefins
US6596883B2 (en) 2001-08-23 2003-07-22 Degussa Ag Process for the epoxidation of olefins
US8719837B2 (en) * 2004-05-19 2014-05-06 Synopsys, Inc. Microprocessor architecture having extendible logic
US20070073925A1 (en) * 2005-09-28 2007-03-29 Arc International (Uk) Limited Systems and methods for synchronizing multiple processing engines of a microprocessor
US8516181B1 (en) * 2009-03-31 2013-08-20 Micron Technology, Inc. Memory devices having data flow pipelining
US20130046964A1 (en) * 2011-08-15 2013-02-21 Noam DVORETZKI System and method for zero penalty branch mis-predictions

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Publication number Priority date Publication date Assignee Title
JPS6048173B2 (ja) * 1977-06-22 1985-10-25 株式会社東芝 真空掃除機
US4200927A (en) * 1978-01-03 1980-04-29 International Business Machines Corporation Multi-instruction stream branch processing mechanism
US4208716A (en) * 1978-12-11 1980-06-17 Honeywell Information Systems Inc. Cache arrangement for performing simultaneous read/write operations
US4325120A (en) * 1978-12-21 1982-04-13 Intel Corporation Data processing system
US4332010A (en) * 1980-03-17 1982-05-25 International Business Machines Corporation Cache synonym detection and handling mechanism
JPS6049340B2 (ja) * 1980-09-29 1985-11-01 日本電気株式会社 分岐命令先取り方式
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4521851A (en) * 1982-10-13 1985-06-04 Honeywell Information Systems Inc. Central processor
US4530052A (en) * 1982-10-14 1985-07-16 Honeywell Information Systems Inc. Apparatus and method for a data processing unit sharing a plurality of operating systems

Also Published As

Publication number Publication date
EP0106671A3 (en) 1986-07-16
AU2007883A (en) 1984-04-19
AU573188B2 (en) 1988-06-02
US4594659A (en) 1986-06-10
CA1204219A (en) 1986-05-06
EP0106671B1 (de) 1989-12-13
JPS59132045A (ja) 1984-07-30
JPS6341093B2 (de) 1988-08-15
EP0106671A2 (de) 1984-04-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: BULL HN INFORMATION SYSTEMS INC., BILLERICA, MASS.

8327 Change in the person/name/address of the patent owner

Owner name: INTEL CORP., SANTA CLARA, CALIF., US

8339 Ceased/non-payment of the annual fee