DE3484992D1 - Puffersteuersystem. - Google Patents

Puffersteuersystem.

Info

Publication number: DE3484992D1
Authority: DE; Germany
Prior art keywords: control system; buffer control; buffer; control
Prior art date: 1983-01-27
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.): Expired - Fee Related

Application number

DE8484100835T

Other languages

English (en)

Inventor

Kiyoshi C O Nec Corporati Hori

Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)

NEC Corp

Original Assignee

NEC Corp

Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)

1983-01-27

Filing date

1984-01-26

Publication date

1991-10-10

1984-01-26 Application filed by NEC Corp filed Critical NEC Corp

1991-10-10 Application granted granted Critical

1991-10-10 Publication of DE3484992D1 publication Critical patent/DE3484992D1/de

2004-01-27 Anticipated expiration legal-status Critical

Status Expired - Fee Related legal-status Critical Current

Links

Classifications

- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
- G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
- G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
- G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison

DE8484100835T 1983-01-27 1984-01-26 Puffersteuersystem. Expired - Fee Related DE3484992D1 (de)

Applications Claiming Priority (1)

Application Number	Priority Date	Filing Date	Title
JP58011841A JPS59136859A (ja)	1983-01-27	1983-01-27	バツフア制御装置

Publications (1)

Publication Number	Publication Date
DE3484992D1 true DE3484992D1 (de)	1991-10-10

Family

ID=11788950

Family Applications (1)

Application Number	Title	Priority Date	Filing Date
DE8484100835T Expired - Fee Related DE3484992D1 (de)	1983-01-27	1984-01-26	Puffersteuersystem.

Country Status (4)

Country	Link
US (1)	US4538226A (de)
EP (1)	EP0115344B1 (de)
JP (1)	JPS59136859A (de)
DE (1)	DE3484992D1 (de)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4754399A (en) *	1983-12-28	1988-06-28	Hitachi, Ltd.	Data transfer control system for controlling data transfer between a buffer memory and input/output devices
JPS62180470A (ja) *	1986-02-04	1987-08-07	Hitachi Ltd	ベクトル処理装置
US4805098A (en)	1986-05-05	1989-02-14	Mips Computer Systems, Inc.	Write buffer
JPH0823842B2 (ja) *	1986-09-30	1996-03-06	富士通株式会社	ストア・バッファのマージ方式
JPS63129437A (ja) *	1986-11-19	1988-06-01	Fujitsu Ltd	部分書き込み制御方式
DE69131763T2 (de) *	1990-08-31	2000-03-09	Texas Instruments Inc	Verfahren zur Kommunikation zwischen Prozessoren eines Mehrprozessorsystems
JP3191302B2 (ja) *	1990-12-28	2001-07-23	日本電気株式会社	メモリ回路
JP3164732B2 (ja)	1994-07-04	2001-05-08	富士通株式会社	データ処理装置
US5638534A (en) *	1995-03-31	1997-06-10	Samsung Electronics Co., Ltd.	Memory controller which executes read and write commands out of order
US5666494A (en) *	1995-03-31	1997-09-09	Samsung Electronics Co., Ltd.	Queue management mechanism which allows entries to be processed in any order
TW388982B (en) *	1995-03-31	2000-05-01	Samsung Electronics Co Ltd	Memory controller which executes read and write commands out of order
US5860107A (en) *	1996-10-07	1999-01-12	International Business Machines Corporation	Processor and method for store gathering through merged store operations
US6073190A (en)	1997-07-18	2000-06-06	Micron Electronics, Inc.	System for dynamic buffer allocation comprising control logic for controlling a first address buffer and a first data buffer as a matched pair
US6243769B1 (en)	1997-07-18	2001-06-05	Micron Technology, Inc.	Dynamic buffer allocation for a computer system
US6151658A (en) *	1998-01-16	2000-11-21	Advanced Micro Devices, Inc.	Write-buffer FIFO architecture with random access snooping capability
US8169440B2 (en) *	1999-04-09	2012-05-01	Rambus Inc.	Parallel data processing apparatus
US8174530B2 (en) *	1999-04-09	2012-05-08	Rambus Inc.	Parallel date processing apparatus
US20080184017A1 (en) *	1999-04-09	2008-07-31	Dave Stuttard	Parallel data processing apparatus
US20080007562A1 (en) *	1999-04-09	2008-01-10	Dave Stuttard	Parallel data processing apparatus
US7802079B2 (en) *	1999-04-09	2010-09-21	Clearspeed Technology Limited	Parallel data processing apparatus
US7627736B2 (en) *	1999-04-09	2009-12-01	Clearspeed Technology Plc	Thread manager to control an array of processing elements
US7966475B2 (en)	1999-04-09	2011-06-21	Rambus Inc.	Parallel data processing apparatus
US7506136B2 (en) *	1999-04-09	2009-03-17	Clearspeed Technology Plc	Parallel data processing apparatus
JP5285828B2 (ja) *	1999-04-09	2013-09-11	ラムバス・インコーポレーテッド	並列データ処理装置
GB2348971B (en) *	1999-04-09	2004-03-03	Pixelfusion Ltd	Parallel data processing systems
US20070294510A1 (en) *	1999-04-09	2007-12-20	Dave Stuttard	Parallel data processing apparatus
US20080016318A1 (en) *	1999-04-09	2008-01-17	Dave Stuttard	Parallel data processing apparatus
US20080008393A1 (en) *	1999-04-09	2008-01-10	Dave Stuttard	Parallel data processing apparatus
US8171263B2 (en) *	1999-04-09	2012-05-01	Rambus Inc.	Data processing apparatus comprising an array controller for separating an instruction stream processing instructions and data transfer instructions
US20080162874A1 (en) *	1999-04-09	2008-07-03	Dave Stuttard	Parallel data processing apparatus
US7526630B2 (en)	1999-04-09	2009-04-28	Clearspeed Technology, Plc	Parallel data processing apparatus
US20070242074A1 (en) *	1999-04-09	2007-10-18	Dave Stuttard	Parallel data processing apparatus
US8762691B2 (en) *	1999-04-09	2014-06-24	Rambus Inc.	Memory access consolidation for SIMD processing elements using transaction identifiers
US6678838B1 (en)	1999-08-23	2004-01-13	Advanced Micro Devices, Inc.	Method to track master contribution information in a write buffer
US9275003B1 (en) *	2007-10-02	2016-03-01	Sandia Corporation	NIC atomic operation unit with caching and bandwidth mitigation
US10168923B2 (en)	2016-04-26	2019-01-01	International Business Machines Corporation	Coherency management for volatile and non-volatile memory in a through-silicon via (TSV) module

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number	Priority date	Publication date	Assignee	Title
US4084234A (en) *	1977-02-17	1978-04-11	Honeywell Information Systems Inc.	Cache write capacity
US4156906A (en) *	1977-11-22	1979-05-29	Honeywell Information Systems Inc.	Buffer store including control apparatus which facilitates the concurrent processing of a plurality of commands
AU521383B2 (en)	1977-12-16	1982-04-01	Honeywell Information Systems Incorp.	Cache memory command circuit
US4245303A (en) *	1978-10-25	1981-01-13	Digital Equipment Corporation	Memory for data processing system with command and data buffering
US4225922A (en) *	1978-12-11	1980-09-30	Honeywell Information Systems Inc.	Command queue apparatus included within a cache unit for facilitating command sequencing

1983
- 1983-01-27 JP JP58011841A patent/JPS59136859A/ja active Granted
1984
- 1984-01-25 US US06/573,745 patent/US4538226A/en not_active Expired - Lifetime
- 1984-01-26 DE DE8484100835T patent/DE3484992D1/de not_active Expired - Fee Related
- 1984-01-26 EP EP84100835A patent/EP0115344B1/de not_active Expired - Lifetime

Also Published As

Publication number	Publication date
EP0115344A2 (de)	1984-08-08
EP0115344B1 (de)	1991-09-04
JPS6331813B2 (de)	1988-06-27
JPS59136859A (ja)	1984-08-06
EP0115344A3 (en)	1988-11-30
US4538226A (en)	1985-08-27

Legal Events

Date	Code	Title	Description
1992-10-01	8364	No opposition during term of opposition
1996-01-18	8339	Ceased/non-payment of the annual fee

Publication	Publication Date	Title
DE3484992D1 (de)	1991-10-10	Puffersteuersystem.
DE3481285D1 (de)	1990-03-15	Kraftkontrollsystem.
DE3483662D1 (de)	1991-01-10	Antiblockierregelsystem.
DK472084D0 (da)	1984-10-02	Xenogenisk udtrykkelsesstyrings-system
DE3380988D1 (de)	1990-01-25	Antiblockierregelsystem.
DE3481093D1 (de)	1990-02-22	Verteiltes bussteuerungssystem.
DE3483022D1 (de)	1990-09-27	Plattenansteuerungssystem.
DE3484319D1 (de)	1991-05-02	Digitales steuerungsgeraet.
DE3481298D1 (de)	1990-03-15	Antiblockierregelsystem.
DE3485487D1 (de)	1992-03-12	Steuerungssystem fuer pufferspeicher.
DE3484147D1 (de)	1991-04-04	Rechnersystem.
FI842384A0 (fi)	1984-06-13	Kontroll av datamaskinhierarki.
DE3484536D1 (de)	1991-06-06	Anzeigesteuersystem.
FI841290A0 (fi)	1984-03-30	Automatiskt system foer behandling av mineralullsrullar.
DE3484427D1 (de)	1991-05-16	Steuergeraet.
DE3381476D1 (de)	1990-05-23	Pufferspeichersteuerungsanordnung.
NO880603D0 (no)	1988-02-11	Styresystem.
DE3484500D1 (de)	1991-05-29	Pufferspeichersteuerungsanordnung.
FR2557918B1 (fr)	1988-09-23	Systeme de controle.
DE3484462D1 (de)	1991-05-23	Numerisches steuersystem.
NO163344C (no)	1990-05-09	Styreventil.
DK129884D0 (da)	1984-02-29	Datastyresystem
NO151754C (no)	1985-05-29	Systemforskaling.
DE3581001D1 (de)	1991-02-07	Regelsystem.
DE3483083D1 (de)	1990-10-04	Kontrollgeraet.