DE3485174D1 - Halbleiterspeicheranordnung. - Google Patents
Halbleiterspeicheranordnung.Info
- Publication number
- DE3485174D1 DE3485174D1 DE8484308237T DE3485174T DE3485174D1 DE 3485174 D1 DE3485174 D1 DE 3485174D1 DE 8484308237 T DE8484308237 T DE 8484308237T DE 3485174 T DE3485174 T DE 3485174T DE 3485174 D1 DE3485174 D1 DE 3485174D1
- Authority
- DE
- Germany
- Prior art keywords
- semiconductor memory
- memory arrangement
- arrangement
- semiconductor
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
- G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
- G11C7/1033—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58223121A JPS60117492A (ja) | 1983-11-29 | 1983-11-29 | 半導体記憶装置 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3485174D1 true DE3485174D1 (de) | 1991-11-21 |
Family
ID=16793141
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8484308237T Expired - Lifetime DE3485174D1 (de) | 1983-11-29 | 1984-11-28 | Halbleiterspeicheranordnung. |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US4707811A (de) |
| EP (1) | EP0143647B1 (de) |
| JP (1) | JPS60117492A (de) |
| KR (1) | KR900007225B1 (de) |
| DE (1) | DE3485174D1 (de) |
Families Citing this family (30)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60136086A (ja) * | 1983-12-23 | 1985-07-19 | Hitachi Ltd | 半導体記憶装置 |
| US4649522A (en) * | 1985-02-11 | 1987-03-10 | At&T Bell Laboratories | Fast column access memory |
| JPS6265298A (ja) * | 1985-09-17 | 1987-03-24 | Fujitsu Ltd | Ｅｐｒｏｍの書き込み方式 |
| JPS637591A (ja) * | 1986-06-25 | 1988-01-13 | Nec Corp | アドレスマルチプレクス型半導体メモリ |
| US4792929A (en) * | 1987-03-23 | 1988-12-20 | Zenith Electronics Corporation | Data processing system with extended memory access |
| JP2659436B2 (ja) * | 1989-08-25 | 1997-09-30 | 富士通株式会社 | 半導体記憶装置 |
| US5692148A (en) * | 1994-04-11 | 1997-11-25 | Intel Corporation | Method and apparatus for improving system memory cost/performance using extended data out (EDO)DRAM and split column addresses |
| US6112284A (en) * | 1994-12-30 | 2000-08-29 | Intel Corporation | Method and apparatus for latching data from a memory resource at a datapath unit |
| US5652724A (en) * | 1994-12-23 | 1997-07-29 | Micron Technology, Inc. | Burst EDO memory device having pipelined output buffer |
| US5598376A (en) * | 1994-12-23 | 1997-01-28 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
| US5721859A (en) * | 1994-12-23 | 1998-02-24 | Micron Technology, Inc. | Counter control circuit in a burst memory |
| US5729503A (en) * | 1994-12-23 | 1998-03-17 | Micron Technology, Inc. | Address transition detection on a synchronous design |
| US5640364A (en) * | 1994-12-23 | 1997-06-17 | Micron Technology, Inc. | Self-enabling pulse trapping circuit |
| US6804760B2 (en) | 1994-12-23 | 2004-10-12 | Micron Technology, Inc. | Method for determining a type of memory present in a system |
| US5675549A (en) * | 1994-12-23 | 1997-10-07 | Micron Technology, Inc. | Burst EDO memory device address counter |
| US5682354A (en) * | 1995-11-06 | 1997-10-28 | Micron Technology, Inc. | CAS recognition in burst extended data out DRAM |
| US6525971B2 (en) | 1995-06-30 | 2003-02-25 | Micron Technology, Inc. | Distributed write data drivers for burst access memories |
| US5668773A (en) * | 1994-12-23 | 1997-09-16 | Micron Technology, Inc. | Synchronous burst extended data out DRAM |
| US5526320A (en) * | 1994-12-23 | 1996-06-11 | Micron Technology Inc. | Burst EDO memory device |
| US5610864A (en) * | 1994-12-23 | 1997-03-11 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
| US5717654A (en) * | 1995-02-10 | 1998-02-10 | Micron Technology, Inc. | Burst EDO memory device with maximized write cycle timing |
| US5850368A (en) * | 1995-06-01 | 1998-12-15 | Micron Technology, Inc. | Burst EDO memory address counter |
| US5729504A (en) * | 1995-12-14 | 1998-03-17 | Micron Technology, Inc. | Continuous burst edo memory device |
| US7681005B1 (en) * | 1996-01-11 | 2010-03-16 | Micron Technology, Inc. | Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation |
| US5966724A (en) * | 1996-01-11 | 1999-10-12 | Micron Technology, Inc. | Synchronous memory device with dual page and burst mode operations |
| US6981126B1 (en) | 1996-07-03 | 2005-12-27 | Micron Technology, Inc. | Continuous interleave burst access |
| US6401186B1 (en) | 1996-07-03 | 2002-06-04 | Micron Technology, Inc. | Continuous burst memory which anticipates a next requested start address |
| US7103742B1 (en) | 1997-12-03 | 2006-09-05 | Micron Technology, Inc. | Burst/pipelined edo memory device |
| US7927948B2 (en) | 2005-07-20 | 2011-04-19 | Micron Technology, Inc. | Devices with nanocrystals and methods of formation |
| CN104869010B (zh) * | 2013-12-13 | 2021-06-18 | 马维尔以色列(M.I.S.L.)有限公司 | 保护切换 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5920193B2 (ja) * | 1977-08-17 | 1984-05-11 | 三菱電機株式会社 | スタテイックランダムアクセスメモリの出力バッファ回路 |
| US4250412A (en) * | 1979-03-05 | 1981-02-10 | Motorola, Inc. | Dynamic output buffer |
| JPS56101694A (en) * | 1980-01-18 | 1981-08-14 | Nec Corp | Semiconductor circuit |
| JPS6012718B2 (ja) * | 1980-03-28 | 1985-04-03 | 富士通株式会社 | 半導体ダイナミックメモリ |
| JPS5727477A (en) * | 1980-07-23 | 1982-02-13 | Nec Corp | Memory circuit |
| US4344156A (en) * | 1980-10-10 | 1982-08-10 | Inmos Corporation | High speed data transfer for a semiconductor memory |
| JPS5817583A (ja) * | 1981-07-21 | 1983-02-01 | Hitachi Ltd | 二次元デ−タ記憶装置 |
| JPS6042547B2 (ja) * | 1981-10-08 | 1985-09-24 | 三菱電機株式会社 | 半導体記憶装置 |
| JPS58220294A (ja) * | 1982-06-16 | 1983-12-21 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JPS58222479A (ja) * | 1982-06-18 | 1983-12-24 | Hitachi Ltd | 半導体メモリのデ−タ読み出し方式 |
| DE3243496A1 (de) * | 1982-11-24 | 1984-05-24 | Siemens AG, 1000 Berlin und 8000 München | Integrierte halbleiterschaltung mit einem dynamischen schreib-lese-speicher |
-
1983
- 1983-11-29 JP JP58223121A patent/JPS60117492A/ja active Granted
-
1984
- 1984-11-17 KR KR1019840007225A patent/KR900007225B1/ko not_active IP Right Cessation
- 1984-11-23 US US06/674,313 patent/US4707811A/en not_active Expired - Lifetime
- 1984-11-28 DE DE8484308237T patent/DE3485174D1/de not_active Expired - Lifetime
- 1984-11-28 EP EP19840308237 patent/EP0143647B1/de not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| EP0143647A3 (en) | 1988-03-16 |
| JPH0514358B2 (de) | 1993-02-24 |
| EP0143647B1 (de) | 1991-10-16 |
| US4707811A (en) | 1987-11-17 |
| KR900007225B1 (ko) | 1990-10-05 |
| KR850003610A (ko) | 1985-06-20 |
| EP0143647A2 (de) | 1985-06-05 |
| JPS60117492A (ja) | 1985-06-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |