DE3580946D1 - Verfahren und system zum verstehen und belegen von schaltungsmustern. - Google Patents

Verfahren und system zum verstehen und belegen von schaltungsmustern.

Info

Publication number
DE3580946D1
DE3580946D1 DE8585109414T DE3580946T DE3580946D1 DE 3580946 D1 DE3580946 D1 DE 3580946D1 DE 8585109414 T DE8585109414 T DE 8585109414T DE 3580946 T DE3580946 T DE 3580946T DE 3580946 D1 DE3580946 D1 DE 3580946D1
Authority
DE
Germany
Prior art keywords
understanding
circuit patterns
assigning circuit
assigning
patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585109414T
Other languages
English (en)
Inventor
Toshinori Watanabe
Tetsuya Masuishi
Koji Sasaki
Koichi Haruna
Noboru Horie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP15526184A external-priority patent/JPS6134674A/ja
Priority claimed from JP15525984A external-priority patent/JPS6134673A/ja
Priority claimed from JP15525784A external-priority patent/JPS6134671A/ja
Priority claimed from JP15525884A external-priority patent/JPS6134672A/ja
Priority claimed from JP59166050A external-priority patent/JPH0623988B2/ja
Priority claimed from JP59166350A external-priority patent/JPH067387B2/ja
Priority claimed from JP59166349A external-priority patent/JPS6145329A/ja
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Application granted granted Critical
Publication of DE3580946D1 publication Critical patent/DE3580946D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S706/00—Data processing: artificial intelligence
    • Y10S706/902—Application using ai with detail of the ai system
    • Y10S706/919—Designing, planning, programming, CAD, CASE
    • Y10S706/921—Layout, e.g. circuit, construction
DE8585109414T 1984-07-27 1985-07-26 Verfahren und system zum verstehen und belegen von schaltungsmustern. Expired - Lifetime DE3580946D1 (de)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
JP15526184A JPS6134674A (ja) 1984-07-27 1984-07-27 電子回路レイアウト方法
JP15525984A JPS6134673A (ja) 1984-07-27 1984-07-27 回路信号伝播経路認識方法
JP15525784A JPS6134671A (ja) 1984-07-27 1984-07-27 電子回路構造理解方式
JP15525884A JPS6134672A (ja) 1984-07-27 1984-07-27 回路構造認識方法
JP59166050A JPH0623988B2 (ja) 1984-08-08 1984-08-08 電子回路レイアウトの生成方法
JP59166350A JPH067387B2 (ja) 1984-08-10 1984-08-10 自動レイアウト方法
JP59166349A JPS6145329A (ja) 1984-08-10 1984-08-10 論理言語におけるデ−タトランザクシヨン方式

Publications (1)

Publication Number Publication Date
DE3580946D1 true DE3580946D1 (de) 1991-01-31

Family

ID=27566177

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585109414T Expired - Lifetime DE3580946D1 (de) 1984-07-27 1985-07-26 Verfahren und system zum verstehen und belegen von schaltungsmustern.

Country Status (3)

Country Link
US (1) US4651284A (de)
EP (1) EP0169576B1 (de)
DE (1) DE3580946D1 (de)

Families Citing this family (58)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4964060A (en) * 1985-12-04 1990-10-16 Hartsog Charles H Computer aided building plan review system and process
JPS62159278A (ja) * 1986-01-08 1987-07-15 Hitachi Ltd 自動論理設計システム
US4831543A (en) * 1986-02-21 1989-05-16 Harris Semiconductor (Patents) Inc. Hierarchical net list derivation system
JPH0785249B2 (ja) * 1986-05-16 1995-09-13 株式会社日立製作所 設計支援装置
AU7728187A (en) * 1986-09-12 1988-03-17 Digital Equipment Corporation Cad of logic circuits: rule structure for inserting new elements
US5191646A (en) * 1986-11-20 1993-03-02 Hitachi, Ltd. Display method in software development support system
JPS63137327A (ja) * 1986-11-29 1988-06-09 Toshiba Corp 意味ネツトワ−ク装置
US4849928A (en) * 1987-01-28 1989-07-18 Hauck Lane T Logic array programmer
US4949388A (en) * 1987-02-19 1990-08-14 Gtx Corporation Method and apparatus for recognition of graphic symbols
JPH0652502B2 (ja) * 1987-05-06 1994-07-06 株式会社日立製作所 推論方法
US4815003A (en) * 1987-06-19 1989-03-21 General Electric Company Structured design method for high density standard cell and macrocell layout of VLSI chips
US4852015A (en) * 1987-06-24 1989-07-25 Eta Systems, Inc. Automatic circuit layout router
JP2535976B2 (ja) * 1987-11-17 1996-09-18 株式会社日立製作所 形態接続構成自動作成システム
US4868770A (en) * 1987-12-02 1989-09-19 Analogy, Inc. Simulation results enhancement method and system
US4922432A (en) * 1988-01-13 1990-05-01 International Chip Corporation Knowledge based method and apparatus for designing integrated circuits using functional specifications
US4965758A (en) * 1988-03-01 1990-10-23 Digital Equipment Corporation Aiding the design of an operation having timing interactions by operating a computer system
US5062054A (en) * 1988-03-10 1991-10-29 Matsushita Electric Industrial Co., Ltd. Layout pattern generation and geometric processing system for LSI circuits
US5031111C1 (en) * 1988-08-08 2001-03-27 Trw Inc Automated circuit design method
US5239465A (en) * 1988-10-11 1993-08-24 Hitachi, Ltd. Method and system for layout design of integrated circuits with a data transferring flow
US4965741A (en) * 1988-10-17 1990-10-23 Ncr Corporation Method for providing an improved human user interface to a knowledge based system
JP2954223B2 (ja) * 1988-11-08 1999-09-27 富士通株式会社 半導体装置の製造方法
US5351197A (en) * 1989-04-13 1994-09-27 Cascade Design Automation Corporation Method and apparatus for designing the layout of a subcircuit in an integrated circuit
US5157668A (en) * 1989-07-05 1992-10-20 Applied Diagnostics, Inc. Method and apparatus for locating faults in electronic units
US5202841A (en) * 1989-07-14 1993-04-13 Mitsubishi Denki Kabushiki Kaisha Layout pattern verification system
JP2801931B2 (ja) * 1989-09-07 1998-09-21 松下電器産業株式会社 論理設計処理装置および回路変換ルール翻訳装置ならびに回路変換ルール翻訳方法
US5367468A (en) * 1990-02-21 1994-11-22 Kabushiki Kaisha Toshiba Design aid method and design aid apparatus for integrated circuits
US5490232A (en) * 1990-10-25 1996-02-06 Daiwa House Industry Co., Ltd. Computer-aided thought process simulation design system
US5459673A (en) * 1990-10-29 1995-10-17 Ross Technology, Inc. Method and apparatus for optimizing electronic circuits
US5299139A (en) * 1991-06-21 1994-03-29 Cadence Design Systems, Inc. Short locator method
US5471398A (en) * 1991-07-01 1995-11-28 Texas Instruments Incorporated MTOL software tool for converting an RTL behavioral model into layout information comprising bounding boxes and an associated interconnect netlist
US5293479A (en) * 1991-07-08 1994-03-08 Quintero Smith Incorporated Design tool and method for preparing parametric assemblies
US5347465A (en) * 1992-05-12 1994-09-13 International Business Machines Corporation Method of integrated circuit chips design
JPH07501906A (ja) * 1992-06-02 1995-02-23 アジレント・テクノロジーズ・インク マルチレベル相互接続技術のためのコンピュータ支援設計方法及び装置
US5493504A (en) * 1992-10-28 1996-02-20 Nippon Telegraph And Telephone Corporation System and method for processing logic function and fault diagnosis using binary tree representation
US5587918A (en) * 1992-12-28 1996-12-24 Kabushiki Kaisha Toshiba Circuit pattern comparison apparatus
US5519633A (en) * 1993-03-08 1996-05-21 International Business Machines Corporation Method and apparatus for the cross-sectional design of multi-layer printed circuit boards
US5475804A (en) * 1993-06-18 1995-12-12 Motorola, Inc. Electronics circuit graphics symbol scaling method
US5818726A (en) * 1994-04-18 1998-10-06 Cadence Design Systems, Inc. System and method for determining acceptable logic cell locations and generating a legal location structure
US5764534A (en) * 1994-10-13 1998-06-09 Xilinx, Inc. Method for providing placement information during design entry
US7068270B1 (en) * 1994-12-02 2006-06-27 Texas Instruments Incorporated Design of integrated circuit package using parametric solids modeller
JP2800881B2 (ja) * 1995-07-31 1998-09-21 日本電気株式会社 配線寄生負荷算出方法
US6321367B1 (en) * 1996-08-30 2001-11-20 Altera Corporation Apparatus and method for automatically generating circuit layouts
US5914889A (en) * 1996-09-13 1999-06-22 Lucent Technologies Inc. Method and system for generating a mask layout of an optical integrated circuit
DE19711909C2 (de) * 1997-03-21 1999-01-07 Siemens Ag Verfahren zur Bestimmung der Abarbeitungs-Reihenfolge von schaltungstechnische Komponenten simulierenden Programmodulen mit Hilfe einer Netzliste
US6577992B1 (en) 1999-05-07 2003-06-10 Nassda Corporation Transistor level circuit simulator using hierarchical data
US6405351B1 (en) 2000-06-27 2002-06-11 Texas Instruments Incorporated System for verifying leaf-cell circuit properties
US6606732B2 (en) 2000-12-11 2003-08-12 International Business Machines Corporation Method for specifying, identifying, selecting or verifying differential signal pairs on IC packages
JP2002252161A (ja) * 2001-02-23 2002-09-06 Hitachi Ltd 半導体製造システム
US7024640B2 (en) * 2001-06-29 2006-04-04 Koninklijke Philips Electronics N.V. Integrated circuit cell identification
US6978012B2 (en) * 2002-01-02 2005-12-20 Intel Corporation Echo cancellation using a variable offset comparator
US20040103375A1 (en) * 2002-11-27 2004-05-27 Rutie Chen Method and apparatus for automated schematic rendering
US20050033662A1 (en) * 2003-08-04 2005-02-10 James Buch Method for visualizing differing types of window coverings within a room setting
JP2005202928A (ja) * 2003-12-19 2005-07-28 Fujitsu Ltd レイアウト処理装置、レイアウト処理方法、及びプログラム
US20080148200A1 (en) * 2006-12-14 2008-06-19 Christian Von Mueffling Method for checking the layout of an integrated circuit
US7818710B2 (en) * 2007-07-03 2010-10-19 Micron Technology, Inc. Method and system for lithographic simulation and verification
WO2015053852A1 (en) 2013-10-07 2015-04-16 Parviz Saghizadeh Complex layout-based topological data analysis of analog netlists to extract hierarchy and functionality
US9830414B2 (en) 2014-06-16 2017-11-28 Raytheon Company Pattern matching techniques in analog and mixed signal circuits
US10192018B1 (en) * 2016-03-31 2019-01-29 Cadence Design Systems, Inc. Method and system for implementing efficient trim data representation for an electronic design

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4055802A (en) * 1976-08-12 1977-10-25 Bell Telephone Laboratories, Incorporated Electrical identification of multiply configurable circuit array
US4613940A (en) * 1982-11-09 1986-09-23 International Microelectronic Products Method and structure for use in designing and building electronic systems in integrated circuits
US4554625A (en) * 1983-06-14 1985-11-19 International Business Machines Corporation Method for generating an optimized nested arrangement of constrained rectangles

Also Published As

Publication number Publication date
EP0169576B1 (de) 1990-12-19
EP0169576A2 (de) 1986-01-29
EP0169576A3 (en) 1987-10-21
US4651284A (en) 1987-03-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee