DE3585756D1 - Halbleiterschaltungsanordnung in hauptscheibentechnik. - Google Patents

Halbleiterschaltungsanordnung in hauptscheibentechnik.

Info

Publication number
DE3585756D1
DE3585756D1 DE8585107918T DE3585756T DE3585756D1 DE 3585756 D1 DE3585756 D1 DE 3585756D1 DE 8585107918 T DE8585107918 T DE 8585107918T DE 3585756 T DE3585756 T DE 3585756T DE 3585756 D1 DE3585756 D1 DE 3585756D1
Authority
DE
Germany
Prior art keywords
circuit arrangement
semiconductor circuit
main disc
disc technology
technology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8585107918T
Other languages
English (en)
Inventor
Tomoaki C O Mr Kobayash Tanabe
Kirigaoka -Chome Fujii
Takayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP59135214A external-priority patent/JPH0680807B2/ja
Priority claimed from JP59135210A external-priority patent/JPS6122648A/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3585756D1 publication Critical patent/DE3585756D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
    • H03K17/6872—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor using complementary field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11803—Masterslice integrated circuits using field effect technology
    • H01L27/11807—CMOS gate arrays
    • H01L2027/11809—Microarchitecture
    • H01L2027/11835—Degree of specialisation for implementing specific functions
    • H01L2027/11837—Implementation of digital circuits
    • H01L2027/11838—Implementation of memory functions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
DE8585107918T 1984-07-02 1985-06-27 Halbleiterschaltungsanordnung in hauptscheibentechnik. Expired - Fee Related DE3585756D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP59135214A JPH0680807B2 (ja) 1984-07-02 1984-07-02 ゲートアレイｌｓｉ装置
JP59135210A JPS6122648A (ja) 1984-07-02 1984-07-02 マスタスライス型半導体集積回路装置

Publications (1)

Publication Number Publication Date
DE3585756D1 true DE3585756D1 (de) 1992-05-07

Family

ID=26469108

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585107918T Expired - Fee Related DE3585756D1 (de) 1984-07-02 1985-06-27 Halbleiterschaltungsanordnung in hauptscheibentechnik.

Country Status (3)

Country Link
US (1) US4780846A (de)
EP (1) EP0170052B1 (de)
DE (1) DE3585756D1 (de)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0642537B2 (ja) * 1985-11-15 1994-06-01 株式会社東芝 半導体装置
JPH0785490B2 (ja) * 1986-01-22 1995-09-13 日本電気株式会社 集積回路装置
US5367208A (en) * 1986-09-19 1994-11-22 Actel Corporation Reconfigurable programmable interconnect architecture
US5265045A (en) * 1986-10-31 1993-11-23 Hitachi, Ltd. Semiconductor integrated circuit device with built-in memory circuit group
JPH0738414B2 (ja) * 1987-01-09 1995-04-26 株式会社東芝 半導体集積回路
US4922441A (en) * 1987-01-19 1990-05-01 Ricoh Company, Ltd. Gate array device having a memory cell/interconnection region
JP2516962B2 (ja) * 1987-03-18 1996-07-24 三菱電機株式会社 マスタ−スライスｌｓｉ
JPH0815210B2 (ja) * 1987-06-04 1996-02-14 日本電気株式会社 マスタスライス方式集積回路
JPS6467940A (en) * 1987-09-08 1989-03-14 Mitsubishi Electric Corp Semiconductor integrated circuit
JP2712079B2 (ja) * 1988-02-15 1998-02-10 株式会社東芝 半導体装置
JPH01251738A (ja) * 1988-03-31 1989-10-06 Toshiba Corp スタンダードセル
US5266821A (en) * 1988-05-31 1993-11-30 Micron Technology, Inc. Chip decoupling capacitor
US5687109A (en) 1988-05-31 1997-11-11 Micron Technology, Inc. Integrated circuit module having on-chip surge capacitors
US5307309A (en) * 1988-05-31 1994-04-26 Micron Technology, Inc. Memory module having on-chip surge capacitors
US5032892A (en) * 1988-05-31 1991-07-16 Micron Technology, Inc. Depletion mode chip decoupling capacitor
US6124625A (en) * 1988-05-31 2000-09-26 Micron Technology, Inc. Chip decoupling capacitor
US4959708A (en) * 1988-08-26 1990-09-25 Delco Electronics Corporation MOS integrated circuit with vertical shield
JP2668981B2 (ja) * 1988-09-19 1997-10-27 富士通株式会社 半導体集積回路
JP2585799B2 (ja) * 1989-06-30 1997-02-26 株式会社東芝 半導体メモリ装置及びそのバーンイン方法
US5099150A (en) * 1989-09-29 1992-03-24 Sgs-Thomson Microelectronics, Inc. Circuit block for programmable logic devices, configurable as a user-writable memory or a logic circuit
US4975601A (en) * 1989-09-29 1990-12-04 Sgs-Thomson Microelectronics, Inc. User-writable random access memory logic block for programmable logic devices
US5040144A (en) * 1989-11-28 1991-08-13 Motorola, Inc. Integrated circuit with improved power supply distribution
JP2953755B2 (ja) * 1990-07-16 1999-09-27 株式会社東芝 マスタスライス方式の半導体装置
US5321280A (en) * 1990-09-13 1994-06-14 Nec Corporation Composite semiconductor integrated circuit device
JPH0562461A (ja) * 1991-04-09 1993-03-12 Mitsubishi Electric Corp 半導体記憶装置
JPH053326A (ja) * 1991-06-25 1993-01-08 Sony Corp 浮遊ゲート型不揮発性半導体記憶装置
JP3179800B2 (ja) * 1991-07-22 2001-06-25 株式会社日立製作所 半導体集積回路装置
JP2822781B2 (ja) * 1992-06-11 1998-11-11 三菱電機株式会社 マスタスライス方式半導体集積回路装置
US5898636A (en) * 1993-06-21 1999-04-27 Hitachi, Ltd. Semiconductor integrated circuit device with interleaved memory and logic blocks
US6049223A (en) 1995-03-22 2000-04-11 Altera Corporation Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US5572148A (en) * 1995-03-22 1996-11-05 Altera Corporation Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
US5570040A (en) * 1995-03-22 1996-10-29 Altera Corporation Programmable logic array integrated circuit incorporating a first-in first-out memory
US5693567A (en) * 1995-06-07 1997-12-02 Xerox Corporation Separately etching insulating layer for contacts within array and for peripheral pads
US5640107A (en) * 1995-10-24 1997-06-17 Northrop Grumman Corporation Method for in-circuit programming of a field-programmable gate array configuration memory
JP3487989B2 (ja) * 1995-10-31 2004-01-19 富士通株式会社 半導体装置
US5977791A (en) 1996-04-15 1999-11-02 Altera Corporation Embedded memory block with FIFO mode for programmable logic device
US5757208A (en) * 1996-05-01 1998-05-26 Motorola, Inc. Programmable array and method for routing power busses therein
US6005410A (en) * 1996-12-05 1999-12-21 International Business Machines Corporation Interconnect structure between heterogeneous core regions in a programmable array
US6249143B1 (en) * 1997-05-23 2001-06-19 Altera Corporation Programmable logic array integrated circuit with distributed random access memory array
US6114756A (en) 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
US6414391B1 (en) * 1998-06-30 2002-07-02 Micron Technology, Inc. Module assembly for stacked BGA packages with a common bus bar in the assembly
US6346826B1 (en) * 1998-12-23 2002-02-12 Integrated Logic Systems, Inc Programmable gate array device
JP3302665B2 (ja) * 1999-10-25 2002-07-15 ローム株式会社 半導体集積回路装置
US7283381B2 (en) 2000-08-17 2007-10-16 David Earl Butz System and methods for addressing a matrix incorporating virtual columns and addressing layers
US6462977B2 (en) 2000-08-17 2002-10-08 David Earl Butz Data storage device having virtual columns and addressing layers
JP3678212B2 (ja) * 2002-05-20 2005-08-03 ウシオ電機株式会社 超高圧水銀ランプ
US6755700B2 (en) * 2002-11-12 2004-06-29 Modevation Enterprises Inc. Reset speed control for watercraft
KR100615579B1 (ko) * 2004-09-20 2006-08-25 삼성전자주식회사 반도체 메모리 장치 및 이 장치의 파워 라인 배치 방법
KR20100003911A (ko) * 2008-07-02 2010-01-12 삼성전자주식회사 3차원 메쉬 기반 전력분배 네트워크를 갖는 멀티 칩 패키지및 이의 전력분배 방법
US9985040B2 (en) 2016-01-14 2018-05-29 Micron Technology, Inc. Integrated circuitry and 3D memory

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60953B2 (ja) * 1977-12-30 1985-01-11 富士通株式会社 半導体集積回路装置
JPS55120150A (en) * 1979-03-09 1980-09-16 Toshiba Corp Semiconductor device
JPS57124463A (en) * 1981-01-26 1982-08-03 Nec Corp Semiconductor device
JPS5835963A (ja) * 1981-08-28 1983-03-02 Fujitsu Ltd 集積回路装置
DE3380548D1 (en) * 1982-03-03 1989-10-12 Fujitsu Ltd A semiconductor memory device
JPS5919367A (ja) * 1982-07-26 1984-01-31 Toshiba Corp メモリ付ゲ−トアレイ
JPS5969948A (ja) * 1982-10-15 1984-04-20 Fujitsu Ltd マスタ−スライス型半導体集積回路
JPS609152A (ja) * 1983-06-29 1985-01-18 Fujitsu Ltd 半導体装置

Also Published As

Publication number Publication date
EP0170052B1 (de) 1992-04-01
EP0170052A2 (de) 1986-02-05
EP0170052A3 (en) 1988-12-14
US4780846A (en) 1988-10-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee