DE3673850D1 - Verfahren zum loeten von verbindungssteckerstiften an metallischen kontaktflecken. - Google Patents

Verfahren zum loeten von verbindungssteckerstiften an metallischen kontaktflecken.

Info

Publication number
DE3673850D1
DE3673850D1 DE8686104601T DE3673850T DE3673850D1 DE 3673850 D1 DE3673850 D1 DE 3673850D1 DE 8686104601 T DE8686104601 T DE 8686104601T DE 3673850 T DE3673850 T DE 3673850T DE 3673850 D1 DE3673850 D1 DE 3673850D1
Authority
DE
Germany
Prior art keywords
metal contact
connecting pins
soldering connecting
contact pegs
pegs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686104601T
Other languages
English (en)
Inventor
Robert William Churchwell
Philip Lee Flaitz
James Noel Humenik
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3673850D1 publication Critical patent/DE3673850D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/12—All metal or with adjacent metals
    • Y10T428/12493—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.]
    • Y10T428/12535—Composite; i.e., plural, adjacent, spatially distinct metal components [e.g., layers, joint, etc.] with additional, spatially distinct nonmetal component
    • Y10T428/12542—More than one such component
DE8686104601T 1985-04-11 1986-04-04 Verfahren zum loeten von verbindungssteckerstiften an metallischen kontaktflecken. Expired - Fee Related DE3673850D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/721,885 US4672739A (en) 1985-04-11 1985-04-11 Method for use in brazing an interconnect pin to a metallization pattern situated on a brittle dielectric substrate

Publications (1)

Publication Number Publication Date
DE3673850D1 true DE3673850D1 (de) 1990-10-11

Family

ID=24899716

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686104601T Expired - Fee Related DE3673850D1 (de) 1985-04-11 1986-04-04 Verfahren zum loeten von verbindungssteckerstiften an metallischen kontaktflecken.

Country Status (5)

Country Link
US (1) US4672739A (de)
EP (1) EP0198354B1 (de)
JP (1) JPS61236148A (de)
CA (1) CA1236930A (de)
DE (1) DE3673850D1 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4755631A (en) * 1985-04-11 1988-07-05 International Business Machines Corporation Apparatus for providing an electrical connection to a metallic pad situated on a brittle dielectric substrate
US4756696A (en) * 1985-12-06 1988-07-12 Amp Incorporated Solder joint inspection feature for surface mount connectors
US4970570A (en) * 1986-10-28 1990-11-13 International Business Machines Corporation Use of tapered head pin design to improve the stress distribution in the braze joint
JP2573225B2 (ja) * 1987-02-10 1997-01-22 株式会社東芝 電子部品の製造方法
DE68904214T2 (de) * 1988-03-04 1993-05-19 Toshiba Kawasaki Kk Hartloetpaste zum verbinden von metalle und keramische materialien.
JPH0632367B2 (ja) * 1989-01-24 1994-04-27 富士通株式会社 セラミック基板のｉ／ｏパッドの形成方法
JPH02304958A (ja) * 1989-05-19 1990-12-18 Hitachi Ltd 電子回路装置
JP2514910Y2 (ja) * 1990-11-28 1996-10-23 京セラ株式会社 半導体素子収納用パッケージ
US5213877A (en) * 1991-05-02 1993-05-25 Mitsubishi Materials Corporation Ceramic substrate used for fabricating electric or electronic circuit
US5483105A (en) * 1994-04-25 1996-01-09 International Business Machines Corporation Module input-output pad having stepped set-back
JP3226752B2 (ja) * 1995-04-12 2001-11-05 株式会社東芝 半導体装置の製造方法
US6555757B2 (en) * 2000-04-10 2003-04-29 Ngk Spark Plug Co., Ltd. Pin solder jointed to a resin substrate, made having a predetermined hardness and dimensions
US20060182939A1 (en) * 2005-02-11 2006-08-17 Motorola, Inc. Method and arrangement forming a solder mask on a ceramic module
JP5671237B2 (ja) * 2009-01-15 2015-02-18 日本特殊陶業株式会社 半導体素子検査用基板
TWI387420B (zh) * 2010-06-18 2013-02-21 Askey Computer Corp 切邊定位型銲接結構及防止引腳偏移的方法
US9984960B2 (en) * 2016-07-21 2018-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3770529A (en) * 1970-08-25 1973-11-06 Ibm Method of fabricating multilayer circuits
US3839727A (en) * 1973-06-25 1974-10-01 Ibm Semiconductor chip to substrate solder bond using a locally dispersed, ternary intermetallic compound
JPS5851425B2 (ja) * 1975-08-22 1983-11-16 株式会社日立製作所 ハンドウタイソウチ
US4176443A (en) * 1977-03-08 1979-12-04 Sgs-Ates Componenti Elettronici S.P.A. Method of connecting semiconductor structure to external circuits
DE2724641C2 (de) * 1977-06-01 1986-04-03 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Aufbringen von Lötungen auf Goldschichten
US4301324A (en) * 1978-02-06 1981-11-17 International Business Machines Corporation Glass-ceramic structures and sintered multilayer substrates thereof with circuit patterns of gold, silver or copper
US4418857A (en) * 1980-12-31 1983-12-06 International Business Machines Corp. High melting point process for Au:Sn:80:20 brazing alloy for chip carriers
US4434434A (en) * 1981-03-30 1984-02-28 International Business Machines Corporation Solder mound formation on substrates
JPS5892242A (ja) * 1981-11-27 1983-06-01 Mitsubishi Electric Corp セラミツク多層基板
JPS58154293A (ja) * 1982-03-10 1983-09-13 株式会社日立製作所 グリ−ンシ−トの寸法安定化法
JPS58191452A (ja) * 1982-05-06 1983-11-08 Ngk Spark Plug Co Ltd セラミツクｉｃパツケ−ジとその製法
JPS59211253A (ja) * 1983-05-17 1984-11-30 Matsushita Electronics Corp 電子部品パツケ−ジ

Also Published As

Publication number Publication date
EP0198354B1 (de) 1990-09-05
CA1236930A (en) 1988-05-17
US4672739A (en) 1987-06-16
EP0198354A3 (en) 1987-12-02
JPS61236148A (ja) 1986-10-21
EP0198354A2 (de) 1986-10-22

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee