DE3681785D1 - Verfahren zum herstellen von selbstjustierten bipolar-transistorstruksturen mit reduziertem basisbahnwiderstand. - Google Patents
Verfahren zum herstellen von selbstjustierten bipolar-transistorstruksturen mit reduziertem basisbahnwiderstand.Info
- Publication number
- DE3681785D1 DE3681785D1 DE8686116736T DE3681785T DE3681785D1 DE 3681785 D1 DE3681785 D1 DE 3681785D1 DE 8686116736 T DE8686116736 T DE 8686116736T DE 3681785 T DE3681785 T DE 3681785T DE 3681785 D1 DE3681785 D1 DE 3681785D1
- Authority
- DE
- Germany
- Prior art keywords
- emitter
- prodn
- base
- layers
- layer structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 4
- 229920005591 polysilicon Polymers 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 2
- 238000000034 method Methods 0.000 abstract 2
- 229910052710 silicon Inorganic materials 0.000 abstract 2
- 239000010703 silicon Substances 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 239000000758 substrate Substances 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- 238000001312 dry etching Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 230000000873 masking effect Effects 0.000 abstract 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE8686116736T DE3681785D1 (de) | 1985-12-17 | 1986-12-02 | Verfahren zum herstellen von selbstjustierten bipolar-transistorstruksturen mit reduziertem basisbahnwiderstand. |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE3544573 | 1985-12-17 | ||
| DE8686116736T DE3681785D1 (de) | 1985-12-17 | 1986-12-02 | Verfahren zum herstellen von selbstjustierten bipolar-transistorstruksturen mit reduziertem basisbahnwiderstand. |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE3681785D1 true DE3681785D1 (de) | 1991-11-07 |
Family
ID=6288636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE8686116736T Expired - Lifetime DE3681785D1 (de) | 1985-12-17 | 1986-12-02 | Verfahren zum herstellen von selbstjustierten bipolar-transistorstruksturen mit reduziertem basisbahnwiderstand. |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US4755476A (de) |
| EP (1) | EP0226890B1 (de) |
| JP (1) | JP2581652B2 (de) |
| KR (1) | KR950006478B1 (de) |
| AT (1) | ATE68055T1 (de) |
| DE (1) | DE3681785D1 (de) |
Families Citing this family (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR900005123B1 (ko) * | 1987-09-26 | 1990-07-19 | 삼성전자 주식회사 | 바이폴라 트랜지스터의 제조방법 |
| JP2623635B2 (ja) * | 1988-02-16 | 1997-06-25 | ソニー株式会社 | バイポーラトランジスタ及びその製造方法 |
| EP0343563A3 (de) * | 1988-05-26 | 1990-05-09 | Siemens Aktiengesellschaft | Bipolartransistorstruktur mit reduziertem Basiswiderstand und Verfahren zur Herstellung eines Basisanschlussbereiches für eine Bipolartransistorstruktur |
| EP0353509B1 (de) * | 1988-08-04 | 1995-06-14 | Siemens Aktiengesellschaft | Verfahren zur Herstellung einer integrierten Halbleiteranord- nung mit einem Photoelement und einem npn-Bipolartransistor in einem Siliziumsubstrat |
| US5015594A (en) * | 1988-10-24 | 1991-05-14 | International Business Machines Corporation | Process of making BiCMOS devices having closely spaced device regions |
| IT1225631B (it) * | 1988-11-16 | 1990-11-22 | Sgs Thomson Microelectronics | Rastremazione di fori attraverso strati dielettrici per formare contatti in dispositivi integrati. |
| EP0396802B1 (de) * | 1989-05-11 | 1997-10-22 | Siemens Aktiengesellschaft | Verfahren zur Herstellung einer integrierten Schaltungsstruktur mit einem lateralen Bipolartransistor |
| US5435888A (en) * | 1993-12-06 | 1995-07-25 | Sgs-Thomson Microelectronics, Inc. | Enhanced planarization technique for an integrated circuit |
| US6284584B1 (en) | 1993-12-17 | 2001-09-04 | Stmicroelectronics, Inc. | Method of masking for periphery salicidation of active regions |
| US5439846A (en) * | 1993-12-17 | 1995-08-08 | Sgs-Thomson Microelectronics, Inc. | Self-aligned method for forming contact with zero offset to gate |
| US6107194A (en) * | 1993-12-17 | 2000-08-22 | Stmicroelectronics, Inc. | Method of fabricating an integrated circuit |
| US5439833A (en) * | 1994-03-15 | 1995-08-08 | National Semiconductor Corp. | Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance |
| DE69626802T2 (de) * | 1995-12-28 | 2003-12-24 | Koninkl Philips Electronics Nv | Verfahren zur herstellung von einem selbstausrichtenden vertikalen bipolaren transistor auf einem soi |
| US5953596A (en) * | 1996-12-19 | 1999-09-14 | Micron Technology, Inc. | Methods of forming thin film transistors |
| US6074954A (en) | 1998-08-31 | 2000-06-13 | Applied Materials, Inc | Process for control of the shape of the etch front in the etching of polysilicon |
| US6110345A (en) * | 1998-11-24 | 2000-08-29 | Advanced Micro Devices, Inc. | Method and system for plating workpieces |
| AT4149U1 (de) | 1999-12-03 | 2001-02-26 | Austria Mikrosysteme Int | Verfahren zum herstellen von strukturen in chips |
| US6682992B2 (en) * | 2002-05-15 | 2004-01-27 | International Business Machines Corporation | Method of controlling grain size in a polysilicon layer and in semiconductor devices having polysilicon structures |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS539469A (en) * | 1976-07-15 | 1978-01-27 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device having electrode of stepped structure and its production |
| FR2508704B1 (fr) * | 1981-06-26 | 1985-06-07 | Thomson Csf | Procede de fabrication de transistors bipolaires integres de tres petites dimensions |
| DE3211752C2 (de) * | 1982-03-30 | 1985-09-26 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum selektiven Abscheiden von aus Siliziden hochschmelzender Metalle bestehenden Schichtstrukturen auf im wesentlichen aus Silizium bestehenden Substraten und deren Verwendung |
| DE3243059A1 (de) * | 1982-11-22 | 1984-05-24 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen |
| US4546536A (en) * | 1983-08-04 | 1985-10-15 | International Business Machines Corporation | Fabrication methods for high performance lateral bipolar transistors |
| DE3402188A1 (de) * | 1984-01-23 | 1985-07-25 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zum herstellen von bor-dotierten polykristallinen siliziumschichten fuer bipolartransistorschaltungen |
-
1986
- 1986-11-17 US US06/931,802 patent/US4755476A/en not_active Expired - Lifetime
- 1986-12-02 DE DE8686116736T patent/DE3681785D1/de not_active Expired - Lifetime
- 1986-12-02 EP EP86116736A patent/EP0226890B1/de not_active Expired - Lifetime
- 1986-12-02 AT AT86116736T patent/ATE68055T1/de not_active IP Right Cessation
- 1986-12-16 JP JP61301097A patent/JP2581652B2/ja not_active Expired - Lifetime
- 1986-12-17 KR KR1019860010805A patent/KR950006478B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| ATE68055T1 (de) | 1991-10-15 |
| EP0226890B1 (de) | 1991-10-02 |
| JPS62156869A (ja) | 1987-07-11 |
| EP0226890A1 (de) | 1987-07-01 |
| JP2581652B2 (ja) | 1997-02-12 |
| US4755476A (en) | 1988-07-05 |
| KR870006673A (ko) | 1987-07-13 |
| KR950006478B1 (ko) | 1995-06-15 |
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| DE3681785D1 (de) | Verfahren zum herstellen von selbstjustierten bipolar-transistorstruksturen mit reduziertem basisbahnwiderstand. | |
| ATE34050T1 (de) | Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen. | |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition |