DE3686600T2 - Verfahren zum herstellen einer harzumhuellten halbleiteranordnung. - Google Patents

Verfahren zum herstellen einer harzumhuellten halbleiteranordnung.

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Publication number
DE3686600T2
DE3686600T2 DE8686108142T DE3686600T DE3686600T2 DE 3686600 T2 DE3686600 T2 DE 3686600T2 DE 8686108142 T DE8686108142 T DE 8686108142T DE 3686600 T DE3686600 T DE 3686600T DE 3686600 T2 DE3686600 T2 DE 3686600T2
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DE
Germany
Prior art keywords
residuated
producing
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686108142T
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English (en)
Other versions
DE3686600D1 (de
Inventor
Shiro Kobayashi
Masahiko Itoh
Akira Minato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
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Publication date
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Publication of DE3686600D1 publication Critical patent/DE3686600D1/de
Publication of DE3686600T2 publication Critical patent/DE3686600T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/12Passive devices, e.g. 2 terminal devices
    • H01L2924/1204Optical Diode
    • H01L2924/12044OLED
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49121Beam lead frame or beam lead device
DE8686108142T 1985-06-14 1986-06-13 Verfahren zum herstellen einer harzumhuellten halbleiteranordnung. Expired - Fee Related DE3686600T2 (de)

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JP60128068A JPS61287155A (ja) 1985-06-14 1985-06-14 半導体装置及び半導体装置の製造方法

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US (1) US4821148A (de)
EP (1) EP0205190B1 (de)
JP (1) JPS61287155A (de)
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DE (1) DE3686600T2 (de)

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US4821148A (en) 1989-04-11
DE3686600D1 (de) 1992-10-08
EP0205190A3 (en) 1987-07-29
JPS61287155A (ja) 1986-12-17
EP0205190A2 (de) 1986-12-17
KR900007303B1 (ko) 1990-10-08
JPH045267B2 (de) 1992-01-30
KR870000752A (ko) 1987-02-20
EP0205190B1 (de) 1992-09-02

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