DE3687409D1 - Verfahren zur herstellung von schmalen, leitenden linien, von mustern und von verbindern. - Google Patents

Verfahren zur herstellung von schmalen, leitenden linien, von mustern und von verbindern.

Info

Publication number
DE3687409D1
DE3687409D1 DE8686114536T DE3687409T DE3687409D1 DE 3687409 D1 DE3687409 D1 DE 3687409D1 DE 8686114536 T DE8686114536 T DE 8686114536T DE 3687409 T DE3687409 T DE 3687409T DE 3687409 D1 DE3687409 D1 DE 3687409D1
Authority
DE
Germany
Prior art keywords
connectors
patterns
conducting lines
producing narrow
narrow
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8686114536T
Other languages
English (en)
Other versions
DE3687409T2 (de
Inventor
Ming-Fea Chow
William Lislie Guthrie
Frank B Kaufman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3687409D1 publication Critical patent/DE3687409D1/de
Application granted granted Critical
Publication of DE3687409T2 publication Critical patent/DE3687409T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
DE8686114536T 1985-10-28 1986-10-21 Verfahren zur herstellung von schmalen, leitenden linien, von mustern und von verbindern. Expired - Fee Related DE3687409T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/791,862 US4702792A (en) 1985-10-28 1985-10-28 Method of forming fine conductive lines, patterns and connectors

Publications (2)

Publication Number Publication Date
DE3687409D1 true DE3687409D1 (de) 1993-02-11
DE3687409T2 DE3687409T2 (de) 1993-07-15

Family

ID=25155008

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686114536T Expired - Fee Related DE3687409T2 (de) 1985-10-28 1986-10-21 Verfahren zur herstellung von schmalen, leitenden linien, von mustern und von verbindern.

Country Status (4)

Country Link
US (1) US4702792A (de)
EP (1) EP0224699B1 (de)
JP (1) JPH0611040B2 (de)
DE (1) DE3687409T2 (de)

Families Citing this family (86)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4867838A (en) * 1986-10-27 1989-09-19 International Business Machines Corporation Planarization through silylation
US4816112A (en) * 1986-10-27 1989-03-28 International Business Machines Corporation Planarization process through silylation
US4956313A (en) * 1987-08-17 1990-09-11 International Business Machines Corporation Via-filling and planarization technique
US4787957A (en) * 1987-09-25 1988-11-29 Air Products And Chemicals, Inc. Desmear and etchback using NF3 /O2 gas mixtures
US4910155A (en) 1988-10-28 1990-03-20 International Business Machines Corporation Wafer flood polishing
US5084071A (en) * 1989-03-07 1992-01-28 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
US4954142A (en) * 1989-03-07 1990-09-04 International Business Machines Corporation Method of chemical-mechanical polishing an electronic component substrate and polishing slurry therefor
GB2233494A (en) * 1989-06-26 1991-01-09 Philips Nv Providing an electrode on a semiconductor device
US5358902A (en) * 1989-06-26 1994-10-25 U.S. Philips Corporation Method of producing conductive pillars in semiconductor device
US5100501A (en) * 1989-06-30 1992-03-31 Texas Instruments Incorporated Process for selectively depositing a metal in vias and contacts by using a sacrificial layer
US5143820A (en) * 1989-10-31 1992-09-01 International Business Machines Corporation Method for fabricating high circuit density, self-aligned metal linens to contact windows
US5948533A (en) * 1990-02-09 1999-09-07 Ormet Corporation Vertically interconnected electronic assemblies and compositions useful therefor
US5130229A (en) * 1990-04-26 1992-07-14 International Business Machines Corporation Multi layer thin film wiring process featuring self-alignment of vias
US5219669A (en) * 1990-04-26 1993-06-15 International Business Machines Corporation Layer thin film wiring process featuring self-alignment of vias
US5081563A (en) * 1990-04-27 1992-01-14 International Business Machines Corporation Multi-layer package incorporating a recessed cavity for a semiconductor chip
US5142828A (en) * 1990-06-25 1992-09-01 Microelectronics And Computer Technology Corporation Correcting a defective metallization layer on an electronic component by polishing
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
US5514449A (en) * 1990-07-27 1996-05-07 Minnesota Mining And Manufacturing Company Multi-chip substrate
US5102718A (en) * 1990-07-27 1992-04-07 Minnesota Mining And Manufacturing Company Multi-chip substrate
US5689428A (en) * 1990-09-28 1997-11-18 Texas Instruments Incorporated Integrated circuits, transistors, data processing systems, printed wiring boards, digital computers, smart power devices, and processes of manufacture
US5137597A (en) * 1991-04-11 1992-08-11 Microelectronics And Computer Technology Corporation Fabrication of metal pillars in an electronic component using polishing
US5118385A (en) * 1991-05-28 1992-06-02 Microelectronics And Computer Technology Corporation Multilayer electrical interconnect fabrication with few process steps
JP2868167B2 (ja) * 1991-08-05 1999-03-10 インターナショナル・ビジネス・マシーンズ・コーポレイション 多重レベル高密度相互接続構造体及び高密度相互接続構造体
US5187121A (en) * 1991-12-18 1993-02-16 International Business Machines Corporation Process for fabrication of a semiconductor structure and contact stud
US5196353A (en) * 1992-01-03 1993-03-23 Micron Technology, Inc. Method for controlling a semiconductor (CMP) process by measuring a surface temperature and developing a thermal image of the wafer
US5470693A (en) * 1992-02-18 1995-11-28 International Business Machines Corporation Method of forming patterned polyimide films
US5262354A (en) * 1992-02-26 1993-11-16 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5300813A (en) * 1992-02-26 1994-04-05 International Business Machines Corporation Refractory metal capped low resistivity metal conductor lines and vias
US5287619A (en) * 1992-03-09 1994-02-22 Rogers Corporation Method of manufacture multichip module substrate
US5440805A (en) * 1992-03-09 1995-08-15 Rogers Corporation Method of manufacturing a multilayer circuit
US5422289A (en) * 1992-04-27 1995-06-06 National Semiconductor Corporation Method of manufacturing a fully planarized MOSFET and resulting structure
US5302551A (en) * 1992-05-11 1994-04-12 National Semiconductor Corporation Method for planarizing the surface of an integrated circuit over a metal interconnect layer
US5294520A (en) * 1992-08-25 1994-03-15 International Business Machines Corporation Zero undercut etch process
US5466636A (en) * 1992-09-17 1995-11-14 International Business Machines Corporation Method of forming borderless contacts using a removable mandrel
US5283208A (en) * 1992-12-04 1994-02-01 International Business Machines Corporation Method of making a submicrometer local structure using an organic mandrel
US5567550A (en) * 1993-03-25 1996-10-22 Texas Instruments Incorporated Method of making a mask for making integrated circuits
US5604158A (en) * 1993-03-31 1997-02-18 Intel Corporation Integrated tungsten/tungsten silicide plug process
US5391258A (en) * 1993-05-26 1995-02-21 Rodel, Inc. Compositions and methods for polishing
US5891352A (en) 1993-09-16 1999-04-06 Luxtron Corporation Optical techniques of measuring endpoint during the processing of material layers in an optically hostile environment
US5508144A (en) * 1993-11-19 1996-04-16 At&T Corp. Process for fabricating a device
WO1996027206A2 (en) * 1995-02-24 1996-09-06 Intel Corporation Polysilicon polish for patterning improvement
US5644188A (en) * 1995-05-08 1997-07-01 Advanced Vision Technologies, Inc. Field emission display cell structure
US5630741A (en) * 1995-05-08 1997-05-20 Advanced Vision Technologies, Inc. Fabrication process for a field emission display cell structure
US5811929A (en) * 1995-06-02 1998-09-22 Advanced Vision Technologies, Inc. Lateral-emitter field-emission device with simplified anode
US5614444A (en) * 1995-06-06 1997-03-25 Sematech, Inc. Method of using additives with silica-based slurries to enhance selectivity in metal CMP
US6547974B1 (en) * 1995-06-27 2003-04-15 International Business Machines Corporation Method of producing fine-line circuit boards using chemical polishing
US6191484B1 (en) 1995-07-28 2001-02-20 Stmicroelectronics, Inc. Method of forming planarized multilevel metallization in an integrated circuit
KR0179838B1 (ko) * 1995-09-02 1999-04-15 문정환 반도체 소자의 절연막 구조 및 절연막 평탄화 방법
US5726099A (en) * 1995-11-07 1998-03-10 International Business Machines Corporation Method of chemically mechanically polishing an electronic component using a non-selective ammonium persulfate slurry
US5738562A (en) * 1996-01-24 1998-04-14 Micron Technology, Inc. Apparatus and method for planar end-point detection during chemical-mechanical polishing
US5994241A (en) * 1996-07-31 1999-11-30 International Business Machines Corporation Method of forming conductive lines on a semiconductor wafer
US6093335A (en) * 1996-08-28 2000-07-25 International Business Machines Corporation Method of surface finishes for eliminating surface irregularities and defects
JP2820132B2 (ja) * 1996-09-09 1998-11-05 日本電気株式会社 半導体装置およびその製造方法
GB9623185D0 (en) * 1996-11-09 1997-01-08 Epigem Limited Improved micro relief element and preparation thereof
US5985762A (en) * 1997-05-19 1999-11-16 International Business Machines Corporation Method of forming a self-aligned copper diffusion barrier in vias
US5920790A (en) * 1997-08-29 1999-07-06 Motorola, Inc. Method of forming a semiconductor device having dual inlaid structure
US6143640A (en) * 1997-09-23 2000-11-07 International Business Machines Corporation Method of fabricating a stacked via in copper/polyimide beol
US6110649A (en) * 1997-11-19 2000-08-29 International Business Machines Corporation Process for manufacture of integrated circuit device
US6274421B1 (en) 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
US6133106A (en) * 1998-02-23 2000-10-17 Sharp Laboratories Of America, Inc. Fabrication of a planar MOSFET with raised source/drain by chemical mechanical polishing and nitride replacement
US6200901B1 (en) 1998-06-10 2001-03-13 Micron Technology, Inc. Polishing polymer surfaces on non-porous CMP pads
US6051496A (en) * 1998-09-17 2000-04-18 Taiwan Semiconductor Manufacturing Company Use of stop layer for chemical mechanical polishing of CU damascene
US6815336B1 (en) 1998-09-25 2004-11-09 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization of copper damascene using reverse current electroplating and chemical mechanical polishing
US6475904B2 (en) * 1998-12-03 2002-11-05 Advanced Micro Devices, Inc. Interconnect structure with silicon containing alicyclic polymers and low-k dielectric materials and method of making same with single and dual damascene techniques
US6146986A (en) * 1999-01-08 2000-11-14 Lam Research Corporation Lithographic method for creating damascene metallization layers
US6272275B1 (en) 1999-06-25 2001-08-07 Corning Incorporated Print-molding for process for planar waveguides
US6387810B2 (en) * 1999-06-28 2002-05-14 International Business Machines Corporation Method for homogenizing device parameters through photoresist planarization
US6361402B1 (en) * 1999-10-26 2002-03-26 International Business Machines Corporation Method for planarizing photoresist
JP2003513475A (ja) 1999-11-02 2003-04-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 薄膜超小型電子装置間の垂直相互接続を形成する方法及びそのような垂直相互接続を備えた製品
US6348395B1 (en) 2000-06-07 2002-02-19 International Business Machines Corporation Diamond as a polish-stop layer for chemical-mechanical planarization in a damascene process flow
JP4672238B2 (ja) * 2001-05-08 2011-04-20 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 電子装置を製造する方法
JP2002353195A (ja) * 2001-05-23 2002-12-06 Sony Corp 半導体装置の製造方法
US6489237B1 (en) 2001-12-04 2002-12-03 Taiwan Semiconductor Manufacturing Company Method of patterning lines in semiconductor devices
US6770419B2 (en) 2002-09-11 2004-08-03 International Business Machines Corporation Low silicon-outgassing resist for bilayer lithography
US9039401B2 (en) 2006-02-27 2015-05-26 Microcontinuum, Inc. Formation of pattern replicating tools
US9307648B2 (en) * 2004-01-21 2016-04-05 Microcontinuum, Inc. Roll-to-roll patterning of transparent and metallic layers
KR100661220B1 (ko) * 2004-12-29 2006-12-22 동부일렉트로닉스 주식회사 듀얼 절연막을 이용한 금속 배선 형성 방법
US7169313B2 (en) * 2005-05-13 2007-01-30 Endicott Interconnect Technologies, Inc. Plating method for circuitized substrates
US7910156B2 (en) * 2007-03-30 2011-03-22 Endicott Interconnect Technologies, Inc. Method of making circuitized substrate with selected conductors having solder thereon
KR100875167B1 (ko) * 2007-07-25 2008-12-22 주식회사 동부하이텍 반도체 소자의 금속배선과 그의 형성방법
FR2938701A1 (fr) * 2008-11-20 2010-05-21 Commissariat Energie Atomique Procede d'amincissement d'un bloc reporte sur un substrat
US8703578B2 (en) * 2012-05-29 2014-04-22 Globalfoundries Singapore Pte. Ltd. Middle in-situ doped SiGe junctions for PMOS devices on 28 nm low power/high performance technologies using a silicon oxide encapsulation, early halo and extension implantations
US9589797B2 (en) 2013-05-17 2017-03-07 Microcontinuum, Inc. Tools and methods for producing nanoantenna electronic devices
US9048410B2 (en) 2013-05-31 2015-06-02 Micron Technology, Inc. Memory devices comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls and methods of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls
TWI621634B (zh) * 2013-09-16 2018-04-21 日商住友電木股份有限公司 經胺處理之具有懸垂矽基之順丁烯二酸酐聚合物、組成物及其應用
WO2015106261A1 (en) * 2014-01-13 2015-07-16 Applied Materials, Inc. Self-aligned double patterning with spatial atomic layer deposition

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS529515B2 (de) * 1972-11-08 1977-03-16
JPS5555546A (en) * 1978-10-19 1980-04-23 Toshiba Corp Method of wiring semiconductor device
US4305779A (en) * 1980-05-28 1981-12-15 The United States Of America As Represented By The United States Department Of Energy Method of polishing nickel-base alloys and stainless steels
US4396704A (en) * 1981-04-22 1983-08-02 Bell Telephone Laboratories, Incorporated Solid state devices produced by organometallic plasma developed resists
US4450652A (en) * 1981-09-04 1984-05-29 Monsanto Company Temperature control for wafer polishing
US4599243A (en) * 1982-12-23 1986-07-08 International Business Machines Corporation Use of plasma polymerized organosilicon films in fabrication of lift-off masks
US4435247A (en) * 1983-03-10 1984-03-06 International Business Machines Corporation Method for polishing titanium carbide
US4507331A (en) * 1983-12-12 1985-03-26 International Business Machines Corporation Dry process for forming positive tone micro patterns
US4552833A (en) * 1984-05-14 1985-11-12 International Business Machines Corporation Radiation sensitive and oxygen plasma developable resist
US4599136A (en) * 1984-10-03 1986-07-08 International Business Machines Corporation Method for preparation of semiconductor structures and devices which utilize polymeric dielectric materials
US4551418A (en) * 1985-02-19 1985-11-05 International Business Machines Corporation Process for preparing negative relief images with cationic photopolymerization
US4782008A (en) * 1985-03-19 1988-11-01 International Business Machines Corporation Plasma-resistant polymeric material, preparation thereof, and use thereof
JPS61268028A (ja) * 1985-04-08 1986-11-27 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション ホトレジスト中にマスク像を現像する方法
US4944836A (en) * 1985-10-28 1990-07-31 International Business Machines Corporation Chem-mech polishing method for producing coplanar metal/insulator films on a substrate

Also Published As

Publication number Publication date
US4702792A (en) 1987-10-27
EP0224699A3 (en) 1988-08-31
EP0224699B1 (de) 1992-12-30
JPS62102545A (ja) 1987-05-13
DE3687409T2 (de) 1993-07-15
EP0224699A2 (de) 1987-06-10
JPH0611040B2 (ja) 1994-02-09

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