DE3854701D1 - Methode und Vorrichtung zum Verändern von Mikrobefehlen mit einer Makrobefehlspipeline. - Google Patents
Methode und Vorrichtung zum Verändern von Mikrobefehlen mit einer Makrobefehlspipeline.Info
- Publication number
- DE3854701D1 DE3854701D1 DE3854701T DE3854701T DE3854701D1 DE 3854701 D1 DE3854701 D1 DE 3854701D1 DE 3854701 T DE3854701 T DE 3854701T DE 3854701 T DE3854701 T DE 3854701T DE 3854701 D1 DE3854701 D1 DE 3854701D1
- Authority
- DE
- Germany
- Prior art keywords
- instruction pipeline
- macro instruction
- micro instructions
- changing micro
- changing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/3017—Runtime instruction translation, e.g. macros
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/036,726 US5005118A (en) | 1987-04-10 | 1987-04-10 | Method and apparatus for modifying micro-instructions using a macro-instruction pipeline |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3854701D1 true DE3854701D1 (de) | 1996-01-04 |
DE3854701T2 DE3854701T2 (de) | 1996-05-23 |
Family
ID=21890278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3854701T Expired - Lifetime DE3854701T2 (de) | 1987-04-10 | 1988-04-05 | Methode und Vorrichtung zum Verändern von Mikrobefehlen mit einer Makrobefehlspipeline. |
Country Status (5)
Country | Link |
---|---|
US (1) | US5005118A (de) |
EP (1) | EP0286354B1 (de) |
JP (1) | JP2848606B2 (de) |
AU (2) | AU607753B2 (de) |
DE (1) | DE3854701T2 (de) |
Families Citing this family (27)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5414426A (en) * | 1987-10-14 | 1995-05-09 | Universal Electronics Inc. | Favorite key macro command and chained macro command in a remote control |
US5255313A (en) * | 1987-12-02 | 1993-10-19 | Universal Electronics Inc. | Universal remote control system |
US6014092A (en) | 1987-10-14 | 2000-01-11 | Universal Electronics Inc. | Key mover |
US5099421A (en) * | 1988-12-30 | 1992-03-24 | International Business Machine Corporation | Variable length pipe operations sequencing |
CA2028085A1 (en) * | 1989-11-03 | 1991-05-04 | Dale J. Mayer | Paged memory controller |
US5303358A (en) * | 1990-01-26 | 1994-04-12 | Apple Computer, Inc. | Prefix instruction for modification of a subsequent instruction |
EP0498067A2 (de) * | 1991-02-08 | 1992-08-12 | International Business Machines Corporation | Mikrokodeerzeugung für eine Maschine mit skalierbarem Verbundbefehlssatz |
US5416911A (en) * | 1993-02-02 | 1995-05-16 | International Business Machines Corporation | Performance enhancement for load multiple register instruction |
US5566298A (en) * | 1994-03-01 | 1996-10-15 | Intel Corporation | Method for state recovery during assist and restart in a decoder having an alias mechanism |
US5630083A (en) * | 1994-03-01 | 1997-05-13 | Intel Corporation | Decoder for decoding multiple instructions in parallel |
US5673427A (en) * | 1994-03-01 | 1997-09-30 | Intel Corporation | Packing valid micro operations received from a parallel decoder into adjacent locations of an output queue |
US5586277A (en) * | 1994-03-01 | 1996-12-17 | Intel Corporation | Method for parallel steering of fixed length fields containing a variable length instruction from an instruction buffer to parallel decoders |
US5600806A (en) * | 1994-03-01 | 1997-02-04 | Intel Corporation | Method and apparatus for aligning an instruction boundary in variable length macroinstructions with an instruction buffer |
US5559974A (en) * | 1994-03-01 | 1996-09-24 | Intel Corporation | Decoder having independently loaded micro-alias and macro-alias registers accessible simultaneously by one micro-operation |
US5748950A (en) * | 1994-09-20 | 1998-05-05 | Intel Corporation | Method and apparatus for providing an optimized compare-and-branch instruction |
US5758116A (en) * | 1994-09-30 | 1998-05-26 | Intel Corporation | Instruction length decoder for generating output length indicia to identity boundaries between variable length instructions |
US5704052A (en) * | 1994-11-06 | 1997-12-30 | Unisys Corporation | Bit processing unit for performing complex logical operations within a single clock cycle |
US5867701A (en) * | 1995-06-12 | 1999-02-02 | Intel Corporation | System for inserting a supplemental micro-operation flow into a macroinstruction-generated micro-operation flow |
US5815724A (en) * | 1996-03-29 | 1998-09-29 | Intel Corporation | Method and apparatus for controlling power consumption in a microprocessor |
US7472259B2 (en) * | 2000-12-06 | 2008-12-30 | Analog Devices, Inc. | Multi-cycle instructions |
US7162621B2 (en) | 2001-02-21 | 2007-01-09 | Mips Technologies, Inc. | Virtual instruction expansion based on template and parameter selector information specifying sign-extension or concentration |
US7711763B2 (en) * | 2001-02-21 | 2010-05-04 | Mips Technologies, Inc. | Microprocessor instructions for performing polynomial arithmetic operations |
US7599981B2 (en) | 2001-02-21 | 2009-10-06 | Mips Technologies, Inc. | Binary polynomial multiplier |
US7181484B2 (en) * | 2001-02-21 | 2007-02-20 | Mips Technologies, Inc. | Extended-precision accumulation of multiplier output |
US7698539B1 (en) * | 2003-07-16 | 2010-04-13 | Banning John P | System and method of instruction modification |
US7937525B2 (en) * | 2004-06-25 | 2011-05-03 | Intel Corporation | Method and apparatus for decoding a virtual machine control structure identification |
US11327759B2 (en) | 2018-09-25 | 2022-05-10 | Marvell Asia Pte, Ltd. | Managing low-level instructions and core interactions in multi-core processors |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51144142A (en) * | 1975-06-06 | 1976-12-10 | Hitachi Ltd | Information processing |
US4168523A (en) * | 1975-11-07 | 1979-09-18 | Ncr Corporation | Data processor utilizing a two level microaddressing controller |
JPS53126836A (en) * | 1977-04-13 | 1978-11-06 | Hitachi Ltd | Data processor |
GB2111264B (en) * | 1978-12-06 | 1983-11-16 | Data General Corp | High speed compact digital computer system |
US4312034A (en) * | 1979-05-21 | 1982-01-19 | Motorola, Inc. | ALU and Condition code control unit for data processor |
US4376976A (en) * | 1980-07-31 | 1983-03-15 | Sperry Corporation | Overlapped macro instruction control system |
US4430708A (en) * | 1981-05-22 | 1984-02-07 | Burroughs Corporation | Digital computer for executing instructions in three time-multiplexed portions |
US4495563A (en) * | 1981-07-02 | 1985-01-22 | Texas Instruments Incorporated | Microcomputer having separate access to complete microcode words and partial microcode words |
JPS58203554A (ja) * | 1982-05-21 | 1983-11-28 | Toshiba Corp | 演算処理装置 |
DE3271123D1 (en) * | 1982-06-08 | 1986-06-19 | Ibm Deutschland | Circuits in the control part of a microprogrammable processor for direct hardware execution of selected instructions |
JPS592143A (ja) * | 1982-06-29 | 1984-01-07 | Hitachi Ltd | 情報処理装置 |
US4488224A (en) * | 1982-08-10 | 1984-12-11 | Ipl Systems, Inc. | System for controlling data flow |
EP0107952B1 (de) * | 1982-10-18 | 1988-06-01 | Nec Corporation | Informationsverarbeitungsapparat und seine Anordnung zur Befehlssteuerung |
JPS60175146A (ja) * | 1984-02-20 | 1985-09-09 | Hitachi Ltd | プログラマブル・コントロ−ラ |
US4677545A (en) * | 1984-10-12 | 1987-06-30 | American Telephone And Telegraph Company | Microprocessor having macro-rom and main program queues |
JPH0638231B2 (ja) * | 1985-04-25 | 1994-05-18 | 松下電器産業株式会社 | マイクロプログラム制御装置 |
-
1987
- 1987-04-10 US US07/036,726 patent/US5005118A/en not_active Expired - Lifetime
-
1988
- 1988-04-05 EP EP88303015A patent/EP0286354B1/de not_active Expired - Lifetime
- 1988-04-05 DE DE3854701T patent/DE3854701T2/de not_active Expired - Lifetime
- 1988-04-08 AU AU14435/88A patent/AU607753B2/en not_active Ceased
- 1988-04-08 JP JP63087082A patent/JP2848606B2/ja not_active Expired - Lifetime
-
1991
- 1991-02-20 AU AU71242/91A patent/AU638101B2/en not_active Ceased
Also Published As
Publication number | Publication date |
---|---|
EP0286354A2 (de) | 1988-10-12 |
JPS63273134A (ja) | 1988-11-10 |
AU638101B2 (en) | 1993-06-17 |
AU607753B2 (en) | 1991-03-14 |
EP0286354A3 (en) | 1990-08-29 |
JP2848606B2 (ja) | 1999-01-20 |
AU1443588A (en) | 1988-10-13 |
AU7124291A (en) | 1991-05-09 |
US5005118A (en) | 1991-04-02 |
EP0286354B1 (de) | 1995-11-22 |
DE3854701T2 (de) | 1996-05-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |