DE3855294T2 - Mikrorechner mit Speicher - Google Patents

Mikrorechner mit Speicher

Info

Publication number
DE3855294T2
DE3855294T2 DE3855294T DE3855294T DE3855294T2 DE 3855294 T2 DE3855294 T2 DE 3855294T2 DE 3855294 T DE3855294 T DE 3855294T DE 3855294 T DE3855294 T DE 3855294T DE 3855294 T2 DE3855294 T2 DE 3855294T2
Authority
DE
Germany
Prior art keywords
internal
memory
external
microcomputer
directional buffers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE3855294T
Other languages
English (en)
Other versions
DE3855294D1 (de
Inventor
Yasuo C O Patent Divisi Iijima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62280212A external-priority patent/JPH01121947A/ja
Priority claimed from JP62280210A external-priority patent/JPH01121957A/ja
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3855294D1 publication Critical patent/DE3855294D1/de
Publication of DE3855294T2 publication Critical patent/DE3855294T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/076—Error or fault detection not based on redundancy by exceeding limits by exceeding a count or rate limit, e.g. word- or bit count limit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/14—Protection against unauthorised use of memory or access to memory
    • G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
    • G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
    • G06F12/1433—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a module or a part of a module
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
DE3855294T 1987-11-05 1988-11-04 Mikrorechner mit Speicher Expired - Lifetime DE3855294T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP62280212A JPH01121947A (ja) 1987-11-05 1987-11-05 マイクロコンピュータ
JP62280210A JPH01121957A (ja) 1987-11-05 1987-11-05 マイクロコンピュータ

Publications (2)

Publication Number Publication Date
DE3855294D1 DE3855294D1 (de) 1996-06-20
DE3855294T2 true DE3855294T2 (de) 1996-10-31

Family

ID=26553680

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3855294T Expired - Lifetime DE3855294T2 (de) 1987-11-05 1988-11-04 Mikrorechner mit Speicher

Country Status (5)

Country Link
US (1) US5089951A (de)
EP (1) EP0315209B1 (de)
KR (1) KR920001283B1 (de)
DE (1) DE3855294T2 (de)
HK (1) HK1003014A1 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4885679A (en) * 1987-12-21 1989-12-05 Bull Hn Information Systems Inc. Secure commodity bus
US5418933A (en) * 1990-02-20 1995-05-23 Sharp Kabushiki Kaisha Bidirectional tri-state data bus buffer control circuit for delaying direction switching at I/O pins of semiconductor integrated circuit
US5072138A (en) * 1990-08-17 1991-12-10 Sgs-Thomson Microelectronics, Inc. Semiconductor memory with sequential clocked access codes for test mode entry
US5247621A (en) * 1990-09-26 1993-09-21 Advanced Micro Devices, Inc. System and method for processor bus use
DE69124946T2 (de) * 1990-11-30 1997-09-18 Ibm Bidirektionaler FIFO-Puffer zur Schnittstellenbildung zwischen zwei Bussen
US5276808A (en) * 1991-02-04 1994-01-04 International Business Machines Corporation Data storage buffer system and method
EP0506060B1 (de) * 1991-03-28 2000-01-05 Hughes Electronics Corporation Bidirektionaler und programmierbarer E/A-Treiber
JP2806075B2 (ja) * 1991-06-06 1998-09-30 日本電気株式会社 マイクロコンピュータ
US5440752A (en) * 1991-07-08 1995-08-08 Seiko Epson Corporation Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
US5493687A (en) * 1991-07-08 1996-02-20 Seiko Epson Corporation RISC microprocessor architecture implementing multiple typed register sets
US5539911A (en) * 1991-07-08 1996-07-23 Seiko Epson Corporation High-performance, superscalar-based computer system with out-of-order instruction execution
JP3387538B2 (ja) * 1992-02-03 2003-03-17 松下電器産業株式会社 データ転送装置，プロセサエレメント及びデータ転送方法
DE69311330T2 (de) * 1992-03-31 1997-09-25 Seiko Epson Corp Befehlsablauffolgeplanung von einem risc-superskalarprozessor
WO1993022722A1 (en) * 1992-05-01 1993-11-11 Seiko Epson Corporation A system and method for retiring instructions in a superscalar microprocessor
US5337414A (en) * 1992-09-22 1994-08-09 Unisys Corporation Mass data storage and retrieval system
US5628021A (en) * 1992-12-31 1997-05-06 Seiko Epson Corporation System and method for assigning tags to control instruction processing in a superscalar processor
JP3531166B2 (ja) * 1992-12-31 2004-05-24 セイコーエプソン株式会社 レジスタ・リネーミングのシステム及び方法
US5457802A (en) * 1993-05-17 1995-10-10 Motorola, Inc. Integrated circuit pin control apparatus and method thereof in a data processing system
JP3131675B2 (ja) * 1993-10-12 2001-02-05 三菱電機株式会社 ワンチップマイクロコンピュータ及びそのプログラムの開発，評価方法
JPH07110803A (ja) * 1993-10-13 1995-04-25 Nec Corp シングルチップマイクロコンピュータ
JPH0877035A (ja) * 1994-09-06 1996-03-22 Toshiba Corp 中央処理装置及びマイクロコンピュータ
US5764907A (en) * 1994-10-17 1998-06-09 Chrysler Corporation Computer to microcomputer interface
IT1277386B1 (it) * 1995-07-28 1997-11-10 Alcatel Italia Apparato per lo scambio di informazioni tra carte di identificazione a circuiti integrati e un dispositivo terminale
US6097218A (en) * 1996-12-20 2000-08-01 Lsi Logic Corporation Method and device for isolating noise sensitive circuitry from switching current noise on semiconductor substrate
US11139043B2 (en) * 2019-05-20 2021-10-05 Board Of Trustees Of The University Of Alabama, For And On Behalf Of The University Of Alabama In Huntsville Systems and methods for identifying counterfeit memory

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6068441A (ja) * 1983-09-22 1985-04-19 Fujitsu Ltd ワンチツプ・マイクロ・コンピユ−タ
DE3579815D1 (de) * 1984-02-09 1990-10-25 Toshiba Kawasaki Kk Terminal zur datenverarbeitung.
JPS60207957A (ja) * 1984-03-31 1985-10-19 Toshiba Corp デ−タ保護方式
US4698750A (en) * 1984-12-27 1987-10-06 Motorola, Inc. Security for integrated circuit microcomputer with EEPROM
JPS6267800A (ja) * 1985-09-20 1987-03-27 Hitachi Ltd 半導体集積回路装置
JPS62204345A (ja) * 1986-03-05 1987-09-09 Oki Electric Ind Co Ltd マイクロコンピユ−タ
JPS62251963A (ja) * 1986-04-25 1987-11-02 Casio Comput Co Ltd Ｉｃカ−ドの認証方式

Also Published As

Publication number Publication date
EP0315209A2 (de) 1989-05-10
EP0315209A3 (en) 1990-07-11
US5089951A (en) 1992-02-18
EP0315209B1 (de) 1996-05-15
KR890008702A (ko) 1989-07-12
HK1003014A1 (en) 1998-09-30
DE3855294D1 (de) 1996-06-20
KR920001283B1 (ko) 1992-02-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition