DE3882977D1 - Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem. - Google Patents

Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.

Info

Publication number
DE3882977D1
DE3882977D1 DE8888904314T DE3882977T DE3882977D1 DE 3882977 D1 DE3882977 D1 DE 3882977D1 DE 8888904314 T DE8888904314 T DE 8888904314T DE 3882977 T DE3882977 T DE 3882977T DE 3882977 D1 DE3882977 D1 DE 3882977D1
Authority
DE
Germany
Prior art keywords
arrangement
data processing
processing system
multiprocessor data
implementing multi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888904314T
Other languages
English (en)
Other versions
DE3882977T2 (de
Inventor
Richard Gillett
Douglas Williams
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of DE3882977D1 publication Critical patent/DE3882977D1/de
Application granted granted Critical
Publication of DE3882977T2 publication Critical patent/DE3882977T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4217—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with synchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
DE88904314T 1987-05-01 1988-04-25 Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem. Expired - Fee Related DE3882977T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/044,466 US4949239A (en) 1987-05-01 1987-05-01 System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
PCT/US1988/001299 WO1988008584A1 (en) 1987-05-01 1988-04-25 Method and apparatus for implementing multiple lock indicators in a multiprocessor computer system

Publications (2)

Publication Number Publication Date
DE3882977D1 true DE3882977D1 (de) 1993-09-09
DE3882977T2 DE3882977T2 (de) 1994-03-24

Family

ID=21932544

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88904314T Expired - Fee Related DE3882977T2 (de) 1987-05-01 1988-04-25 Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.

Country Status (8)

Country Link
US (1) US4949239A (de)
EP (1) EP0344216B1 (de)
JP (1) JPH0642236B2 (de)
KR (1) KR910007750B1 (de)
AU (1) AU600830B2 (de)
CA (1) CA1304828C (de)
DE (1) DE3882977T2 (de)
WO (1) WO1988008584A1 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1227711B (it) * 1988-11-18 1991-05-06 Caluso Torino Sistema multiprocessore di elaborazione dati a risorse distribuite condivise e prevenzione di stallo.
US5142676A (en) * 1988-12-28 1992-08-25 Gte Laboratories Incorporated Separate content addressable memories for storing locked segment addresses and locking processor identifications for controlling access to shared memory
US5175837A (en) * 1989-02-03 1992-12-29 Digital Equipment Corporation Synchronizing and processing of memory access operations in multiprocessor systems using a directory of lock bits
US5182809A (en) * 1989-05-31 1993-01-26 International Business Machines Corporation Dual bus microcomputer system with programmable control of lock function
JPH0387958A (ja) * 1989-06-30 1991-04-12 Nec Corp バスロツク制御方式
US5101479A (en) * 1989-07-21 1992-03-31 Clearpoint Research Corporation Bus device for generating and responding to slave response codes
US5353416A (en) * 1989-10-25 1994-10-04 Zenith Data Systems Corporation CPU lock logic for corrected operation with a posted write array
US5136714A (en) * 1989-12-04 1992-08-04 International Business Machines Corporation Method and apparatus for implementing inter-processor interrupts using shared memory storage in a multi-processor computer system
US5381536A (en) * 1989-12-29 1995-01-10 Cray Research, Inc. Method and apparatus for separate mark and wait instructions for processors having multiple memory ports
US5168570A (en) * 1989-12-29 1992-12-01 Supercomputer Systems Limited Partnership Method and apparatus for a multiple request toggling priority system
US5499356A (en) * 1989-12-29 1996-03-12 Cray Research, Inc. Method and apparatus for a multiprocessor resource lockout instruction
US5276847A (en) * 1990-02-14 1994-01-04 Intel Corporation Method for locking and unlocking a computer address
US5359715A (en) * 1991-09-16 1994-10-25 Ncr Corporation Architectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfaces
US5269005A (en) * 1991-09-17 1993-12-07 Ncr Corporation Method and apparatus for transferring data within a computer system
US5430860A (en) * 1991-09-17 1995-07-04 International Business Machines Inc. Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence
US5491799A (en) * 1992-01-02 1996-02-13 Amdahl Corporation Communication interface for uniform communication among hardware and software units of a computer system
JP3515142B2 (ja) * 1992-06-11 2004-04-05 セイコーエプソン株式会社 データ転送制御装置
GB2273586A (en) * 1992-12-21 1994-06-22 Hanover Restricting access to shared memory during updates.
US5666515A (en) * 1993-02-18 1997-09-09 Unisys Corporation Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address
US5574862A (en) * 1993-04-14 1996-11-12 Radius Inc. Multiprocessing system with distributed input/output management
JP3360933B2 (ja) * 1994-06-01 2003-01-07 富士通株式会社 情報処理システムにおける記憶制御方法および記憶制御装置
US5594875A (en) * 1994-07-01 1997-01-14 Digital Equipment Corporation Method and apparatus to provide pended transaction on a non-pended system bus
US5701422A (en) * 1995-12-13 1997-12-23 Ncr Corporation Method for ensuring cycle ordering requirements within a hierarchical bus system including split-transaction buses
US5872980A (en) * 1996-01-25 1999-02-16 International Business Machines Corporation Semaphore access control buffer and method for accelerated semaphore operations
DE69733011T2 (de) 1997-06-27 2005-09-29 Bull S.A. Schnittstellenbrücke zwischen einem Systembus und einem lokalen Bus zur Steuerung wenigstens eines Slave-Gerätes, wie ein ROM-Speicher
US6421751B1 (en) * 1998-11-23 2002-07-16 Advanced Micro Devices, Inc. Detecting a no-tags-free condition in a computer system having multiple outstanding transactions
US6611891B1 (en) 1998-11-23 2003-08-26 Advanced Micro Devices, Inc. Computer resource configuration mechanism across a multi-pipe communication link
US6397225B1 (en) * 1998-12-23 2002-05-28 Advanced Micro Devices, Inc. Messaging system with protocol independent message format
US6529983B1 (en) 1999-11-03 2003-03-04 Cisco Technology, Inc. Group and virtual locking mechanism for inter processor synchronization
US6681341B1 (en) 1999-11-03 2004-01-20 Cisco Technology, Inc. Processor isolation method for integrated multi-processor systems
US6892237B1 (en) 2000-03-28 2005-05-10 Cisco Technology, Inc. Method and apparatus for high-speed parsing of network messages
US6505269B1 (en) 2000-05-16 2003-01-07 Cisco Technology, Inc. Dynamic addressing mapping to eliminate memory resource contention in a symmetric multiprocessor system
US6922745B2 (en) * 2002-05-02 2005-07-26 Intel Corporation Method and apparatus for handling locks
JP4576323B2 (ja) * 2004-12-10 2010-11-04 富士通株式会社 データ転送装置およびデータ転送方法
US7315910B2 (en) * 2005-06-16 2008-01-01 Oracle International Corporation Techniques for handling lock-related inconsistencies
US8994533B2 (en) * 2006-11-30 2015-03-31 Patent Navigation, Inc. Conditional RFID
US8001328B2 (en) * 2008-01-29 2011-08-16 International Business Machines Corporation Method and process for expediting the return of line exclusivity to a given processor through enhanced inter-node communications
US9560134B1 (en) * 2012-06-27 2017-01-31 Netapp, Inc. Storage array side write locking
US20170111286A1 (en) * 2015-10-15 2017-04-20 Kabushiki Kaisha Toshiba Storage system that includes a plurality of routing circuits and a plurality of node modules connected thereto

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3398405A (en) * 1965-06-07 1968-08-20 Burroughs Corp Digital computer with memory lock operation
US3528061A (en) * 1968-07-05 1970-09-08 Ibm Interlock arrangement
FR2056894A1 (de) * 1969-07-31 1971-05-07 Cii
US3761883A (en) * 1972-01-20 1973-09-25 Ibm Storage protect key array for a multiprocessing system
US3997875A (en) * 1973-01-08 1976-12-14 U.S. Philips Corporation Computer configuration with claim cycles
US3916384A (en) * 1973-06-15 1975-10-28 Gte Automatic Electric Lab Inc Communication switching system computer memory control arrangement
JPS5319501B2 (de) * 1973-11-21 1978-06-21
GB1536853A (en) * 1975-05-01 1978-12-20 Plessey Co Ltd Data processing read and hold facility
US4000485A (en) * 1975-06-30 1976-12-28 Honeywell Information Systems, Inc. Data processing system providing locked operation of shared resources
US3993981A (en) * 1975-06-30 1976-11-23 Honeywell Information Systems, Inc. Apparatus for processing data transfer requests in a data processing system
US4079454A (en) * 1976-01-02 1978-03-14 Data General Corporation Data processing system using read-only-memory arrays to provide operation in a plurality of operating states
US4055851A (en) * 1976-02-13 1977-10-25 Digital Equipment Corporation Memory module with means for generating a control signal that inhibits a subsequent overlapped memory cycle during a reading operation portion of a reading memory cycle
US4099243A (en) * 1977-01-18 1978-07-04 Honeywell Information Systems Inc. Memory block protection apparatus
JPS53105139A (en) * 1977-02-24 1978-09-13 Nec Corp Dynamic main memory controller
US4115854A (en) * 1977-03-28 1978-09-19 International Business Machines Corporation Channel bus controller
US4161778A (en) * 1977-07-19 1979-07-17 Honeywell Information Systems, Inc. Synchronization control system for firmware access of high data rate transfer bus
JPS596415B2 (ja) * 1977-10-28 1984-02-10 株式会社日立製作所 多重情報処理システム
US4296466A (en) * 1978-01-23 1981-10-20 Data General Corporation Data processing system including a separate input/output processor with micro-interrupt request apparatus
US4384322A (en) * 1978-10-31 1983-05-17 Honeywell Information Systems Inc. Asynchronous multi-communication bus sequence
CA1143854A (en) * 1979-03-12 1983-03-29 Paul Binder Apparatus for interconnecting the units of a data processing system
US4315310A (en) * 1979-09-28 1982-02-09 Intel Corporation Input/output data processing system
US4313161A (en) * 1979-11-13 1982-01-26 International Business Machines Corporation Shared storage for multiple processor systems
US4481573A (en) * 1980-11-17 1984-11-06 Hitachi, Ltd. Shared virtual address translation unit for a multiprocessor system
US4407016A (en) * 1981-02-18 1983-09-27 Intel Corporation Microprocessor providing an interface between a peripheral subsystem and an object-oriented data processor
JPS58107977A (ja) * 1981-12-22 1983-06-27 Toshiba Corp 記憶装置へのアクセス方式
US4480307A (en) * 1982-01-04 1984-10-30 Intel Corporation Interface for use between a memory and components of a module switching apparatus
JPS58140862A (ja) * 1982-02-16 1983-08-20 Toshiba Corp 相互排他方式
US4490785A (en) * 1982-05-07 1984-12-25 Digital Equipment Corporation Dual path bus structure for computer interconnection
US4574350A (en) * 1982-05-19 1986-03-04 At&T Bell Laboratories Shared resource locking apparatus
US4698753A (en) * 1982-11-09 1987-10-06 Texas Instruments Incorporated Multiprocessor interface device
JPS59106021A (ja) * 1982-12-10 1984-06-19 Oki Electric Ind Co Ltd バス構成方式
US4543628A (en) * 1983-01-28 1985-09-24 Digital Equipment Corporation Bus for data processing system with fault cycle operation
US4891749A (en) * 1983-03-28 1990-01-02 International Business Machines Corporation Multiprocessor storage serialization apparatus
JPS6010384A (ja) * 1983-06-29 1985-01-19 Nec Corp デ−タ処理装置
US4587609A (en) * 1983-07-01 1986-05-06 Honeywell Information Systems Inc. Lockout operation among asynchronous accessers of a shared computer system resource
US4660169A (en) * 1983-07-05 1987-04-21 International Business Machines Corporation Access control to a shared resource in an asynchronous system
AU564271B2 (en) * 1983-09-22 1987-08-06 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in a digital computer system
US4763249A (en) * 1983-09-22 1988-08-09 Digital Equipment Corporation Bus device for use in a computer system having a synchronous bus
US4706190A (en) * 1983-09-22 1987-11-10 Digital Equipment Corporation Retry mechanism for releasing control of a communications path in digital computer system
US4626843A (en) * 1983-09-27 1986-12-02 Trw Inc. Multi-master communication bus system with parallel bus request arbitration
JPS60107170A (ja) * 1983-11-15 1985-06-12 Nec Corp マルチプロセッサ制御方式
US4604694A (en) * 1983-12-14 1986-08-05 International Business Machines Corporation Shared and exclusive access control
US4709326A (en) * 1984-06-29 1987-11-24 International Business Machines Corporation General locking/synchronization facility with canonical states and mapping of processors

Also Published As

Publication number Publication date
CA1304828C (en) 1992-07-07
JPH0642236B2 (ja) 1994-06-01
EP0344216A1 (de) 1989-12-06
EP0344216B1 (de) 1993-08-04
JPH02500783A (ja) 1990-03-15
AU600830B2 (en) 1990-08-23
KR890702145A (ko) 1989-12-23
KR910007750B1 (ko) 1991-09-30
AU1716888A (en) 1988-12-02
US4949239A (en) 1990-08-14
DE3882977T2 (de) 1994-03-24
WO1988008584A1 (en) 1988-11-03

Similar Documents

Publication Publication Date Title
DE3882977D1 (de) Verfahren und anordnung zur implementierung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.
DE3882989T2 (de) Verfahren und anordnung zur verwaltung von mehrverriegelungsanzeigen in einem multiprozessordatenverarbeitungssystem.
DE3882988D1 (de) Verfahren und anordnung zur einleitung von vorgaengen in einem multiprozessordatenverarbeitungssystem mit verwendung von mehrverriegelungsanzeigen.
DE3887886T2 (de) Verfahren und anordnung zur sicherung von angepasstem zugriff zu betriebsmitteln in einem multiprozessordatenverarbeitungssystem.
DE69320847T2 (de) Verfahren und Anordnung zur Ausführung von Prozessen in einem Multiprozessor-System
DE69032781D1 (de) System und Verfahren zur Optimierung von Cachespeicherung in einem auf Plattenspeicher basierendem Rechnersystem
DE68925653D1 (de) Verfahren und System zur Sicherungssteuerung in einem Datenverarbeitungssystem
DE3685339D1 (de) Verfahren zur optimierung des operandzugriffs und verarbeitung in einem rechnersystem.
DE3650478D1 (de) Verfahren in einem Informationsverarbeitungssystem zum Verdichten und Ersetzen von Wendungen
DE69032517D1 (de) Verfahren und System zum dynamischen Identifizieren von Datenträgern in einem Gestaltungsdateisystem
DE3788208D1 (de) Verfahren zur elektronischen Kalendererstellung zur Verwendung in einem Datenverarbeitungssystem.
DE3788212T2 (de) Verfahren zur elektronischen Kalendererstellung zur Verwendung in einem Datenverarbeitungssystem.
DE3485602D1 (de) Vorrichtung und verfahren zur zeichenanzeige in einem bitorganisierten graphiksystem.
DE3853274D1 (de) Verfahren und Vorrichtung zur Aufteilung von Datenverarbeitungsfunktionen zwischen mehreren Prozessoren.
DE69229755T2 (de) Anordnung und Verfahren zur Freigabe von geschützten Prozessen in einem verteilten Mehrprozessdatensystem
DE68924719D1 (de) Vorrichtung und Verfahren zur Ausführung eines Unterprogramms in einem Datenverarbeitungssystem mit Blockumschaltung.
DE3485907T2 (de) Verfahren und vorrichtung zur vorladung von speicherspaltenleitungen.
DE3586700D1 (de) Vorrichtung und verfahren zur datenverarbeitung.
DE69326705D1 (de) Verfahren und Anordnung zur Feststellung der Befehlsablauffolge in einem Datenverarbeitungssystem
DE3577253D1 (de) Verfahren und anordnung zur verarbeitung von empfangsdaten in einem tdma-uebertragungssystem.
DE68928314D1 (de) Verfahren und Vorrichtung zur Datenverarbeitung in einem Ubermittlungssystem für medizinische Informationen
DE68926119D1 (de) Verfahren zur anzeige oder zum speichern von beziehungsänderungen zwischen objekten in einem datenverarbeitungssystem
DE69004431D1 (de) Verfahren und Vorrichtung für Datenspeicherverbindung.
DE3788824T2 (de) Vorrichtung und Verfahren zur Seitenersetzung in einem Datenverarbeitungssystem mit virtuellem Speicher.
DE3855616D1 (de) Vorrichtung und Verfahren mit Benutzung von Lockout für Zugriffssynchronisation auf Hauptspeichersignalgruppen in einem Multiprozessordatenverarbeitungssystem

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee