DE3882990D1 - Verfahren und geraet zur simulation von m-dimensionalen verbindungsnetzwerken in einem n-dimensionalen netzwerk, worin m kleiner ist als n. - Google Patents

Verfahren und geraet zur simulation von m-dimensionalen verbindungsnetzwerken in einem n-dimensionalen netzwerk, worin m kleiner ist als n.

Info

Publication number
DE3882990D1
DE3882990D1 DE8888904811T DE3882990T DE3882990D1 DE 3882990 D1 DE3882990 D1 DE 3882990D1 DE 8888904811 T DE8888904811 T DE 8888904811T DE 3882990 T DE3882990 T DE 3882990T DE 3882990 D1 DE3882990 D1 DE 3882990D1
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DE
Germany
Prior art keywords
node
dimension
address
gray code
dimensional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8888904811T
Other languages
English (en)
Other versions
DE3882990T2 (de
Inventor
Daniel Hillis
Brewster Kahle
George Robertson
Guy Steele
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Thinking Machines Corp
Original Assignee
Thinking Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Thinking Machines Corp filed Critical Thinking Machines Corp
Application granted granted Critical
Publication of DE3882990D1 publication Critical patent/DE3882990D1/de
Publication of DE3882990T2 publication Critical patent/DE3882990T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337—Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343—Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Image Processing (AREA)
  • Small-Scale Networks (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
DE88904811T 1987-04-27 1988-04-26 Verfahren und gerät zur simulation von m-dimensionalen verbindungsnetzwerken in einem n-dimensionalen netzwerk, worin m kleiner ist als n. Expired - Lifetime DE3882990T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/042,761 US5050069A (en) 1987-04-27 1987-04-27 Method and apparatus for simulating m-dimension connection networks in and n-dimension network where m is less than n

Publications (2)

Publication Number Publication Date
DE3882990D1 true DE3882990D1 (de) 1993-09-09
DE3882990T2 DE3882990T2 (de) 1993-11-25

Family

ID=21923608

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88904811T Expired - Lifetime DE3882990T2 (de) 1987-04-27 1988-04-26 Verfahren und gerät zur simulation von m-dimensionalen verbindungsnetzwerken in einem n-dimensionalen netzwerk, worin m kleiner ist als n.

Country Status (6)

Country Link
US (1) US5050069A (de)
EP (1) EP0358704B1 (de)
JP (1) JPH02503245A (de)
AT (1) ATE92658T1 (de)
DE (1) DE3882990T2 (de)
WO (1) WO1988008566A1 (de)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5170482A (en) * 1987-08-14 1992-12-08 Regents Of The University Of Minnesota Improved hypercube topology for multiprocessor computer systems
WO1989012861A1 (en) * 1988-06-20 1989-12-28 United States Department Of Energy Interconnection networks
JPH03112324A (ja) * 1989-09-21 1991-05-13 Mitsubishi Electric Corp 分散型シミユレーシヨン装置
US5198979A (en) * 1989-09-26 1993-03-30 Shell Oil Company Seismic migration of multiprocessor computer
US5157785A (en) * 1990-05-29 1992-10-20 Wavetracer, Inc. Process cell for an n-dimensional processor array having a single input element with 2n data inputs, memory, and full function arithmetic logic unit
US5301104A (en) * 1990-08-07 1994-04-05 Honeywell Inc. Method for allocating processing elements interconnected in a hypercube topology
WO1992003792A1 (en) * 1990-08-10 1992-03-05 Syracuse University Method and apparatus for routing and partitioning a multistage interconnection network and for determining network passability
US5404296A (en) * 1991-09-25 1995-04-04 Tinking Machines Corporation Massively parallel computer arrangement for analyzing seismic data pursuant to pre-stack depth migration methodology
US5442797A (en) * 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
JP2512272B2 (ja) * 1992-01-10 1996-07-03 インターナショナル・ビジネス・マシーンズ・コーポレイション マルチプロセッサ・コンピュ―タ・システムおよびそのデ―タ割振り方法
US5659778A (en) * 1992-02-03 1997-08-19 Tm Patents, L.P. System and method of mapping an array to processing elements
US5796966A (en) * 1993-03-01 1998-08-18 Digital Equipment Corporation Method and apparatus for dynamically controlling data routes through a network
US6546451B1 (en) * 1999-09-30 2003-04-08 Silicon Graphics, Inc. Method and apparatus for decoupling processor speed from memory subsystem speed in a node controller
CN1311376C (zh) * 2001-02-24 2007-04-18 国际商业机器公司 一种计算结构和计算系统
DE10123406A1 (de) * 2001-05-15 2002-11-21 Sick Ag Verfahren zum Erfassen von zweidimensionalen Codes
US6895571B2 (en) * 2002-09-13 2005-05-17 Hewlett-Packard Development Company, L.P. Nanometer scale devices
JP4652741B2 (ja) * 2004-08-02 2011-03-16 インターナショナル・ビジネス・マシーンズ・コーポレーション 異常検出装置、異常検出方法、異常検出プログラム、及び記録媒体
WO2012146406A1 (en) 2011-04-23 2012-11-01 Deubzer Michael Method for the design evaluation of a system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4065808A (en) * 1975-01-25 1977-12-27 U.S. Philips Corporation Network computer system
US4533993A (en) * 1981-08-18 1985-08-06 National Research Development Corp. Multiple processing cell digital data processor
US4523273A (en) * 1982-12-23 1985-06-11 Purdue Research Foundation Extra stage cube
US4644496A (en) * 1983-01-11 1987-02-17 Iowa State University Research Foundation, Inc. Apparatus, methods, and systems for computer information transfer
US4727474A (en) * 1983-02-18 1988-02-23 Loral Corporation Staging memory for massively parallel processor
US4598400A (en) * 1983-05-31 1986-07-01 Thinking Machines Corporation Method and apparatus for routing message packets
US4709327A (en) * 1983-05-31 1987-11-24 Hillis W Daniel Parallel processor/memory circuit
JPS6015768A (ja) * 1983-07-08 1985-01-26 Hitachi Ltd ネツトワ−ク最適化装置
US4550397A (en) * 1983-12-16 1985-10-29 At&T Bell Laboratories Alternate paths in a self-routing packet switching network
JPS60204673A (ja) * 1984-03-29 1985-10-16 株式会社東芝 窒化ケイ素焼結体の製造方法
US5113523A (en) * 1985-05-06 1992-05-12 Ncube Corporation High performance computer system
US4739476A (en) * 1985-08-01 1988-04-19 General Electric Company Local interconnection scheme for parallel processing architectures

Also Published As

Publication number Publication date
DE3882990T2 (de) 1993-11-25
ATE92658T1 (de) 1993-08-15
EP0358704A4 (en) 1990-12-19
EP0358704A1 (de) 1990-03-21
US5050069A (en) 1991-09-17
EP0358704B1 (de) 1993-08-04
WO1988008566A1 (en) 1988-11-03
JPH02503245A (ja) 1990-10-04

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