DE3883935T2 - Halbleiterspeicheranordnung mit einem seriellen Zugriffsspeicher. - Google Patents

Halbleiterspeicheranordnung mit einem seriellen Zugriffsspeicher.

Info

Publication number
DE3883935T2
DE3883935T2 DE88403061T DE3883935T DE3883935T2 DE 3883935 T2 DE3883935 T2 DE 3883935T2 DE 88403061 T DE88403061 T DE 88403061T DE 3883935 T DE3883935 T DE 3883935T DE 3883935 T2 DE3883935 T2 DE 3883935T2
Authority
DE
Germany
Prior art keywords
serial access
arrangement
access memory
semiconductor memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE88403061T
Other languages
English (en)
Other versions
DE3883935D1 (de
Inventor
Tsutomu Sugiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu VLSI Ltd
Fujitsu Ltd
Original Assignee
Fujitsu VLSI Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu VLSI Ltd, Fujitsu Ltd filed Critical Fujitsu VLSI Ltd
Application granted granted Critical
Publication of DE3883935D1 publication Critical patent/DE3883935D1/de
Publication of DE3883935T2 publication Critical patent/DE3883935T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter
DE88403061T 1987-12-04 1988-12-02 Halbleiterspeicheranordnung mit einem seriellen Zugriffsspeicher. Expired - Fee Related DE3883935T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62307936A JPH0748301B2 (ja) 1987-12-04 1987-12-04 半導体記憶装置

Publications (2)

Publication Number Publication Date
DE3883935D1 DE3883935D1 (de) 1993-10-14
DE3883935T2 true DE3883935T2 (de) 1994-01-05

Family

ID=17974956

Family Applications (1)

Application Number Title Priority Date Filing Date
DE88403061T Expired - Fee Related DE3883935T2 (de) 1987-12-04 1988-12-02 Halbleiterspeicheranordnung mit einem seriellen Zugriffsspeicher.

Country Status (5)

Country Link
US (1) US4930108A (de)
EP (1) EP0319432B1 (de)
JP (1) JPH0748301B2 (de)
KR (1) KR930004669B1 (de)
DE (1) DE3883935T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2880547B2 (ja) * 1990-01-19 1999-04-12 三菱電機株式会社 半導体記憶装置
JPH0821233B2 (ja) * 1990-03-13 1996-03-04 株式会社東芝 画像メモリおよび画像メモリからデータを読み出す方法
JP2928654B2 (ja) * 1991-04-10 1999-08-03 株式会社東芝 マルチポートｄｒａｍ
US5206821A (en) * 1991-07-01 1993-04-27 Harris Corporation Decimation circuit employing multiple memory data shifting section and multiple arithmetic logic unit section
JPH05101646A (ja) * 1991-10-07 1993-04-23 Mitsubishi Electric Corp デユアルポートメモリ
JP2947664B2 (ja) * 1992-03-30 1999-09-13 株式会社東芝 画像専用半導体記憶装置
EP0593173B1 (de) * 1992-10-16 1998-11-11 Matsushita Electric Industrial Co., Ltd. Gerät zur Aufzeichnung von Datensignalen mittels Steuerung der Frequenzcharakteristiken der Datensignale
KR0141665B1 (ko) * 1994-03-31 1998-07-15 김광호 비디오램 및 시리얼데이타 출력방법
US6167486A (en) * 1996-11-18 2000-12-26 Nec Electronics, Inc. Parallel access virtual channel memory system with cacheable channels
US6708254B2 (en) 1999-11-10 2004-03-16 Nec Electronics America, Inc. Parallel access virtual channel memory system
US6509851B1 (en) * 2000-03-30 2003-01-21 Cypress Semiconductor Corp. Method for using a recovered data-encoded clock to convert high-frequency serial data to lower frequency parallel data
JP4857544B2 (ja) * 2004-10-29 2012-01-18 富士電機株式会社 可撓性基板の穴あけ加工方法、薄膜基板の貫通孔加工装置、および薄膜太陽電池の製造装置
US8208314B2 (en) 2010-06-01 2012-06-26 Aptina Imaging Corporation Sequential access memory elements

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6072020A (ja) * 1983-09-29 1985-04-24 Nec Corp デュアルポ−トメモリ回路
JPS60140924A (ja) * 1983-12-27 1985-07-25 Nec Corp 半導体回路
EP0179605B1 (de) * 1984-10-17 1992-08-19 Fujitsu Limited Halbleiterspeicheranordnung mit einer seriellen Dateneingangs- und Ausgangsschaltung
CA1293565C (en) * 1986-04-28 1991-12-24 Norio Ebihara Semiconductor memory
JPS62287497A (ja) * 1986-06-06 1987-12-14 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
KR930004669B1 (ko) 1993-06-02
US4930108A (en) 1990-05-29
JPH01149298A (ja) 1989-06-12
EP0319432A2 (de) 1989-06-07
EP0319432A3 (en) 1990-11-28
JPH0748301B2 (ja) 1995-05-24
DE3883935D1 (de) 1993-10-14
KR890010914A (ko) 1989-08-11
EP0319432B1 (de) 1993-09-08

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee