DE4143074A1 - TV picture redn. by reformatting of interlocked data - averaging successive pixel pairs and row averages before removing foregoing pixel or row - Google Patents

Abstract

Digitised signals representing the entire data field are fed serially into a circuit (17) which selects portions of video signal for display in a window of the outupt screen (14). The computer (10) also controls a reformatting circuit (18) whose output is buffer-stored (12, 13) as either video or graphical data. Pixels to be omitted are accumulated and averaged with the next pixel to be reproduced, yielding mean pixel value for each row. ADVANTAGE - Practically any redn. of picture size is feasible to match a chosen window of a computer output display at low hardware cost.

Description

The invention relates to computer graphics systems and in particular special to a method and a device for any Reformatting digital video images or other nested ter data for display on a computer output display advises.

According to the idea of many will be in the near future a user of a personal computer will be able to Infor retrieve from any number of sources. It will be at expected, for example, that a person would be able to and listening to radio communications, television or movie recording to see stereo music and computer graphics and use text programs. It is also expected that this Operations can be performed simultaneously so that for example, a television program on a rectangular bed the display, a window, can be made visible can while a computer graphics program in another window ster expires or computer graphics material the television program on the screen.

To watch a television program on a computer output display To display (monitor) in a window, it is very useful ßig, the full size of the television disc offered at the source plays to the desired window size in which the TV program can be displayed on the screen should. The format or reformatting of an image in Ab mood on a window poses a number of problems. These problems are very complicated when the information than television information is available. The problem is made more difficult solution in particular by combining Fern visual (video) signals with computer graphics signals within the same computer and their display on the same output monitor condition. Although both types of signals are electrical signals, The main problem with problem solving is that the two signal types because of their different tasks arrive in fundamentally different formats. The Com  puter processes digital information. The television signals are however, analog. For this reason, the television signals are ge usually first converted into digital representations so that they processed by the computer and darge on a computer monitor can be put. In addition, video signals in a (in Interlaced), nested patterns supplied, a first field (or field) of horizontal lines from Pixels from a second field of lines of 1/60 pixels is followed a second later. The lines of the two half or fields alternate, and all lines of both fields are usually used to reproduce a full picture second hand. The two fields are reproduced one after the other give. Due to the sluggishness of the mapping process by the human eye effectively finds a combination of education a full picture instead. This form of nesting The representation is typically used in television dung.

Contrary to this nested representation a computer display typically all lines of pixels in one non-nested way (single field). Because of the sub Different in the format of the television display is the usual edition display of a computer not suitable without further video to process. However, you are expected to be able the output of all these different input signals ent neither on a nested television monitor or to be able to display a computer monitor of any kind. Therefore, the interleaved video data and the non nested computer data mixed in some way and on both nested and non-nested monitors can be played optionally.

There are very expensive algorithms to use on Video data for size reduction (reduction) of the video image from the full monitor size to the size of a window can be applied. These algorithms try to ensure  len that the picture during playback due to the size reduction tion is not distorted. However, these algorithms require too high an exclusion of an inexpensive implementation Computing effort. It is therefore desirable to resize a video by applying simple algorithms to the data of a video image to be able to reduce results aim, which enables a pleasingly clear presentation and are quick and inexpensive.

An easy way to be reformatting a television picture is that every other field of the nested TV picture is completely dropped. Since the lines of Verify pixels in sequential video fields on the screen are nested, omitting alternating fields leads to a significant reduction in the number of lines, n by half. If the lines from the remaining half-balance are shown as an overall picture, so the vertical Re size the image to half its original size induced. To the size of the overall picture also in horizontal direction to adapt to the vertical size reduction must shrink, every second pixel from the lines of the rest Chen field are omitted, so only half the number rows and pixels. Since it is going away lines of alternating fields are actually slightly transmitted lapping is by simply omitting every other line vertical distortion not particularly noticeable. The distortion due to omitting every other pixel however more clearly recognizable. The fact is even more essential che that this method is only a reduction of a given one Allows grading to half in each direction. Larger Reductions can be achieved by resul reducing image to a further downsizing step and omits these lines. This means, however, that there are places in the original picture where two or more adjacent lines or two or more adjacent lines  bearded pixel columns to produce the desired image reduction tion are omitted. The resulting pictures ha However, loss of information caused by blurring, image jump extreme distortions and the unrecognizability of the Reach image content (below the eightfold reduction). The fact that the Fortlas alternating fields the image to a maximum size of limited to half in each dimension. Window between the Full and half size cannot be set.

Another way to reformat a television image is the representation of every other field and that Drop rows from one or the other as needed whose field to set the desired size reduction too can. Pixels are made up of the remaining lines at will omitted to the corresponding horizontal size reduction to reach. Since this procedure is not necessarily so begins that half of the lines of an image are omitted images in the range between full and hal ben vertical size. This is one of the Field selection method solved inherent problems. Other On the other hand, this well-known process also leads to new Pros bleme. The unsystematic omission of lines from the One or the other field means that after this Process window sizes mostly have areas in which have two or more adjacent lines from the same field originate, or in other words, alternating lines in the fen not necessarily come from alternating fields. When viewing the computer output on a non-chess telten display, this is not a problem. Viewing one However, computer output on a nested display presents then when the video window is made up of two fields whose lines do not alternate with respect to additional ones Circuits and a complicated circuit structure a ho This represents a cost factor or leads to an unreasonable distortion  degree of the resulting image. In addition, this leads known procedures below half the size in every dimension at least to the same degree of distortion as that above written field dropout procedures, however complicated In addition, the circuit, since both fields and not just one have to be processed.

It would therefore be desirable to find a middle ground between the costly and simple methods of image size reduction find, the cost effectiveness of simple methods approx However, there is an image quality and reproduction accuracy can be enough, largely the costly methods corresponds to the requirement of image recognition fulfill.

The invention is therefore based on the object of a method ren and a device for economically reducing the size of video and other nested data put that in a window of a computer output display should be reproduced. In particular, any Reduce the size of video or other nested data be made possible. This object is achieved by a A method according to claim 1 or a device according to claim 2 solved.

In the method for size reduction according to the invention the desired size of the output window is first Right. Then a sequence of output signals is generated which the pixels to be omitted in a line and the ones to be continued leaving pixel lines to achieve the appropriate reduction determine. Then the ones to be played back with the next one Pixel to be dropped and accumulated to average for to generate each line of middle pixels as an output signal for each line only sent those pixels of the sequence that are not omitted, each row of averaged pixels with the next Most row of averaged pixels averaged when the first of the times len should be dropped, and finally only those  Lines and fields are output that are not dropped that should.

As a result, the invention enables the hardware to be small practically any reduction in size reproduction to adapt to a selected window on a computer off display.

Further advantageous exemplary embodiments and further training gene of the invention are characterized in the dependent claims.

In the following the invention based on in the drawing illustrated embodiments explained in more detail. In the Show drawing:

Fig. 1 shows a size reduction of a television picture when it is displayed in a window of a computer output display slide;

Fig. 2 is a small part of those lines representing diagram, which can be displayed from a nested video image on a computer display;

Fig. 3 is a block diagram showing a general arrangement, which shows information supplied in both video and graphic form on a computer output display;

Fig. 4 is a functional block diagram of a circuit for realizing the invention;

Fig. 5 is a block diagram of a circuit for executing all stages of size reduction according to the invention;

Fig. 6 is a circuit diagram of part of the circuit shown in Fig. 4; and

Fig. 7 is a circuit diagram of another part of the TIC of FIG. 4.

The invention is based on the knowledge that a one direction for reducing the size of a television picture by one  any size in an economical manner and with maintenance desired output capabilities can be realized if the The task of size reduction is divided into two stages: a first stage to produce any size reduction tion in the range from full size to half size in any dimension; and a second stage, which is a fixed one Half size, a fixed quarter size or a fixed eighth size reduction in every dimension. Through the belie bige size reduction in the first stage, either directly or in connection with a fixed reduction quantity of the second Level can cover the entire area from full size to 1/16 in any dimension (or up to 1/256 of the area) can be achieved. The advantage of this solution is that the fixed form matation levels, which reduce each size by a factor of 2 nern, are very easy to manufacture, so that only the level be arbitrary size adjustment requires a special treatment. It has been found that the image distortion due to the Fort if pixels are greatly reduced with this method can if the omitted pixels during reformatting by averaging with the neighboring pixels in the original Filtered image back into the image. This procedure can although simply described as backward averaging, is ever but much more complicated, since a pixel only with one pixel can be averaged from the same field, one pixel in one field time-distorted to one pixel in the other half image is so that the averaged result is a temporal distortion experience and therefore unsatisfactory in most cases would be. In addition, the averaging with the immediate telbar neighboring pixels take place so the mean education is useful.

Fig. 1 shows an input video image in the left rectangle, which can be pending for display on a television screen. The same video image can be provided to the computer system to which the subject of the invention belongs to be displayed on the computer output display. The computer output display is shown in the rectangle on the right side of the figure, and the smaller rectangle in the output display represents the window in which the video image shown in the left input image is to be reproduced. It is easy to see that the size of the video image must be reduced so that it can be displayed in the window on the computer output display.

Fig. 2 shows a small part of the horizontal lines which form the two fields A and B in a normal video display or a window of such a display. The lines in the first field A are labeled A1-A10. The lines in field A are scanned for the display by the raster beam from left to right, starting with line A 1 and individually to A 10 until all lines of this field are displayed. The raster beam then returns to the upper left corner and scans field B for playback. Lines B 1- B 10 are scanned in such a way that they lie between the lines of field A. A total video image is represented by these two fields.

The overall process for performing size reduction is that first the size of the desired output window is detected; then the frame to be left out len and the pixels to be omitted within the remaining Lines are selected to achieve the appropriate reduction chen; next, the pixels to be omitted neighboring pixels of a line are collected and averaged to the Generate average pixels for each line; after that only given those pixels for output that weren't dropped should be; if a line is to be dropped, next with the next row of averaged pixels averaged; then only those lines are output that should not be dropped; and finally when  necessary to drop every other field to get the one you want To achieve size reduction.

As described above, this method is carried out in two stages. The first stage, which is called the freely selectable formatting or scaling stage, must work on both fields of the incoming image, since ignoring one field would lead to a vertical reduction of at least one half. In order to achieve a vertical reduction between the full and half size, lines with the same spacing across the overall image are omitted in order to achieve the desired vertical height dimension. Since the resulting image should have alternating lines of alternating fields in order to be able to display the result on a device with nested output, it is necessary that the same line of the other field is omitted if one line of a field is omitted. This moves all subsequent lines up two and maintains the correct order of the fields. For example, if line A 2 were omitted in the diagram of FIG. 2, line B 2 would also have to be dropped. Instead of eliminating a predetermined number of evenly spaced lines from an image, half of equally spaced line "doublets" are omitted from the image.

In the horizontal direction, the problem is much easier. There all pixels on a given line from the same field individual pixels are evenly spaced from the Er target of the desired width omitted. However, it is necessary nimble that the same pixels from all other lines too be omitted, otherwise an unacceptable distortion tion due to the horizontal shift of the pixels from a Line to the next would occur.

An important remark must be made about arbitrary scaling be made: because the smallest image size to half Restricted in every dimension needs no more than any  second line in a field or every other pixel one Line to be omitted. As mentioned earlier, the is through Elimination of data caused distortion greatly reduced when the omitted data by averaging one be neighboring pixels are filtered back into the image. Although the Operation in the following description is sometimes an averaging one pixel into another, it can also be called Averaging a predetermined number of pixels in and on then dropping the pixels used to generate the Mean pixels are understood.

If telt GEMIT a pixel denoted by C in the line A 1 with the value of the designated D next pixel in the line A 1 in the diagram according to Fig. 2, for example, the value and the original pixel C and D dropped who is the so the difference (in intensity or color) between the remaining averaged pixel and pixel E on row A 1 (on average) is smaller than the difference between pixel E and pixel D. In addition, the difference (in intensity or color ) between the new averaged pixel and pixel F to the right of pixel D on line A 1 (on average) greater than the difference between pixel D and pixel F; the change from F to the averaged pixel and to pixel E is therefore more linear and therefore cheaper. This same averaging can be used if a greater degree of reduction in the image width is desired. For example, three pixels in a row can be averaged into a single pixel and the original pixels can be omitted if the size of the image is to be reduced more.

The hardness required for omitting and averaging commodity is very expensive if the number of pixels to be averaged is a power of 2. Because the stepless reduction never again as a second pixel of a line, it is very easy to take a first pixel and with the next pixel to average on the same line in such a way that always  only two pixels are taken together for averaging can.

The same argument applies in the vertical direction as in the horizontal direction; however, in the case of arbitrary, that is to say stepless reduction, the problem becomes more complicated due to the fields which are separated twice. Because of this time shift, the pixels are directly above and below each pixel in the original image in a different field. In Fig. 2, for example, the pixels C and C 2 are in field A, while the pixel C 1 is in field B. A pixel line omitted from a field can therefore not be averaged with a pixel line from another field, since otherwise unacceptable time distortions in moving images would have to be expected and, in addition, an extremely high circuit complexity would have to be driven. Therefore, if row A 3 in Fig. 2 should be dropped, it would have to be middled with either row A 2 or A 4 . Since a row "doublet" must be omitted to maintain the correct row order, B3 must also be omitted and averaged with either row B 2 or row B 4 . Therefore, there are four possible combinations of averaging that can be carried out with the omitted "doublet": Row A 3 with row A 4 and row B 3 with row B 4 , row A 3 with row A 2 and row B 3 with row B. 2 , row A 3 with row A 4 and row B 3 with row B 2 and finally row A 3 with row A 2 and row B 3 with row B 4 . These four possibilities are represented by arrows in Fig. 2 Darge. Of these four options, the first three are actually equivalent. Since the averaging is symmetrical, averaging one line down into a second line is equivalent to averaging the second line up into the first line, the second option can be omitted from line A 2 and line B 2 and Form the averaging of these lines down lines A 3 and B 3 If the up arrow is reversed in the third possibility, the same possibility arises as in the case of the elimination of the line B 2 and the line A 3 and averaging down into the line B 3 and the line A 4 . In all three cases, two adjacent lines (one from each field) are omitted and averaged into the lines of the field assigned to them. This is a relatively inexpensive solution. Only in the fourth option is there a difference in the result. As can be seen, the fourth possibility produces an image in which the lines resulting from the averaging of omitted lines are separated by lines (B 2 and A 4 ) which have not been modified. This result turns out to be much less favorable. Since the results of the first three options are far better than the fourth option, the invention makes use of the first options mentioned.

As mentioned above, the second stage consists of fixed factor-2 reformatting. Since the distortion caused by the elimination of a field is not imperceptible, but is acceptable, these reformatter achieve a vertical size reduction by a factor of 2 simply by omitting a field of the image that they took in the first stage of any change in scale. A further reduction by a factor of 2 can be achieved by averaging all two lines in one line. This can be done reliably since all lines now come from one field. A factor of 4 can be achieved if all four lines are averaged in one line. The same procedure is used horizontally. A factor 2 reduction is achieved by averaging two pixels each; a factor of 4 can be achieved by averaging four pixels each and a reduction by factor 8 by averaging eight pixels each. By combining these horizontal and vertical size reductions, all desired fixed size expenses can be achieved.

A very general circuit arrangement for displaying video information in a window on a computer output display is shown as a block diagram in FIG. 3. The arrangement has a block 10 , generally referred to as a computer, which contains main components such as a central processing unit, a main memory, input / output circuits and other circuit components which are usually present in a general-purpose computer. An image buffer 12 and an output display 14 , which are normally regarded as components of the computer 10 , are shown separately in order to be able to describe the invention more clearly. In a special arrangement for displaying video signals on a computer output display, a second frame buffer 13 can be used for storing those video signals that are to be displayed. In such a system the output signals from the two frame buffers are combined 12 and 13 when the display 14 associated STEU erschaltung be applied to the output display 14 16th

If the video signals are stored in a separate frame buffer 13 or with the computer graphics signals in the frame buffer 12 , analog video signals, such as MTSC or PAL signals, are applied from a standard video source to an analog / digital converter 15 . The analog / digital converter 15 can be of a known design. The circuit 15 holds the video signals and uses the system clock to convert these signals into digitized color or black / white pixels, which represent the incoming video information.

The digitized signals representing the entire information field (the large rectangle on the left in FIG. 1) are transmitted in one stream to a circuit 17 which, under control of the computer 10, first selects that part of the video signals of the input video information which is in a window ( the small rectangle on the right side of Fig. 1) are to be displayed on the output display. For the purposes of the invention, the ability of the circuit 17 to select less than the entire video image is not essential; accordingly, it is assumed from this point that the entire video image is used. It is of course possible to apply the teaching of the invention to the size reduction of video images that are smaller than the full screen size.

Thereafter, the circuit 17 determines, under the control of the computer 10 for the digitized video signals, the address in the frame buffer 12 or 13 at which they should be saved so that they appear in the desired memory area on the output display.

From the circuit 17 , the video signals, again under control of the computer 10 , are passed through a reformatting circuit 18 which is designed according to the invention, and also through a circuit 19 which controls the storage of the video signals in the corresponding frame buffer 12 or 13 . If both are stored in the frame buffer 12 , the computer 10 determines for each storage location whether video or computer graphics information should be stored; Therefore, the computer 10 selectively transmits information from the computer 10 or from the circuit 17 by means of the interface circuit 18 . If the video signals are placed in the image buffer 13 , this selective transfer is carried out when the information from the image buffer 12 and 13 is written to the output display.

A functional diagram of a circuit 30 of the type according to the invention for reformatting video images is shown in FIG. 4 Darge. The circuit 30 has a control circuit 31 which determines a special operation to be carried out with each reformatting. Such an operation may include delivery of those signals which include linear dimensions of any reduction ratio in the range between half and full size to produce an overall reduction between a quarter and full size. Such an action can then further reduce the linear size of the video image in fixed steps from half of the linear dimensions to produce an overall reduction to 1/4, to 1/4 of the linear dimension to produce an overall reduction of 1/16 of 1 / 8 of the linear dimension to produce a total reduction of 1/64 or a combination of these actions. The control circuit 31 can therefore transmit the video signal to the stepless reduction circuit 32 , in which it can be reduced by a selectable amount controlled by the control circuit 31 . The reformatting circuit 32 is designed so that it can supply a video output image, which is reduced in any dimension between full and half size. The size of the reduction is arbitrary, so that any intermediate size of the image can be achieved. The reduced size generated by the circuit 32 is transmitted to one of several different circuits ver. In an alternative method, the picture generated by the circuit 32 in the redu ed size can be viewed directly when the scarf tung 32 reduction achieved for fitting the image in the window is sufficient.

The reduced size image, on the other hand, can be transferred to one of three second stage circuits. The first of these circuits 33 provides a fixed reduction by half in each dimension or an entire reduction to 1/4 of the original image area. The second circuit 34 of this stage provides a fixed reduction to 1/4 in each dimension and a total size reduction to 1/16 of the original size. The third circuit 35 of this stage provides a fixed size reduction of 1/8 in each dimension or a total reduction of 1/64 of the original size. By combining these stages in succession, an overall reduction in size from the original size to 1/256 can be achieved.

Each of the three second stage circuits 33-35 generally operates in the same manner in obtaining the fixed size reduction. Before reaching the second stage, the image size was already reduced by the continuously adjustable reformatting circuit 32 . Therefore, each of these circuits ignores every other image field when the size of the image is equal to or less than half of the original. This causes one half of the rows to drop and the vertical vertical reduction of one half required by circuit 33 . In circuit 34 , every other line of the remaining field is omitted and averaged in the remaining lines to produce the desired reduction to 1/4. In circuit 35 , all four adjacent lines of the rest of the field are averaged into one remaining line to produce the desired reduction to 1/8. In the horizontal direction the circuit 33 averages two pixels in one, the circuit 34 four pixels in one and the circuit 35 eight pixels in one.

The function of the freely selectable reformatting circuit 32 , which is designed in such a way that it allows the free selection of the size reduction of the image, cannot be carried out as easily as the reductions of the circuits which are reduced in fixed proportional steps. Since the reduction is arbitrary and creates an image area that is larger than 1/4, it is impossible to use the method of dropping every other field, since this method does not allow images that are larger than 1/4 of the total area of the Are the starting picture. In addition, all fields must be preserved in order to produce a large format image for output on a television screen. If both fields of the television signals are maintained, whoever omits a line in one field must also omit a line in the other field. The omission must take place in adjacent lines of the temporally adjacent fields so that the images of the fields are not shifted when the line is left. Therefore, the circuit is constructed so that the same lines and pixels are omitted in alternating fields and the mean values of the same lines and pixels are formed with the immediately following lines and pixels.

After discussing the functional aspects of the invention, the details of the circuit for realizing the stages of size reduction are explained below with reference to FIG. 5. In Fig. 5 is a block diagram of those particular circuit shown, in a preferred Ausführungsbei the invention play for reducing the size of a video image for display on a computer output display used. The circuit 40 has a first counter circuit 41 which receives the individual pixels which are supplied by the analog / digital converter. The counter circuit 41 also receives control signals with a first signal which becomes valid for indicating the start of a horizontal pixel line and a second signal which indicates the end of the line of signals. The counter circuit also counts the input pixels and the number of line starts and ends in a manner known per se to generate a first output signal indicating the line count for the particular field and a second output signal indicating the pixel count in each line.

The circuit 40 also has a circuit 42 which receives the control signals with the first signal indicating the beginning of a horizontal pixel line and the second signal indicating the end of the signal line and by counting these signals in a manner known per se the special field of the Video image indicating output signal generated.

The signals from the circuits 41 and 42 are transmitted as an input signals to a limiting circuit 44 . The circuit 44 receives as control input signals horizontal and vertical signals which indicate the area of each input signal field which is to be displayed. These signals are compared with the pixel count and line count provided by the counter circuit 44 to designate the horizontal image area and the vertical image area in which the image is to appear.

The limiting circuit 44 also receives signals from the control circuit 46 which indicate that even or odd fields from the picture and even or odd lines from the picture should be omitted. The control circuit 46 supplies these signals in accordance with the central processing unit of the computer system in dependence on information on the size desired for the output image. The signals determining the elimination of the even and odd field are compared with the field signals supplied by the circuit, and the result is used to control the output signals which denote the horizontal area of the picture and the vertical area of the picture, so that a special field to be omitted in these output signals are not included. In a similar manner, the signals determining the discontinuation of the even and odd lines are compared with the signals supplied by the counting circuit 41 , so that the lines to be dropped are not included in the output signals controlling the horizontal and vertical image areas.

Circuit 40 also includes horizontal and vertical skip circuits 47 and 48 . These two circuits are constructed essentially identically. The horizontal pass circuit 47 receives the signal indicating the beginning of the line and the signal indicating the end of the line, as well as two signals NDR and NDIF, which are used to determine the pixels to be transmitted in each line for the purpose of image size compression. In the preferred embodiment of the invention, the NDIF signal identifies the counter of the fraction by which the size is to be reduced. The signal NDR marks the difference between the numerator value and the denominator of this fraction. At the output of circuit 47 , two signals are generated, a first signal indicating that a particular pixel is to be omitted on a horizontal line and a second signal indicating that a particular pixel is used to calculate an average of a number of pixels on the line should be used.

The vertical forward circuit 48 operates practically in an identical manner and generates output signals which identify the pixel lines to be dropped and those pixel lines which are to be used in averaging with adjacent lines of the fields of the television picture. It should be noted that the same NDIF and NDR signals for the control of each field of a television signal are provided in such a way that the pixels and lines of the same designation are omitted and averaged during the image reformatting.

A circuit which fulfills the functions of the horizontal relay circuit 47 and the vertical relay circuit 48 , which was proposed earlier by the applicant, can provide output signals which can be used to determine the elements to be omitted from a sequence of signals in order to achieve an arbitrarily selectable reduction in the elements of the Sequence of selectable input signals that can be partially defined to achieve a reduction. Such a circuit can be used to determine specific pixels and lines for omission and averaging in order to achieve the desired selectable scale reduction.

The circuit 40 also has a further control circuit 50 , the output signals of which control the dropping and averaging of pixels and lines actually causing the circuit. The input signals of this circuit 50 on the one hand indicate the operating mode in accordance with the control circuit 46 and on the other hand serve as an activation signal. In the exemplary embodiment described here, the operating mode denotes the desired degree of size reduction, according to which it is effectively determined how many pixels are dropped in each line and averaged into neighboring pixels.

In order to omit and average the pixels in each image line for the purpose of selectable scale reduction, a programmable pixel averaging circuit 51 is provided. The programmable pixel averaging circuit 51 is shown in FIG. 6. The circuit 51 has an adder 52 which receives inputs from the pixel source (not shown in this figure) and from a memory element 54 . Element 54 and adder 52 each contain a sufficient number of stages for the particular pixel of interest. For example, if a pixel is an 8-bit color or gray scale value, both element 54 and adder 52 each contain at least 8 levels and a sufficient number of levels for the carry bits. If a 24-bit color is to be displayed, who is sharing the three individual programmable pixel averaging circuits 52 , one to transmit the 8 bits of information related to the red, green and blue color information, respectively.

The output signal of the adder 52 corresponds to the sum of the two input pixels, one from the element 54 and one from the pixel stream shifted to the right by one bit in order to obtain an average of the two pixels. Since the freely selectable reformatter does not reduce the size to less than 1/2, the averaging circuit 51 never uses more than two pixels for averaging. Therefore, a first pixel can be transferred to element 54 and returned for averaging with the next pixel stream. The output of adder 52 is transmitted as an input to a multiplexer 56 . The pixel stream forms the other input signal, which can be transmitted from the multiplexer 56 to the memory element 54 . Therefore, the multiplexer 56 selects either a pixel from the pixel stream to be transmitted to the element 54 or the averaged sum of the two neighboring pixels. Which of these two signals is transmitted depends on the averaging signal from the horizontal relay circuit 47 . The averaging signal can average a signal with the next signal as long as only every other pixel is averaged in this way. Element 54 generates either a pixel from the pixel stream or an averaged pixel as an output signal.

A pixel drop select circuit 58 is for averaging and dropping any number of pixels on each line of the image. Pixel exit select circuit 58 is constructed similarly to programmable pixel averaging circuit 51 and is shown in FIG . The selector circuit 58 receives an input signal from the pixel stream provided by the programmable pixel averaging circuit 51 . These pixels are transferred to an adder 60 , which also receives an input signal from a memory element 62 . As with programmable pixel averaging circuit 51 , both element 42 and adder 60 each have a sufficient number of stages for the particular pixel of interest. For example, if a pixel is an 8-bit color or grayscale pixel, both element 62 and adder 60 each contain at least eight stages plus a sufficient number of stages for the carry bits. If a 24-bit color is to be displayed, three individually selectable pixel forward circuits 58 are used, one of which is used to transmit the eight information bits, each relating to red, green and blue color information.

The input signal from the pixel stream supplied by the programmable pixel averaging circuit 51 and the output signal of the adder 60 are transmitted to a drum shifter 63 . The output signal of the barrel shifter 63 forms an input signal for the memory element 62 . The output signal of the storage element 62 is fed back as a white teres input signal to the element 62nd A final input to element 62 is the original pixel input from the pixel stream. The selection of the input signals takes place with the aid of a multiplexer 64 which is controlled in accordance with the size reduction to be carried out by accumulator signals supplied by the circuit 50 .

The pixel lapse selection circuit 58 can perform four different operations. If the pixel (be it a simple pixel or averaged using programmable pixel averaging circuit 51 ) is to be passed without any action, multiplexer 64 simply transmits the pixel signal from the input to element 62 . In this case, the circuit 50 does not deliver a shift signal to the drum shifter 63 , so that the pixel passes through unchanged. If pixels are to be collected so that they can be further averaged, the first input pixel to be averaged is transmitted to element 62 , after which the value of the pixel stored in element 62 is transmitted back to the input of adder 60 , where it corresponds to the value of next input pixel is summed. This value is transmitted from multiplexer 64 to element 62 . The process continues until the desired number of pixels in element 62 has been totalized.

When a desired number of pixels have been accumulated, the final addition of the adder 60 shifts the results from the drum shifter 63 to perform the division operation averaging the accumulated pixel values. For example, if eight pixels are to be averaged, the total accumulated value can be shifted three positions to drop the three least significant bits and divide by eight. The output signal from the drum shifter 63 is transmitted to the memory element 62 through the multiplexer 64 and used as the desired average pixel value.

Special pixels can also be skipped during the totalization for various reasons. This happens because the multiplexer 64 for coupling the signal of element 62 directly to element 62 is caused during the time in which the pixel to be dropped is present at the input of multiplexer 64 .

It can therefore be seen that the pixels in each line can first be processed by the programmable pixel averaging circuit 51 to produce a selectable output in which more than half of the signals are averaged. These signals are then transmitted to a selection circuit 58 where they are further averaged to produce the linear order formatting by the set amounts of 1/2, 1/4 or 1/8.

Although the pixel signals are averaged by the programmable pixel averaging circuit 51 and the selection circuit 58 , the pass pixel signals from the horizontal pass circuit 47 and the control circuit 50 are applied to an output validity circuit 68 . These signals and the signals indicative of the valid range for the television picture control circuit 68 such that their outputs indicate the particular pixels which are valid on each line of each field. The signals that are not to be included in the image are designated by the pixel non-signals and are not included in the valid pixel signals. When the valid pixel signals match the pixel stream generated by the programmable pixel averaging circuit 51 and the selection circuit 58 , the corresponding pixels are selected to produce the size reduction specified by the processor. The pixel stream in each line is applied from the selection circuit 58 to a line averaging circuit 70 . The circuit 70 has a configuration which is substantially the same as that of the programmable pixel averaging circuit 51 and is therefore able to omit and average or pass pixels. The pixels averaged in this circuit are those which are provided by the selection circuit 58 and those pixels from the immediately preceding line which have already passed through the circuit 70 and are buffered in a line buffer 72 . The pixels of a first line which is to be dropped can be passed by circuit 70 to line buffer 72 and averaged with the neighboring pixels of the next line. When the programmable pixel averaging circuit 51 is controlled by an averaging signal, the output signal of the circuit 70 is controlled by a row averaging signal provided by the vertical pass circuit 48 . This row averaging signal, shifted by one clock cycle, follows the skip signals generated by circuit 48 . Circuit 48 also sends the line-off signal to output validation circuit 68 to cause those lines which are not to be omitted to remain in field output. If the last pixel output of the row averaging circuit is combined with the pixel valid output signal of the circuit 68 , then both the number of pixels in a row would be reduced to the desired number, and the omitted pixels would be averaged into the adjacent subsequent pixels, and the number the lines of the pixels would be reduced to the desired number of lines, the pixels of the omitted lines having been averaged into the pixels of the next lines.

As can be seen from the above description, all desired results can be generated by circuit 40 in FIG . If, for example, the size of a television picture is to be reduced by half or less in linear dimensions, the degree of reduction is determined by the signals NDIF and NDR, which determine the size of the freely and continuously selectable reduction. For example, if the image is to be reduced to 2/3 of its original size in both linear directions, a value representing numerator 2 and a value for NDR representing the difference of 1 between the numerator and the denominator are provided . Neither a line drop-off nor an image drop-out signal is generated. Accordingly, the horizontal pass circuit 47 produces an output signal which causes a pass of three pixels and an average of the last of these pixels into the next pixel. This sequence is continued in this order through the line and after the following lines. At some point, the output validation circuit 68 indicates that every third pixel of a line is to be averaged. This will reduce the line size. As each line passes through line averaging circuit 70 , it is treated in the same manner. Three lines are passed through without change. Thereafter, the third row is averaged into the following row under the control of the row averaging signal from the vertical pass circuit 48 . At the same time, output validation circuit 68 denotes omitting every third line. Therefore, a first line of reduced pixels and a second line of reduced pixels are passed, the third line is omitted, and a fourth line of reduced pixels generated by averaging the pixels of the third and fourth lines is again passed. In this way the line size is reduced.

In order to additionally generate reduction levels, the field dropout and line dropout signals are selectively activated so that an entire field of lines and half of the lines still present in a remaining special field are omitted. Since these two functions only concern the omission of lines, the selection circuit 58 is used to reduce the number of pixels in each line for the appropriate number. If the size of the horizontal dimension is to be reduced to 1/8 of the original size, the programmable pixel averaging circuit 51 is first used to reduce the number of pixels to 1/2 by averaging every other pixel in its next pixel, the ones to be omitted Run through pixels without averaging. This pixel stream is passed through selection circuit 58 where the first (to be omitted) pixel is transmitted to element 62 . The second averaged pixel is then inserted into element 62 to replace the first. The third pixel (to be omitted) is ignored by causing multiplexer 64 to pass the averaged pixel back to element 62 . The second averaged pixel is then added to the fourth averaged pixel and placed in element 62 . The fifth pixel is ignored, the averaged sixth pixel is added to the total in element 62 , the seventh pixel is ignored, the averaged eighth pixel is added to the total in element 62 , and shifted four places in the drum shifter 63 to produce a pixel that averages which represents eight pixels. Since each of these pixels is transmitted to the output by the row averaging circuit 70 for each row to be generated at the output, only the averaged eighth pixel is marked as valid for the output by the output validation circuit 68 .

Through various combinations of the control signals different pixel numbers and lines are omitted to he arbitrarily selectable size reduction according to the invention testify.

Claims (18)

1. A method for reducing the size of a television picture, characterized in that
that the desired size of the output window is first determined,
that a sequence of output signals is generated which define the pixels to be omitted in one line and the lines of pixels to be omitted in order to achieve the correct reduction;
that the pixels to be omitted are collected and averaged with the next pixel to be displayed in order to produce averaged pixels for each line;
that only those pixels in the sequence which are not omitted are transmitted to the output for each line;
that each row of averaged pixels is averaged with the next row of averaged pixels if the first of the rows is to be dropped; and
that only the lines that have not been dropped and the fields (fields) that have not been dropped are made available at the exit. 2. Device for reducing the area of a display or an image reproduction of digital signals for a computer or other display output system, characterized by
Means ( 31 ) for selecting the desired area reduction;
Means ( 32 ) for continuously variable size reduction of the display within a range up to half in each linear dimension; and
Means ( 32 , 35 ) for further reducing the linear size of the display in fixed steps by half of the linear dimensions. 3. Device according to claim 2, characterized in that the means ( 32 ) for continuously variable size reduction of the display up to half of each linear dimension means ( 47 , 51 ) for selecting the pixels to be averaged, means ( 51 ) for using the mean values when generating new pixels for the display and means ( 58 ) for omitting pixels used to achieve the mean values from the display. 4. Device according to claim 3, characterized in that the means ( 47 , 51 ) for selecting the pixels to be averaged together have a circuit for calculating the pixels to be omitted for achieving the selected size reduction. 5. Device according to claim 3 or 4, characterized net that the means for selecting the to be averaged together Pixels are designed so that they are the pixels to be averaged in both the horizontal and vertical directions can choose. 6. Device according to one of claims 2 to 5, characterized in that the means for infinitely selectable reduce the display size by up to half of each of its line ardimensions a circuit for selecting adjacent horizontal tal lines in a special partial image, a circuit ( 48 , 70 ) for averaging the pixels in these adjacent lines for generating new pixels and a circuit for omitting the pixels averaged for generating new pixels. 7. Device according to one of claims 2 to 6, characterized in that the means for continuously selectable Reduie ren the display size up to half of each linear dimension a circuit ( 47 , 51 ) for selecting adjacent pixels in each horizontal line, a circuit for averaging ( 51 ) of the neighboring pixels for the generation of new pixels and a circuit for omitting ( 58 ) the pixels averaged for the generation of new pixels. 8. Device according to claim 7, characterized in that the means for continuously variable reduction of the display size up to half in each linear dimension are designed that they have pixels in adjacent positions and horizontal time influence the fields to be displayed. 9. Device according to one of claims 2 to 8, characterized characterized in that the means to further reduce the li near size of the display in fixed steps to each Half of the linear dimensions a circuit to omit partial or field from a nested image exhibit (interlaced). 10. Device according to one of claims 2 to 9, characterized characterized in that the means to further reduce the li near size of the display in fixed steps of each Half of the linear dimensions a circuit for averaging each because two adjacent horizontal lines into one Have row of averaged pixels. 11. Device according to one of claims 2 to 10, characterized characterized in that the means to further reduce the li near size of the display in fixed steps of each Half of the linear dimensions a circuit for averaging each two adjacent pixels to horizontal lines to egg have a single mean pixel. 12. Device according to one of claims 2 to 11, characterized characterized in that the means to further reduce the li near size of the display in fixed steps around the Half of the linear dimensions a circuit for averaging  of four adjacent horizontal lines to one umpte row with averaged pixels. 13. Device according to one of claims 2 to 12, characterized characterized in that the means for further reducing the li near size of the display in fixed steps to each Half of the linear dimensions a circuit for averaging of four each adjacent in a horizontal line Have pixels to a single mean pixel. 14. Device according to one of claims 2 to 13, characterized characterized in that the means for further reducing the li near size of the display in fixed steps of each Half of the linear dimensions a circuit for averaging of eight neighboring horizontal lines to one line of averaged pixels. 15. Device according to one of claims 2 to 14, characterized characterized in that the means for further reducing the li near size of the display in fixed steps of each Half of the linear dimensions a circuit for averaging to each eight adjacent pixels on horizontal lines have a single mean pixel. 16. Method of reducing the size of an image for Fitting into a display on a computer output display lendes output window, characterized in that the size of the desired output window determines the ones to be omitted Lines of the image and those of the remaining image lines pixels to be omitted are selected, neighboring pixels to be omitted send pixels are averaged to get mean value pixels for generating lines of image, neighboring pixels to be omitted lines are averaged to generate averaged pixel lines,  and output from obtained pixel rows and averaged Pixels is developed. 17. Method of reducing an image size for fitting into an output window of a computer output display, the Image from two interlaced half-frames is constructed, characterized in that the size of the desired output window is determined that at least one Line from a first of the nested fields and one Line from a second of the nested fields as lines to be omitted are selected such that the lines from the first and second fields in the picture others are adjacent that from the remaining image afterwards lines to be omitted pixels that are adjacent pixels to be omitted are averaged to average pixels for maintained image lines to produce that one to read away send line in each nested field with at least an adjacent pixel line in the same field to generate distribution of adjacent mean lines of pixels in each of the ver boxed fields is averaged that each of the Er generation of an average pixel used pixels omitted is that each of the to generate an average row of Lines used pixels is omitted and that for each of the interlaced fields did not read out an edition pixel lines is developed. 18. The method according to claim 16 or 17, characterized indicates that the size of the line output by a fixed factor gate is reduced by 2.