DE4241465A1 - - Google Patents

Abstract

While recording and reproducing in a digital VTR, sync-block unit data is separated into an independent decodable code (IDC) and a dependent decodable code (DDC) to which respective inner parities are added and then recorded, and the independent decodable code (IDC) only is error-corrected during variable tape-speed reproduction. The DC code contains the minimum information required to faithfully reproduce the original image whilst the DDC code contains the remaining information required to add detail to the image and during high-speed reproduction the DC code only is used to form the image. An embodiment of the error-correcting encoding apparatus is shown in fig. 2. <IMAGE>

Description

The present invention relates to an error correction method and an associated device of a digital video tape recorder (VTR), and in particular an error correction method and one too proper device in a digital VTR, in which image data a synchronization block recorded and / or how be given in an independently decodable code be split up, almost all the required image information contains, and in a dependent decodable code which the contains other image information.

A digital VTR records and / or outputs image information again after it has been converted into a digital signal, and this has advantages over a conventional, analog one  magnetic recording / reproducing device, namely at for example, an improved signal / noise ratio, an increase te resolution, easy editing, etc. Such a digi taler VTR converts an analog signal from a single image into a digital signal, and stores the converted signal in egg frame memory. The stored in the frame memory th data is divided into unit blocks, and then by egg ne discrete cosine transformation (hereinafter referred to as "DCT" net) and a Huffman coding with variable length. Each an error correction code (in parity) and then the block is in another Reorganize single image memory according to its original position siert. A block with external parity, the other error rate rectification code (outer parity), each unit block in the vertical direction of the reorganized frame memory added. The unit block and the block with external parity are by a synchronization signal and a block address whole, and then sequentially recorded on tracks of a tape. During playback, the unit block and the block become with reproduced external parity from a recording signal which is generated by a head scanning the tracks, and the repro reduced unit blocks or blocks with external parity in the frame memory corresponding to each block address draws. An error correction is then carried out by the outside and inner parity, inverse Huffman variable coding, and an inverse DCT with respect to the unit blocks contained in the one frame memory are recorded. The signal which the invert subjected to DCT is converted into an analog signal delt, so that the analog signal is reproduced, which the Original image represents.

The unit block is transformed into an energy function by the DCT  converted, which DC voltage and AC voltage coefficient has clients. Characteristic of the DCT is the fact that almost all the energy of a signal in the low frequency th section converges. With Huffman coding with variab length of the coefficients of the frequency function with vari encoded length. To play a tape with variable Ge speed, the recording must be done in this way that the bit amount of each unit block is constant. If each block is compressed so that it has a constant amount of bits has, so simple and complicated sections of the Original image compressed with the same amount of bits, so that the Re producibility of the complex section during playback ver is deteriorated compared to that of the simple section. In order to ensure a uniform overall reproducibility in the image during normal playback, the rela tive complexity of a frame is calculated, and the amount of bits each unit block set accordingly. This means that fewer bits are assigned to the simple sections, and more bits are assigned to complex sections.

The U.S. patent application filed by this applicant (which claimed priority from Korean Patent No. 92-4227) describes a method in which the recording thereby is carried out that the unit block in an independent de encodable code (hereinafter simply referred to as "IDC") under is shared, which contains almost all the information needed for Reproduction of the original image is required and in one dependent decodable code (hereinafter simply referred to as "DDC" records), which contains the remaining information. With this procedure The original image is reproduced using both from IDC as well as from DDC during normal playback, and from IDC only during playback with variable tape speed,  which makes playback at variable tape speed easy and becomes easy. Despite the appearance of mismatched synchronis station blocks due to the passage of the heads over several spu during tape playback at variable speed reproducing an image that is almost the same as that Original image, provided that the IDC is established that represents a portion of the unit block. Hence who preferably the IDC and the DDC in different ways the error correction encoding recorded the playback rate to increase the recorded data during playback.

An advantage of the present invention is the provision an error correction coding method which is used for the recording method of unit blocks is suitable, which in a un dependent decodable code and a dependent decodable Code are divided.

Another advantage of the present invention is that Providing an error correction decoding method which facilitate tape playback at variable speed can.

Another advantage of the present invention is that To provide a device for error correction Coding method is suitable.

Another advantage of the present invention is that To provide a device for error correction Decoding method is suitable.

To achieve the foregoing advantages of the present Er an error correction coding method is available the step of adding the first and second  internal parities for a respective block identification sig nal, to IDC and DDC within a unit block.

To achieve a further advantage of the present invention, an error correction decoding method is provided with the following steps:
Decoding the block identification signal, the IDC and the DDC by the first and second inner parity during normal playback; and
Decoding only the block identification signal and the IDC by the first inner parity during variable speed tape playback.

To achieve a further advantage of the present invention, an error correction coding device is provided with the following parts:
a demultiplexer for inputting the unit block to which the block identification signal is supplied and for separating the input into the block identification signal, the independently decodable code, and the dependent decodable code so as to output them;
a first inner parity encoder for adding a first inner parity to the block identification signal and the independently decodable code from the demultiplexer;
a second inner parity encoder for adding a second inner parity to the dependent decodable code from the demultiplexer; and
a multiplexer for inputting the block identification signal and the independently decodable code, to which the first inner parity is added in the first inner parity encoder, and for inputting the dependent decodable code, which has the second inner parity in the second inner parity encoder Parity is added, and to output the result of their combination.

To achieve a further advantage of the present invention, an error correction decoding device is provided with the following parts:
a demultiplexer for inputting the unit block, and separating the unit block into a first group consisting of the block identification signal, the independently decodable code and the first inner parity, and a second group consisting of the dependent decodable code and the second inner There is parity to spend it like this;
a first inner parity decoder for decoding the block identification signal and the independently decodable code by the first inner parity of the first group from the demultiplexer;
a second inner parity decoder for decoding the dependent decodable code by the second inner parity of the second group from the demultiplexer;
a multiplexer for receiving the block identification signal and the independently decodable code from the first inner parity decoder and the dependent decodable code from the second inner parity decoder and outputting the result of their combination;
a buffer for receiving the block identification signal and the independently decodable code from the first inner parity decoder; and
a selector for selectively outputting either the output signal of the multiplexer or the output signal of the buffer.

In a digital VTR, the error correction procedure and the associated device according to the present invention Recording through that first and second parities one the respective IDC, which is almost all required data, and to a DDC that the rest gene data in the single unit block, whereby the Data sustainability is improved.

Due to the error correction only of the IDC, which during the re variable belt speed is to be used, also minimizes error correction coding and Decoding device according to the present invention ver effective data due to Synchro's error adjustment nization blocks, which result from crossing the heads of multiple tracks during variable band playback speed occurs, and introduces error correction on fold out way.

The invention is illustrated below with reference to drawings ter exemplary embodiments explained in more detail, from which white more advantages and. Characteristics. It shows:

Fig. 1 is a block diagram showing the construction of a recording system in a digital VTR;

Fig. 2 is a block diagram showing the detailed structure of an error correction encoder according to the present invention;

Fig. 3 shows the arrangement of data written in a first memory of Fig. 2 and its read / write state;

Fig. 4 shows the arrangement of data written in a second memory of Fig. 2 and its read / write state;

Fig. 5A and to which an inner parity is added by an encoder for inner parity of Figure 2 5B assemblies independent decodable code data or dependent decodable code data.

Fig. 6 shows the arrangement of data written in a third memory of Fig. 2 and its read / write state;

Fig. 7 is a block diagram showing the structure of a reproducing system in a digital VTR; and

Fig. 8 is a block diagram showing the detailed structure of an error correction decoder according to the present invention.

In Fig. 1, data compression of a chroma signal (an RGB signal, or a luminance signal or color difference signals) which is input to a recording system is performed by an image compressor 10 , an error correction code is added in an error correction encoder 12 , and the color difference signals are alternately arranged in tracks by a channel encoder 14 , whereby the processed signal is recorded on a tape 16 .

Fig. 2 shows the construction of the error correction encoder according to the present invention.

In Fig. 2, reference numeral 20 denotes a block ID generator for supplying a block identification signal (ID) for each unit block (synchronization block); 22 a vector alpha converter for converting the input data into folds of an alpha value which is the root of a primitive polynomial expression of a Reed-Solomon code (RS); 24 and 26 are a first memory and a first memory controller, respectively, which rearrange and output the data to encode an outer parity of the RS code which has passed through the vector-alpha converter 22 ; 28 denotes an outer parity encoder for adding an outer parity to the sync block in the column direction output from the first memory 24 ; 30 and 32 denote a second memory and a second memory controller, respectively, which rearrange the data to encode an inner parity of the synchronization block which has passed through the outer parity encoder 28 ; 34 denotes a demultiplexer that separates a synchronization block from the second memory 30 into a block ID signal, an IDC and a DDC; 36 and 38 denote first and second inner parity encoders which add the respective inner parities to the block ID signal and the IDC and DDC; 40 denotes a multiplexer for combining the outputs from the first and second encoders 36 and 38 for inner parity; 42 and 44 denote a third memory and a third memory controller, respectively, which rearrange and output the sync block recorded on the tape 16 ; and 46 denotes a synchronization generator that adds a synchronization code for each synchronization block.

The operation of the device shown in Fig. 2 will be described in detail.

The sync block that is output from the state shown in Fig. 10 image compressor 10, consists of the IDC and DDC. The IDC represents data for playback at variable tape speed, which for example comprise a DC voltage component and some low-frequency components in the DCT, or is the result of a first vector quantization in a vector quantization method. The DDC is the section remaining from the section described above. The input synchronization blocks are supplemented by an ID signal, which defines each synchronization block from the ID generator 20 and fed to the first memory 24 , by converting them into folds of α, which is the root of a primitive polynomial expression of an RS code, and through the vector-alpha converter 22 .

The operation of the first memory will now be described with reference to FIG. 3.

As shown in Fig. 3, the sync blocks input to the first memory 24 are written in the X direction, read out in bit units in the Y direction, and then supplied to the outer parity encoder 28 under the control of the first one Memory controller 26 .

The operations of the outer parity encoder 28 , the second memory 30, and the second memory controller 32 will be described with reference to FIG. 4.

As shown in Fig. 4, the outer parity encoder 28 encodes the outer parity with respect to a bit M read out under the control of the first memory controller 26 and adds numbers (OP) for the external parity, whereby the combined result is supplied to the second memory 30 . The data input to the second memory 30 is written in the Y direction under the control of the second memory controller 32 , read out in the X direction in sync block units, and separated into a "block ID signal and IDC" and a "DDC "by the demultiplexer 34 , thereby feeding them to the first inner parity encoder 36 and the second inner parity encoder 38 .

The operations of encoders 36 and 38 for inner parity will be described with reference to FIGS . 5A and 5B.

The first inner parity encoder 36 encodes the inner parity with "the block ID signal (A) and the IDC data (B)" or "the outer parity with respect to that. ***" ID and IDC data ", thereby adding the first inner parity number IP1 as shown in Fig. 5A.

The second inner parity encoder 38 encodes the inner parity, "DDC data (C)" or "outer parity related to the DDC data", thereby adding a second inner parity number IP2 as shown in Fig. 5B. The output signals of the encoders for the inner parity are alternately selected by the multiple xer 40 and fed to the third memory 42 .

The operations of the third memory 42 and the third memory controller 44 will be described with reference to FIG. 6.

The output signals of the first and second encoders 36 and 38 for the inner parity are multiplexed by the multiplexer 40 and fed to the third memory 42 . Under the control of the third memory controller 44 , the data written in the third memory 42 is read out in the X direction in synchronization block units, as shown in FIG. 7, and then supplied to the synchronization generator 46 . The synchronization generator 46 adds a synchronization code to each synchronization block, and thus supplies the result to the channel encoder 14 of FIG. 1.

Fig. 7 explains the structure of a reproduction system in a digital VTR.

In Fig. 7, the signal recorded on a tape 76 is decoded with respect to the channel by a channel decoder 74 , and error compensation or correction is carried out by inner or outer parity via an error correction decoder 72 . Then the original signal (RGB, or a luminance signal and color difference signals) is demodulated by an image expander 70 .

Figure 8 illustrates the error correction code decoder according to the present invention.

In Fig. 8, reference numeral 80 denotes a synchronizing signal detector; 82 and 84 designate a fourth memory and a fourth memory controller, respectively, which rearrange and output the data to divide the synchronization block into a first group consisting of the block ID signal, the IDC and the first inner parity , and into a second group consisting of the DDC and the second inner parity to which the inner parities are added; 86 denotes a demultiplexer which divides the data from the fourth memory 82 into "the first group and the second group" or "the outer parity with respect to the ID and IDC data and the outer parity with respect to the DDC -Data"; 88 and 90 are the decoders for inner parity; 92 is a two-dimensional error mark memory; 94 is an address generator for generating a display address for the two-dimensional mark memory 92 by the error signal from the inner parity decoders 88 and 90 ; 96 is a multiplexer for selectively outputting the block ID signal, IDC and DDC data decoded by the inner parities; 98 and 100 are a fifth memory and a fifth memory controller, respectively, which combine the block ID signal, the IDC and DDC data decoded by inner parities and rearrange them for output; 102 is an external parity decoder; 104 is a switch controlled to block the data transmission path by an error signal ERR1 from the first internal parity decoder 88 ; 106 is a buffer, 108 is a selector that selectively outputs the output signals from the external parity decoder 102 and the buffer 106 in accordance with an externally supplied signal indicating the variable speed tape reproduction; and 110 is an alpha-vector converter for vector converting the data converted in the form of folds of α.

In operation of the device shown in FIG. 8, the synchronization signal detector 80 detects a synchronization code contained in the input binary data column and supplies it to the fourth memory 82 by segmentation in synchronization block units. As shown in FIG. 6, the fourth memory 82 is written by the input synchronization block unit data under the control of the fourth memory controller 84 , reads in the X direction, and supplies the synchronization block unit data to the demultiplexer 86 . The demultiplexer 86 alternately selects the first group and the second group from the input synchronization block unit data, and supplies them to the first decoder 88 for inner parity and the second decoder 90 for inner parity, respectively.

The first and second inner parity decoders 88 and 90 perform error correction of "first group and second group" or "outer parity with respect to the ID and IDC data and outer parity with respect to the DDC "Data" and deliver it to multiplexer 96 according to their respective internal parities. The multiplexer 96 alternately selects the output signals from the first and second decoders 88 and 90 for inner parity and sends them to the fifth memory 98 .

As shown in FIG. 4, under the control of the fifth memory controller 100, the fifth memory 98 writes "the block ID signal and IDC and DDC" or "the outer parity with respect to ID and DDC and the outer parity with respect to it the DDC "encoded by inner parities in the multiplexer 96 de in the X direction and reads out in sync block units in the Y direction, thereby feeding the decoder 102 for the outer parity.

When an error exceeds the inner parity error correction limit, the inner parity decoders 88 and 90 generate error signals ERR1 and ERR2 and send them to the two-dimensional error flag memory 92 . The two-dimensional memory 92 writes the position of a synchronization block in which an error occurs with respect to the error signals ERR1 and ERR2, and an address ADDR in the address generator 94 . The outer parity decoder 102 performs error correction with the sync block in which the non-correctable internal parity error occurs with reference to the two-dimensional error flag memory 92 and supplies it to a selector 108 . The output of the selector 108 is sent to the alpha-vector converter 110 , and is output by converting to the original vector form from foldings of α, which is the root of a primitive polynomial expression of an RS code.

On the other hand, in the case of variable-speed playback, the selector 108 is controlled to select the buffer 106 by a variable-speed playback signal, thereby outputting only the "block ID signal and IDC" output from are output to the first internal parity decoder 88 via a path formed by the switch 104 , the buffer 106 , the selector 108 and the alpha-vector converter 110 . The switch 104 is controlled to output to the buffer 106 only when the data supplied by the first internal parity decoder 88 through the error signal ERR1 has no defects. At this time, since the data from the switch 104 is not data having ID signals for consecutive blocks, a queue-like buffer is required. The error correction path corresponding to the normal playback operation and the playback operation with variable tape speed is selected by controlling the selector 108 in accordance with a tape speed control signal which indicates a tape playback with variable speed.

The foregoing description should make it clear be that a person skilled in the art makes numerous changes and variations could easily be carried out without Nature or scope of the novel concept of the present Deviate invention.

Claims (6)

1. Error correction coding method in a digital video tape recorder (VTR), characterized in that image data of an image are divided into blocks, and a code conversion in block units that the result in an independent decodable code (IDC) and in one dependent decodable code (DDC) is separated to be recorded in a synchronization block unit and the recorded data is reproduced according to the reverse order of the recording step, the step of adding respective first and second inner parities to a block identification signal (ID) and the independently decodable code (IDC) and the dependent decodable code (DDC) is provided within a synchronization block. 2. Error correction decoding method in a digital video tape recorder (VTR), characterized in that image data of an image is divided into blocks and subjected to code conversion in block units, that the result in an independent decodable code (IDC) and a dependent decodable code ( DDC), to which first and second inner parities are added in order to record it in a synchronization block unit, and that the recorded data are reproduced in the reverse order of the recording step, the following steps being provided:
Decoding the independent and dependent decodable codes by the first and second inner parity during normal playback; and
Decoding only the independent decodable code (IDC) by the first inner parity during variable tape speed playback. 3. Error correction coding device in a digital video tape recorder (VTR), characterized in that image data of an image is divided into blocks and subjected to code conversion in block units, that the result in an independent decodable code (IDC) and in a dependent decodable code (DDC) is divided to be recorded in a synchronization block unit by adding a block identification signal (ID), and the recorded data is reproduced in the reverse order of the recording step, the error correction encoder comprising:
a demultiplexer ( 34 ) for inputting the block unit image data to which the block identification signal is added and separating the image data into the block identification signal and the independent decodable code, and the dependent decodable code to be output thereby;
a first inner parity encoder ( 36 ) for adding a first inner parity to the block identification signal and the independent decodable code from the demultiplexer ( 34 );
a second inner parity encoder ( 38 ) for adding a second inner parity to the dependent decodable code from the demultiplexer ( 34 ); and
a multiplexer ( 40 ) for inputting the block identification signal and the independent decodable code to which the first inner parity is added and the dependent decodable code to which the second inner parity is added and to output the result of their combination. 4. Error correction decoding device in a digital video tape recorder (VTR), characterized in that image data of an image is divided into blocks and subjected to code conversion in block units, that the result in an independent decodable code (IDC) and in a dependent decodable code (DDC) that a block identification signal and the independent decodable code and the dependent code are recorded in a synchronization block unit by adding respective first and second inner parities, and that the recorded data is reproduced according to the reverse order of the recording step, the error correction decoding device comprising:
a demultiplexer ( 86 ) for entering the synchronization block, and for separating the synchronization block into a first group consisting of the block identification signal, the independent decodable code and the first inner parity, and a second group consisting of the dependent decodable code and the second inner parity exists to thereby issue it;
a first inner parity decoder ( 88 ) for decoding the block identification signal and the independent decodable code by the first inner parity of the first group from the demultiplexer ( 86 );
a second inner parity decoder ( 90 ) for decoding the dependent decodable code by the second inner parity of the second group from the demultiplexer ( 86 ); and
a multiplexer ( 96 ) for inputting the block identification signal and the independent decodable code from the first inner parity decoder ( 88 ), and the dependent decodable code from the second inner parity decoder ( 90 ), and for output the result of their combination. 5. Error correction decoding device according to claim 4, characterized in that a buffer ( 106 ) for inputting the block identification signal and the independent decodable code from the first decoder for internal parity is also provided, and a selector ( 108 ) for selective output the output signals from the multiplexer ( 96 ) and the buffer ( 106 ). 6. Error correction decoding device according to claim 5, there characterized by the buffer queuing is like a buffer.