DE4300357A1 - Semiconductor device of DRAM structure - comprising substrate, impurity regions formed on substrate, and conducting layers - Google Patents

Abstract

Semiconductor device (I) comprises: (a) a substrate (1) of a 1st conducting type; (b) a 1st and 2nd impurity region (3a, 3b) of a 2nd conducting type formed on the main surface of the substrate on opposite lying sides of an intermediate channel region (16); (c) 3rd impurity region (4) of a 2nd conducting type formed in the 1st impurity region, a gate electrode (6) formed on the channel region with a gate insulating film (5), a 1st conducting layer (8) formed on the 1st and 3rd impurity regions; and (d) a 2nd conducting layer (9) formed on the 1st conducting layer and havng pre-determined impurity regions, where the impurity concn. of the 1st conducting layer is lower than that of the 2nd conducting layer. USE/ADVANTAGE - (I) is a structure of a DRAM.

Description

The invention relates to semiconductor devices according to the preamble of claim 1, 10, 16, 28, 29, 30 or 31 and one Manufacturing process therefor according to the preamble of claim 18, 25 or 26. The invention particularly relates to a structure of a dynamic random access memory (DRAM) and a Manufacturing process therefor.

Lately, the demand is for Semiconductor memory devices among the semiconductor devices quickly increased because of itself  Information processing equipment such. B. Computer have remarkably prevailed. Beyond that Semiconductor memory devices with large storage capacity and Ability to operate at high speed. Accordingly, technological development is high Integration density, high-speed behavior and high Reliability has been promoted.

Among the semiconductor memory devices, a DRAM is known as a memory in which an optional (direct) input / output of stored information is carried out. In general, the DRAM consists of a memory cell array section, which is a memory area for storing a lot of information, and a peripheral circuit section, which is necessary for external input / output. Fig. 38 is a block diagram showing a general DRAM structure. As shown in FIG. 38, a DRAM 120 has a memory cell array 121 for storing a data signal of information, a row and column address buffer 122 for receiving an address signal externally for selecting a memory cell constituting a unit memory circuit, a row decoder 123 and a column decoder 124 for determining a memory cell by decoding the address signal, a read / refresh amplifier 125 for amplifying and reading out a signal stored in a specific memory cell, a data input buffer 126 and a data output buffer 127 for input / output of data and a clock signal generator 128 for generating of a clock signal.

The memory cell array 121 , which occupies a large area on a semiconductor chip, has a plurality of memory cells in a matrix for storing unit memory information. This means that a memory cell usually consists of a MOS transistor and a capacitor connected to it. This memory cell is known as a 1-transistor-1-capacitor memory cell. Because the structure of such a memory cell is simple, it is easy to increase the integration density of a memory cell array, and thus it is widely used for a high-capacity DRAM.

DRAM memory cells can be designed according to the structures of their Capacitors can be divided into several types. In one Stacked capacitor, which is one of these types, can Capacitance of the capacitor can be increased by the Main section of the capacitor to a gate electrode and one Field insulation film extends to enlarge the area on which the electrodes of the capacitor face each other. The Stacked capacitor has such a peculiarity that the Capacitance of the capacitor itself in a miniaturized Establishment with high integration density can be ensured. As a result, a stacked capacitor has been widely used as the integration density of the semiconductor devices has been increased is.

Fig. 39 shows a cross section of a DRAM with a stack capacitor. As shown in FIG. 39, a DRAM has a p-type single crystal silicon substrate 131 , an insulating oxide film (a thick silicon oxide film) 132 for isolating devices formed on predetermined portions of a main surface of the single crystal silicon substrate 131 , a pair of sources - / Drain regions (n⁺ impurity implantation layers) 133 a, 133 b formed in an area surrounded by the insulating oxide film 132 so that a channel region 145 with a predetermined size is formed therebetween, a gate electrode 136 which is formed on the channel region 145 with a gate oxide film 135 therebetween, an interlayer insulating film 137 which is formed to cover the entire surface and has contact holes 137 a, 137 b over the n + impurity implantation layers 133 a, 133 b, a lower capacitor electrode 138 made of low resistance polycrystalline silicon doped with phosphorus (P) with the n⁺ impurity nimplantationsichten 133 b and is formed so that it extends on the interlayer insulating film 137 , an upper capacitor electrode 140 made of low-resistance polycrystalline silicon, which is doped with phosphorus (P) and on the lower capacitor electrode 138 with a dielectric capacitor film 139 made of Ta ₂ O ₅ or the like is formed therebetween, an n⁺ impurity diffusion layer 134 formed by thermal diffusion of impurities (P) of the lower capacitor electrode 138 , an interlayer insulating film 141 formed to cover the entire surface and an opening over the n⁺ - Impurity implantation layer 133 a has a polycrystalline silicon film 142 a, which is electrically connected to the n⁺ impurity implantation layers 133 a and extends on the interlayer insulating film 141 , a silicide film 142 b made of WSi ₂ or similar, which on the polycrystalline silicon film 142 a is formed, an interlayer insulating film 143 , which is formed on the silicide film 142 b, and aluminum wirings 144 , which are formed on the interlayer insulating film 143 at a predetermined distance from one another so that they correspond to the gate electrodes 136 .

A pair of n + impurity implantation layers (source / drain regions) 133 a, 133 b and the gate electrode 136 form a switching MOS transistor. A stacked capacitor is formed from the lower capacitor electrode 138 , the dielectric capacitor film 139 and the upper capacitor electrode 140 to store charges corresponding to a data signal. A bit line 142 consists of a polycrystalline silicon film 142 a and a silicide film 142 b.

Figs. 40 to 47 are cross-sections (of the first to eighth steps), showing a manufacturing process for a DRAM, which is shown in Fig. 39. A manufacturing process for a DRAM will now be described with reference to FIGS. 39 to 47.

As shown in FIG. 40, an insulating oxide film (thick silicon oxide film) 132 for insulation is formed in a predetermined portion on the main surface of the single crystal silicon substrate 131 using a LOCOS (local oxidation of silicon) method.

As shown in Fig. 41, a gate oxide film layer (not shown) is formed on the entire surface using a thermal oxidation method, and a low resistance polycrystalline silicon layer (not shown) doped with impurities (P) , deposited on the gate oxide film layer using a CVD (chemical vapor deposition) method. Patterning is then performed using lithography and dry etching to create a gate oxide film 135 and a gate electrode 136 .

As shown in Fig. 42, a pair of n + impurity implantation layers (source / drain regions) 133 a, 133 b is self-aligned by ion implantation of arsenic (As) at 50keV and 4 ^* 10 ¹⁵ / cm ² under Formed using the gate electrode 136 as a mask. Then the n⁺ impurity implantation layers 133 a, 133 b are electrically activated by a heat treatment.

As shown in Fig. 43, an interlayer insulating film 137 is formed on the entire surface using the CVD method.

As shown in FIG. 44, a contact hole 137 a is created in a portion on the first impurity region 133 b of the interlayer insulating film 137 using lithography and dry etching.

As shown in Fig. 45, the lower capacitor electrode 138 is patterned using lithography and dry etching after the phosphorus (P) doped (not shown) polycrystalline silicon layer is formed on the entire surface by the CVD method. The step of forming the lower capacitor electrode 138 by the CVD method is carried out at a temperature of about 700 ° C so that impurities (phosphorus) in the lower capacitor electrode 138 thermally diffuse to the single crystal silicon substrate 131 . So that the lower capacitor electrode 138 and the n-impurity implantation layer 133 b are electrically connected.

As shown in FIG. 46, the dielectric capacitor film 139 is formed on the lower capacitor electrode 138 . The dielectric capacitor film 139 is made of a single layer film, such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ . After a low-resistance polycrystalline silicon layer (not shown) doped with phosphorus (P) is formed using the CVD method, the upper capacitor electrode 140 is created by patterning using lithography and dry etching. The interlayer insulating film 141 is formed on the entire surface using the CVD method. In order to flatten the top surface of the interlayer insulating film 141 , a heat treatment is carried out at a temperature of about 850 ° C by a reflow process.

As shown in Fig. 47, in the interlayer insulating films 137 and 141 using lithography and dry etching, contact holes 137 a and 141 a are formed in a section on the n⁺-impurity implantation layer 133 a, so that part of the n⁺-impurity implantation layer 133 a exposed. It is doped with impurities of a polycrystalline silicon film so created 142 that it is connected to the exposed n⁺- impurity implantation layer 133 a is electrically and extending on the interlayer 141st A silicide film 142 b made of WSi ₂ or the like is formed on the polycrystalline silicon film 142 a using a sputtering method. An interlayer insulating film 143 is created on the entire surface using the CVD method. To flatten the surface of the interlayer insulating film 143 , a heat treatment is carried out at a temperature of about 850 ° C by a reflow process.

Finally, as shown in FIG. 39, aluminum wirings 144 are formed with predetermined intervals between them.

As described above, a DRAM has been created.

In a memory cell constituting a DRAM as described above impurity (phosphorus) in the lower capacitor electrode 138 are thermally diffused to the single crystal silicon substrate 131, so that the n + impurity diffused layer 134 for electrically connecting the n + impurity implantation layer 133 b and the lower capacitor electrode 138 is formed. This means that the n⁺ impurity diffusion layer 134 is created by thermal diffusion by means of heat at approximately 700 ° C. when the lower capacitor electrode 138 is formed.

However, as shown in Fig. 46, a temperature of about 850 ° C is applied in the reflow process to flatten the surface after the interlayer insulating film 141 is formed. As a result, impurities (phosphorus) in the lower capacitor electrode 138 are further diffused to the single crystal silicon substrate 131 . This further increases the diffusion area of the nend impurity diffusion layer 134 . This leads to the disadvantage that an end portion B of the n⁺ impurity diffusion layer 134 extends from an end portion A of the n⁺ impurity implantation layer 133 b on the side of the gate electrode 136 . In addition, as shown in Fig. 47, the interlayer insulating film 143 is also subjected to a heat treatment at about 850 ° C in the reflow process for leveling, so that impurities (phosphorus) in the lower capacitor electrode 138 are further diffused to the single crystal silicon substrate 131 and thus the n⁺ impurity diffusion layer 134 further diffuses to the gate electrode side.

When a portion of the n⁺-type impurity diffusion layer 134 b projecting from the side of the gate electrode 136 by the impurity implantation n⁺- 133 and extends under the gate electrode 136, the following problems may occur.

The effective gate length L _{0 of} the gate electrode 136 is shortened by the expanded region of the n⁺ impurity diffusion layer 134 from the n⁺ impurity implantation layer 133 b. This means that the effective gate length becomes L ₁ . This causes a so-called short-channel effect in which the threshold voltage of a switching MOS transistor is reduced. If the channel length is short, a depletion layer in the vicinity of the n⁺ impurity implantation layer 133 a, which is to form a drain region when writing data, extends to the n⁺ impurity diffusion layer 134 , which is to form a source region, and therefore can The problem arises that a so-called breakdown can easily occur in which the current cannot be controlled by the gate voltage. Furthermore, the n⁺ impurity diffusion layer 134 is not created as an n⁺ impurity implantation layer 133 b in a self-aligning manner, so that the expanded portion of the n⁺ impurity diffusion layer 134 from the n⁺ impurity implantation layer 133 b is dependent on the variation in the orientation of the gate Electrode 136 and lower capacitor electrode 138 vary in patterning. The problem thus arises that the transistor characteristics, such as. B. the threshold voltage vary.

Fig. 48 shows a cross section of the structure of a DRAM with another stack capacitor. As shown in Fig. 48, this DRAM has a p-type single crystal silicon substrate 241 with a trench 241 a formed in a predetermined portion on its main surface, an insulating oxide film 242 for device isolation which is on the main surface of the single crystal silicon substrate 241 formed and adjacent to the trench 241 a, an n⁺ impurity implantation layer 243 b, the end portion of which is formed in contact with a side wall of the trench 241 a, an n⁺ impurity implantation layer 243 a, which is formed such that a channel region 257 between the n⁺ impurity implantation layers 243 a and 243 b is enclosed at a predetermined distance from one another, an n⁺ impurity implantation layer 244 , which is formed along the surface of the trench 241 a, a gate electrode 247 which is connected to the channel region 257 with a gate Oxide film 246 is formed in between, an interlayer insulating film 248 with contact holes 248 a and 248 b over the n + impurity implantation layer 243 a and a recessed portion 241 a, a lower capacitor electrode 250 made of a polycrystalline silicon film with low resistance, which has a large amount of impurities (phosphorus (P) with 4-8 ^* 10 ²⁰ / cm ³⁾ has, and is formed such that it extends to a surface of the interlayer insulating film 248 and formed on the n⁺- impurity implantation 244 241 a is located on the bottom and the side wall of the recessed portion, a capacitor dielectric film 251, created on the lower capacitor electrode, an upper capacitor electrode 252 formed on the dielectric capacitor film 251 , an n⁺ impurity diffusion layer 245 formed by thermal diffusion of impurities in the lower capacitor electrode 250 , an interlayer insulating film 253 thus formed is that it covers the entire surface and a K contact hole 253 a over the n⁺-impurity implantation layer 243 a, a polycrystalline silicon film 254 a, which is electrically connected in contact holes 248 a, 253 a with the n⁺-impurity implantation layer 243 a and is formed along the surface of the interlayer insulating film 253 , a silicide film 254 b, which is on the polycrystalline silicon film 254 a formed, an interlayer insulating film 255, which is provided on the b silicide film 254, and aluminum wirings 256 which are formed at predetermined intervals from each other on the interlayer insulating film 255, on.

The DRAM of another type with such a structure has problems similar to the DRAM shown in FIG. 39. That is, to flatten the surface of the interlayer insulating films 253 and 255, heat treatment is carried out at about 850 ° C in a reflow process. This heat treatment causes impurities (phosphorus) in the lower capacitor electrode 250 to thermally diffuse to the single crystal silicon substrate. The widening of the diffusion area of the n Stör impurity diffusion layer 245 thus continues. This leads to the disadvantage that an end portion B of the n⁺ impurity diffusion layer 245 extends from an end portion A of the n⁺ impurity implantation layer 243 b on the gate electrode 247 side to the lower part. This results in the appearance of a short channel effect and the likelihood of a penetration.

The object of the invention is to shorten the effective gate Effectively prevent length in a semiconductor device. Further is to be effectively prevented that the transistor properties in of a semiconductor device fluctuate. Furthermore, in one subsequent heat treatment step in a Manufacturing process for a semiconductor device diffusion of impurities contained in a lower capacitor electrode are effectively reduced in a semiconductor substrate. task the invention is also to shorten an effective Effectively prevent channel length even when there are defects a lower capacitor electrode in the following Heat treatment step is diffused further.

The object is achieved by the in claims 1, 10, 16, 28, 29, 30 or 31 labeled facility. The procedure is in progress 18, 25 or 26 marked. In one aspect of the present Invention, a semiconductor device has a semiconductor substrate of a first conductivity type with a main surface, one first and a second impurity region of a second Conductivity type that are spaced apart on the Main surface of the semiconductor substrate on each other opposite sides of one enclosed between them Channel area are formed, a third impurity area of the second conductivity type, that in the first impurity area is formed, a gate electrode which is on the channel region an interposed gate insulating film is formed, one first conductive layer on top of the first and third Impurity region is formed and predetermined impurities  and a second conductive layer on top of the first conductive layer is formed and predetermined impurities has on. The impurity concentration of the first conductive Layer is lower than that of the second conductive layer.

Because the first conductive layer with the lesser Impurity concentration than that of the second conductive layer between a first impurity region and a second conductive one Layer is included, the diffusion of Impurities in the second conductive layer to the semiconductor substrate reduced in one heat treatment step compared to previously. This will also further diffuse impurities in the second conductive layer in the semiconductor substrate in the following Heat treatment step effectively diminished, and the expansion an end portion of the third impurity region on the side the gate electrode from an end portion of the first Impurity area on the side of the gate electrode, which by Diffusion is effectively prevented. If at the Pattern a fluctuation in the alignment of the gate electrode and the second conductive layer occurs, the extension of the Side portion of the third impurity region on the gate Electrode side from the end portion of the first impurity region the gate electrode effectively prevented.

In a further aspect of the present invention, a Semiconductor device is a semiconductor substrate of a first Conductivity type with a main surface and a recessed one Section in a predetermined area on the main surface, a first impurity region of a second conductivity type, which is in a predetermined area on the main surface of the Semiconductor substrate is formed, a second impurity region of the second conductivity type that runs along the surface of the recessed portion of the semiconductor substrate is formed and a Has distance from the first impurity area, so that a Channel area in between, a third impurity area of the second conductivity type, which is on the bottom surface of the recessed Portion of the semiconductor substrate is formed to the second  Overlap impurity area, a gate electrode on the Channel area with a gate insulating film in between is formed, a side wall insulating film on the second Impurity area on a side wall of the recessed portion is formed, and a conductive layer that merges with the second Impurity area at the bottom portion of the recessed area connected and extending along the side wall insulating film extends to.

The second impurity area is along the surface of the recessed portion of the semiconductor substrate, and the Sidewall insulating film is on the second impurity area the side wall of the recessed section. A senior Layer s is formed with the second impurity region is connected at the bottom portion of the recessed area and itself extends along the sidewall insulating film. Even if that Impurities in the conductive layer due to a heat treatment for the conductive layer is diffused into the semiconductor substrate, consequently, an impurity region which is formed by the heat treatment with the channel area between the first impurity area and the second Impurity area overlaps. Even if there is a fluctuation in the Alignment of the conductive layer and the gate electrode occurs, can also be effectively prevented from the impurity region overlapped with the channel area.

In a further aspect of the present invention, a Semiconductor device is a semiconductor substrate of a first Conductivity type with a main surface and a recessed one Section in a predetermined area of the main surface, one first impurity region of a second conductivity type, which in a predetermined area on the main surface of the Semiconductor substrate is formed, a second impurity region of the second conductivity type that runs along the surface of the recessed portion of the semiconductor substrate is formed to a Channel area between the first and the second impurity area to enclose at a predetermined distance from one another  third impurity region of the second conductivity type based on the bottom surface of the recessed portion of the semiconductor substrate overlaps the second impurity region, a gate electrode that on the channel area with a gate in between Insulating film is formed, a sidewall Diffusion reduction film on the second impurity region is formed on the side wall of the recessed portion, and a conductive layer with a predetermined amount of impurities, the with the second and third impurity area at the bottom of the recessed area connected and along the side wall Diffusion reduction film is formed on.

The second impurity area is along the surface of the recessed portion of the semiconductor substrate is formed, the Sidewall diffusion reduction film is on the second Impurity area on the side wall of the recessed portion created, and the conductive layer is formed so that it with the second and third impurity areas at the bottom of the recessed Section is connected and along the side wall Diffusion reduction film extends. Even if imperfections in of the conductive layer by heat treatment of the conductive Diffusing layer into the semiconductor substrate will be accordingly effectively prevents that from thermal diffusion third impurity region formed overlaps with the channel region, between the first and second impurity area located. Even if there are fluctuations in the orientation at the Patterning of the conductive layer and the gate electrode is there an overlap of the third impurity region and the Channel area effectively prevented.

In a further aspect of the present invention Manufacturing process for a semiconductor device the steps Formation of a gate electrode on a main surface of a Semiconductor substrate of a first conductivity type with a gate Insulating film in between, forming a first and a second Impurity region of a second conductivity type Storage of impurities, formation of an insulating layer with a  Opening on the first impurity area, forming a first conductive layer on the first impurity region in the opening, Form a second conductive layer with a higher one Impurity concentration than that of the first conductive layer the first conductive layer, and forming a third Impurity region of the second conductivity type due to thermal Diffusion of the impurities in the lower capacitor electrode for Semiconductor substrate through the first conductive layer.

The first conductive layer with the impurities is on the first Impurity region formed, the second conductive layer with more Impurities as the first conductive layer is on the first conductive layer is created, and the third impurity region is by thermal diffusion of the impurities in the second conductive Layer to the semiconductor substrate through the first conductive layer educated. The amount of impurities from the second conductive Diffused to the semiconductor substrate is by the first conductive layer reduced compared to the previous case, so the amount of impurities in the second conductive layer, which are further diffused into the semiconductor substrate, likewise is effectively reduced. It is prevented that the End portion of the third impurity region on the gate side Electrode from the end portion of the first impurity region on the Side of the gate electrode extended to the side of the gate electrode. Therefore, a fluctuation in the transistor properties can also occur be prevented.

In a further aspect of the present invention Manufacturing process for a semiconductor device the steps Formation of a gate electrode on a main surface of a Semiconductor substrate of a first conductivity type with a gate Insulating film in between, forming a first impurity region a second conductivity type by incorporating impurities, Form a recessed section on the main surface of the Semiconductor substrate at a predetermined distance from the first Impurity region, forming a second impurity region of the second conductivity type along the main surface of the  recessed portion, forming a sidewall insulating film a sidewall portion of the recessed portion, forming one conductive layer that is electrically connected to the bottom portion of the recessed section is connected and along the side wall Insulating film extends on.

The recessed section is in the main surface of the Semiconductor substrate, the second impurity region along the Main surface of the recessed portion, the sidewall Insulating film on the side wall portion of the recessed portion, and the conductive layer that is electrically connected to the bottom portion of the recessed section is connected and has defects, formed along the side wall insulating film. Even if that Impurities in the conductive layer in the following Heat treatment can be further diffused, can thus be prevented be that the impurity region formed by diffusion the Channel area between the first impurity area and the second Impurity area overlaps. Even if there is one in the pattern Fluctuation in the alignment of the gate electrode and the conductive one Layer occurs, is also prevented by diffusion created impurity area overlaps with the channel area, and therefore a variation in the transistor properties can also occur be prevented.

In a further aspect of the present invention Manufacturing process for a semiconductor device the steps Formation of a gate electrode on a main surface of a Semiconductor substrate of a first conductivity type with a gate Insulating film in between, forming a first impurity region a second conductivity type by incorporating impurities, Form a recessed section on the main surface of the Semiconductor substrate at a predetermined distance from the first Impurity region, forming a second impurity region of the second conductivity type along the main surface of the recessed section, forming a sidewall Diffusion reduction film on a side wall of the recessed Portion, forming a conductive layer with a predetermined one  Amount of impurities that are electrically recessed with the bottom of the Section is connected and along the side wall Extends diffusion reduction film, and forming a third Impurity region of the second conductivity type due to thermal Diffusion of impurities in the conductive layer to the bottom of the recessed section.

The recessed section is in the main surface of the Semiconductor substrate, the second impurity region along the Main surface of the recessed portion, the sidewall Diffusion reduction film on the side wall of the recessed Section, the conductive layer with impurities, the electrically with is connected to the bottom of the recessed portion along the Sidewall diffusion reduction film and the third Impurity region through thermal diffusion of the impurities in the conductive layer formed to the bottom of the recessed portion. Even if the defects in the conductive layer are caused by a subsequent heat treatment can be diffused further accordingly effectively prevented by diffusion third impurity area formed the channel area between the first impurity region and the second impurity region overlaps. Even if there is a variation in alignment when patterning of the gate electrode and the conductive layer also occurs prevents the third created by diffusion Impurity area overlaps with the channel area. Therefore Fluctuations in transistor properties prevented.

Further features and advantages of the invention result from the description of exemplary embodiments with reference to the figures. From the figures show:

Fig. 1 shows a cross section of a DRAM having a stacked capacitor according to a first embodiment of the invention;

FIG. 2 is an enlarged cross section of the contact area of the lower capacitor electrode shown in FIG. 1;

Fig. 3 is a diagram of the distribution of the impurity concentration where the impurity concentration of the contact area is compared in Fig lower capacitor electrode shown in Figure 2 with the contact portion of a known capacitor lower electrode of.

Fig. 4 to 12 cross-sections of the respective steps of a manufacturing method of the DRAM shown in Figure 1 according to the first embodiment.

13 is a cross section of a DRAM having a stacked capacitor according to a second embodiment of the invention.

Fig. 14 to 22 cross-sections of the respective steps of a manufacturing method of the DRAM shown in Figure 13 according to the second embodiment.

23 is a cross section of a DRAM having a stacked capacitor according to a third embodiment of the invention.

Fig. 24 to 33 cross-sections of the respective steps of a method of manufacturing the DRAM shown in Figure 23 according to the third embodiment.

34 is a cross section of a DRAM having a stacked capacitor according to a fourth embodiment of the invention.

Figure 35 is a cross section of a DRAM having a stacked capacitor according to a fifth embodiment of the invention.

Figure 36 is a cross section of a DRAM having a stacked capacitor according to a sixth embodiment of the invention.

Figure 37 is a cross section of a DRAM having a stacked capacitor according to a seventh embodiment of the invention.

Fig. 38 is a block diagram of the structure of a general DRAM;

FIG. 39 is a cross section of a DRAM with a known stacked capacitor;

Fig. 40 to 47 cross-sections of the respective steps of a manufacturing method for the conventional DRAM shown in Fig. 39; and

Fig. 48 shows a cross section of a DRAM with another known stacked capacitor.

As shown in FIG. 1, a DRAM of the embodiment has a p-type single crystal silicon substrate 1 , an insulating oxide film (a thick silicon oxide film) 2 for isolating devices formed on a main surface of the single crystal silicon substrate 1 at a predetermined distance from each other , A pair of n⁺ impurity implantation layers (source / drain regions) 3 a, 3 b, which are formed in a region surrounded by the insulating oxide film 2 , so that the channel region 16 lies between them with a predetermined size, a gate -Electrode 6 , which is formed on the channel region 16 over a gate oxide film 5 , an interlayer insulating film 7 , which is formed to cover the entire surface and has contact holes 7 a, 7 b on the n⁺ impurity implantation layers 3 a and 3 b , An epitaxial silicon layer 8 , which is formed so that it is connected to the n⁺ impurity implantation layer 3 b in the contact hole 7 b, ei ne lower capacitor electrode 9 made of a polycrystalline silicon film with low resistance, which is doped with phosphorus (P), having a higher impurity concentration than the epitaxial silicon layer 8 and is formed on the epitaxial silicon layer 8, a capacitor dielectric film 10 of a layer of thermal oxide film or Similar, a multi-layer structure from z. As a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like, which is formed on the lower capacitor electrode 9 , an upper capacitor electrode 11 made of polycrystalline silicon with low resistance, which is doped with phosphorus (P), which on the dielectric capacitor film 10 is formed, an n⁺ impurity diffusion layer 4 , which is formed by thermal diffusion of the impurities (phosphorus) in the lower capacitor electrode 9 to the single-crystal silicon substrate 1 , for electrically connecting the n⁺ impurity implantation layer 3 b and the lower capacitor electrode 9 having an interlayer 12, which is formed to cover the entire surface and a contact hole 12 a over the n + impurity implantation layer 3 a, a polycrystalline silicon film 13 a provided with the n⁺- impurity implantation layer 3 a in the contact holes 7 a, 12 a is connected and on the intermediate layer insulation film 12 extends, a silicide film 13 b of WSi ₂ , which is formed on the polycrystalline silicon film 13 a, an interlayer insulation film 14 , which is formed on the silicide film 13 b, and aluminum wirings 15 , which are on the interlayer insulation film 14 with a predetermined distance between them are formed on.

A switching MOS transistor is formed by a pair of n⁺ impurity implantation layers (source / drain regions) 3 a, 3 b and the gate electrode 6 . A bit line 13 for transmitting a data signal is formed from a polycrystalline silicon film 13 a and a silicide film 13 b. A stacked capacitor is formed by the lower capacitor electrode 9 , the dielectric capacitor film 10 and the upper capacitor electrode 11 for storing charges in accordance with the data signal.

In this embodiment, the epitaxial silicon layer 8 is with a lower impurity concentration than that of the lower capacitor electrode 9 between the n⁺ impurity implantation layer 3 b and the lower capacitor electrode 9 , as described above, so that the amount of impurities (phosphorus) in the lower capacitor electrode 9 , which diffuses to the single-crystal silicon substrate 1 , is reduced.

FIG. 2 shows an enlarged cross section of the contact area of the lower capacitor electrode 9 of the DRAM according to the first embodiment shown in FIG. 1. Fig. 3 is a diagram showing a comparison between the impurity concentration distribution along the X-axis of the DRAM according to the first embodiment and the known impurity concentration. As shown in FIGS. 2 and 3, the impurity concentration of the first embodiment is the impurity concentration of the lower capacitor electrode 9 (4-8 × 10 ²⁰ / cm ³ ) between a point C and a point D along the X axis of FIG. 2. When the point D is passed, the impurity concentration gradually drops. This means that the impurity concentration in the epitaxial silicon layer 8 between the point D and a point E and in the n⁺ impurity diffusion layer 4 (single-crystal silicon substrate 1 ) after the point E decreases continuously. The impurity concentration along the X-axis finally drops to the value of the impurity concentration (1 × 10 ¹⁵ / cm ³ ) of the single crystal silicon substrate 1 . On the other hand, in a known DRAM without an epitaxial silicon layer 8, a lower capacitor electrode is formed in a region of the epitaxial silicon layer 8 shown in FIG. 2 (the section between the points D and E). As shown in FIG. 3, the impurity concentration in a known capacitor structure is therefore constant from point C to point E (4-8 × 10 ²⁰ / cm ³ ). Only after passing point E does the impurity concentration begin to drop. This means that in the known structure, the impurity concentration begins to decrease when the impurities penetrate into the n Stör impurity diffusion layer 4 on the single-crystal silicon substrate 1 . Thus, between the known capacitor structure and the capacitor structure of the first embodiment, there is a difference in the position at which the impurity concentration drops to the value of the impurity concentration of the single crystal silicon substrate 1 (1 × 10 ¹⁵ / cm ³ ). In other words, as shown in Fig. 3, there is a difference between the known capacitor structure and the capacitor structure of the first embodiment in the position at which the respective impurity concentration is equal to the value of the impurity concentration of the single crystal silicon substrate 1 (1 × 10 ¹⁵ / cm ³ ) decreases, only in the L section. This shows that the diffusion path of the impurities in the capacitor structure of the first embodiment can be reduced by the L portion compared to the known capacitor structure. When heat treatment is carried out at about 850 ° C to e.g. B. to level the interlayer insulating films 12 , 14 (see FIG. 1), the diffusion of the impurities in the n⁺ impurity diffusion layer is reduced. Thus, protrusion of the end portion of the n⁺ impurity diffusion layer 4 on the gate electrode 6 side from the end portion of the n⁺ impurity implantation layer 3 b on the gate electrode 6 side , as has been the case so far, can be effectively prevented. This can effectively prevent a short channel effect without shortening the length of the channel area. Furthermore, a so-called penetration can be effectively prevented, in which a depletion layer in the vicinity of the n-impurity implantation layer 3 a, the z. B. is to form a drain region when writing data, up to the extended n⁺ impurity diffusion layer 4 , which is to form a source region. This means that the current cannot be controlled by the gate voltage. Even if variations in the alignment of the gate electrode 6 and the lower capacitor electrode 9 occur in the patterning, the end portion of the n⁺- impurity diffusion layer 4 on the side of the gate electrode 6 is not b from the end portion of the n⁺-impurity implantation layer 3 on the Side of the gate electrode expanded because the diffusion of impurities in the n⁺ impurity diffusion layer 4 is reduced. Thus, the channel length of the channel 16 can be controlled by the n⁺ impurity implantation layer 3 b in a self-aligning manner, so that the transistor properties are stable regardless of the fluctuations in the alignment of the gate electrode 6 and the lower capacitor electrode 9 .

A manufacturing method for the DRAM according to the embodiment will now be described with reference to FIGS. 1 and 4 to 12.

As shown in FIG. 4, a thick silicon oxide film (an isolation oxide film) 2 is selectively formed on the main surface of the p-type single crystal silicon substrate 1 using a LOCOS method.

As shown in Fig. 5, a gate oxide film layer (not shown) is formed on the entire surface using a thermal oxidation process, and a polycrystalline silicon layer (not shown) doped with phosphorus is formed thereon using the CVD process. Then, patterning is performed using lithography and dry etching to create a plurality of gate oxide films 5 and gate electrodes 6 with a predetermined distance from each other.

As shown in Fig. 6, arsenic (As) with 4 × 10 ¹⁵ / cm ² at 50keV is ion-implanted using the gate electrode 6 as a mask, so that n⁺ impurity implantation layers 3 a, 3 b are formed.

As shown in Fig. 7, an interlayer insulating film 7 is formed on the entire surface using the CVD method.

As shown in Fig. 8, a contact hole 7 is using lithography and dry etching b in a region on the impurity implantation n⁺- 3 b in the interlayer insulating film 7 together.

As shown in Fig. 9, silicon grows epitaxially at about 700 ° C for several ten minutes on the n⁺ impurity implantation layer 3 b, which is exposed through the contact hole 7 b, so that the epitaxial silicon layer 8 is formed. The thickness t of the epitaxial silicon layer 8 should be adjusted by including the distance W between the gate electrode 6 and the lower capacitor electrode 9 (see Fig. 1) and the impurity concentration of the lower capacitor electrode 9 in such a range that the end portion B of the n Stör- impurity diffusion layer 4 on the side of the gate electrode 6 , which is finally created by diffusion, is not extended from the end portion A of the n⁺ impurity implantation layer 3 b on the side of the gate electrode 6 . Under these conditions, the impurity concentration of the epitaxial silicon layer 8 is approximately 1 × 10 ¹⁵ / cm ³ (corresponding to the impurity concentration of the single-crystal silicon substrate 1 ). If e.g. B. W = 0.3 µm, S = 0.1 µm, it is preferred that t = 0.1 µm, the impurity concentration of the lower capacitor electrode 9 being 4-8 × 10 ²⁰ / cm ³ . The impurity concentration of the epitaxial silicon layer 8 is set to any value according to the external parameters, such as. B. the impurity concentration of the lower capacitor electrode 9 is set.

As shown in FIG. 10, a low resistance polycrystalline silicon layer doped with phosphorus (P) to 4-8 × 10 ²⁰ / cm ^{3 is formed} on the epitaxial silicon layer 8 and the interlayer insulating film 7 by the CVD method. The lower capacitor electrode 9 is usually created by lithography and dry etching by patterning. The lower capacitor electrode 9 is formed at a temperature of 700 ° C., so that impurities (phosphorus) in the lower capacitor electrode 9 thermally diffuse through the epitaxial silicon layer 8 to the single-crystal silicon substrate 1 . The n⁺ impurity diffusion layer 4 is formed and the lower capacitor electrode 9 and the n⁺ impurity implantation layer 3 b are electrically connected.

As shown in Fig. 11, a dielectric capacitor film 10 is formed from a single layer, such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ and the like are formed on the lower capacitor electrode 9 . A low-resistance polycrystalline silicon layer (not shown) doped with phosphorus of 4-8 × 10 ²⁰ / cm ³ is formed on the dielectric capacitor film 10 by the CVD method. The upper capacitor electrode 11 is created using pattern lithography and dry etching. The interlayer insulating film 12 is formed by the CVD method. In order to flatten the interlayer insulating film 12 , heat treatment is performed by a reflow process at 850 ° C. Impurities (phosphorus) in the lower capacitor electrode 9 are diffused further into the single-crystal silicon substrate 1 by this heat treatment. However, the degree of diffusion is reduced by the epitaxial silicon layer 8 . Thus, the end portion B of the n + impurity diffusion layer 4 on the gate electrode 6 side , which is formed by diffusion, is not extended from the end portion A of the n + impurity implantation layer 3 b on the gate electrode 6 side.

As shown in Fig. 12, contact holes 7 a, 12 a are created on the n⁺ impurity implantation layer 3 a in the interlayer insulating film 7 and 12 , respectively. A polycrystalline silicon film 13 a is formed so that it extends on the interlayer insulating film 12 and is connected to the n-impurity implantation layer 3 a in the contact hole 7 a, 12 a. A silicide film 13 b made of WSi ₂ or the like is formed on the polycrystalline silicon film 13 a using a sputtering method. An interlayer insulating film 14 is created on the silicide film 13 b. A heat treatment is carried out by a reflow process at 850 ° C. to flatten the surface of the interlayer insulation film 14 . During the heat treatment, the defects (phosphorus) in the lower capacitor electrode 9 are also thermally diffused to the single-crystal silicon substrate 1 . However, the diffusion is reduced again by the epitaxial silicon layer 8 . Thus, the end portion of the n⁺ impurity diffusion layer 4 on the gate electrode 6 side formed by diffusion is not extended from the end portion of the n⁺ impurity implantation layer 3 b on the gate electrode 6 side.

Thus, the epitaxial silicon layer 8 effectively prevents the end portion of the n⁺-type impurity diffusion layer 4 on the side of the gate electrode 6 b from the end portion of the n⁺- impurity implantation layer 3 in the heat treatment for planarization of the interlayer 12 is expanded fourteenth In contrast to the previous, the effective gate length (channel length) is therefore not shortened, and a short channel effect, crackdown or the like can be effectively prevented.

As shown in FIG. 13, a DRAM according to a second embodiment has a p-type single crystal silicon substrate 21 , an insulating oxide film 22 formed in a predetermined area on the main surface of the single crystal silicon substrate 21 , a pair of n⁺ impurity implantation layers (Source / drain regions) 23 a, 23 b, which are formed in an area which is surrounded by the insulating oxide film 22 , so that a channel region 36 with a predetermined size lies therebetween, a gate electrode 26 which is on the channel region 36 is formed over a gate oxide film 25 , an interlayer insulating film 27 , which is formed to cover the entire surface and has contact holes 27 a, 27 b on the n + impurity implantation layers 23 a and 23 b, a polycrystalline silicon film 28 with high resistance and a small amount of impurities (phosphorus), which is formed so that it in contact with the n⁺ impurity implantation layer 23 b hole 27 b is connected and extends along the interlayer insulating film 27 , a lower capacitor electrode 29 on a polycrystalline silicon film 28 with an impurity concentration (phosphorus (P) to 4-8 × 10 ²⁰ / cm ³ ) higher than that of the polycrystalline silicon film 28 , one dielectric capacitor film 30 made of a single layer such. B. a thermal oxide film, a multilayer structure of z. A silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like on the lower capacitor electrode 29 , an upper capacitor electrode 31 formed on the dielectric capacitor film 30 and almost the same impurity concentration (phosphorus (P) to 4-8 × 10 ²⁰ / cm ³ ) as the lower capacitor electrode 29 , an n⁺ impurity diffusion layer 24 , which is formed by thermal diffusion of the impurities (phosphorus) in the lower capacitor electrode 29 through the polycrystalline silicon film 28 , an interlayer insulating film 32 , which to cover the entire surface is formed and a contact hole 32 a over the n⁺ impurity implantation layer 23 a, a polycrystalline silicon film 33 a doped with impurities, which is connected to the n⁺ impurity implantation layer 23 a in the contact holes 27 a, 32 a and along of the interlayer insulating film 32 extends a silicon dfilm 33 b of WSi ₂ or the like, which is formed on the polycrystalline silicon film 33 a, an interlayer insulating film 34 , which is formed on the silicide film 33 b, and aluminum wirings 35 , which are formed on the interlayer insulating film 34 at a predetermined distance from one another .

In the second embodiment, the polycrystalline silicon film 28 is located with a lower impurity concentration than that of the lower capacitor electrode 29 between the lower capacitor electrode 29 and the n⁺ impurity implantation layer 23 b, so that, as in the first embodiment shown in FIG. 1, the diffusion of impurities in the n⁺ impurity diffusion layer 24 , which is formed by the diffusion, is reduced. This means that the impurities (phosphorus) in the lower capacitor electrode 29 , which diffuse in the heat treatment for leveling the interlayer insulating films 32 , 34 into the single crystal silicon substrate, can be reduced. Thus can be effectively prevented that the end portion B of the n⁺- impurity diffusion layer 24 b on the side of the gate electrode 26 from the end portion A of the n + impurity implantation layer 23 on the side of the gate electrode 26 in the above-mentioned heat treatment for the interlayer 32 , 34 is expanded. As a result, as shown in FIG. 1, a short channel effect, penetration and other variations in transistor characteristics depending on variations in the alignment of gate electrode 26 and lower capacitor electrode 29 can be effectively prevented in the patterning.

A manufacturing method for the DRAM according to the second embodiment will now be described with reference to FIGS. 13 to 22.

The steps shown in FIGS. 14 to 18 (first to fifth steps) correspond to those in the manufacturing method of the first embodiment, which are shown in FIGS. 4 to 8. After these steps, as shown in Fig. 19, a polycrystalline silicon film 28 a (with an impurity concentration of 1 × 10 ¹⁵ / cm ³ ) with high resistance is formed, and a lower capacitor electrode 29 a made of a polycrystalline silicon layer with a large amount Phosphorus (4- 8 × 10 ²⁰ / cm ³ ) is created on it. In the formation of the polycrystalline silicon film layer 28 a and the lower capacitor electrode 29 a a temperature of 700 ° C is applied, and the impurity in the lower capacitor electrode 29 a is diffused by the polycrystalline silicon film layer 28 a thermally in the single crystal silicon substrate 21st Thus, the n⁺ impurity diffusion layer 24 is created, and the n⁺ impurity implantation layer 23 b and the lower capacitor electrode 29 a are electrically connected. The diffusion of the defects from the lower capacitor electrode 29 a is reduced because of the presence of the polycrystalline silicon film layer 28 a.

As shown in Fig. 20, the polycrystalline silicon film layer 28 a and the lower capacitor electrode 29 a patterned using well-known lithography and dry etching to form a polycrystalline silicon film 28 and to provide a capacitor lower electrode 29.

As shown in Fig. 21, the dielectric capacitor film 30 is made of a single layer such as. B. a thermal oxide film, a multilayer film with the structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like is formed on the lower capacitor electrode 29 . The upper capacitor electrode 31 of a low-resistance polycrystalline silicon film having the same impurity concentration (phosphorus with 4-8 × 10 ²⁰ / cm ³ ) as the lower capacitor electrode 29 is created on the dielectric capacitor film 30 . The interlayer insulating film 32 is formed on the entire surface using the CVD method. In order to flatten the surface of the interlayer insulating film 32 , a heat treatment at 850 ° C. is carried out by a melting process.

As shown in Fig. 22, contact holes 27 a, 32 a are created on the n-impurity implantation layer 23 a in the interlayer insulating films 27 and 32 , respectively. The polycrystalline silicon film 33 a in electrical contact with the n-impurity implantation layer 23 a in the contact holes 27 a, 32 a is created using the CVD process and extends on the interlayer insulating film 32nd The silicide film 33 b made of WSi ₂ or the like is formed on the polycrystalline silicon film 33 a by means of the sputtering method. On the silicide film 33 b, the interlayer insulating film 34 is created using the CVD method. In order to level the surface of the interlayer insulating film 34 , a heat treatment at 850 ° C. is carried out by the melting process.

Finally, aluminum wirings 35 are formed on the interlayer insulating film 34 at a predetermined interval from each other, as shown in FIG. 13. The DRAM according to the second embodiment is now complete.

As shown in Fig. 23, a DRAM according to a third embodiment has a p-type single crystal silicon substrate 41 having a trench 41 a in a predetermined area in its main surface, an insulating oxide film (a thick silicon oxide film) 42 adjacent to the trench 41 a for isolation of components formed on the main surface of the single crystal silicon substrate 41 , an n⁺ impurity implantation layer 43 b, the end portion of which is adjacent to the side wall portion of the trench 41 a, an n⁺ impurity implantation layer 43 a, between the and the n⁺ impurity implantation layer 43 b there is a channel region 57 with a predetermined width, an n + impurity implantation layer 44 along the surface of the trench 41 a, a gate electrode 47 which is formed on the channel region 57 with a gate oxide film 46 therebetween, an interlayer insulating film 48 , which is formed to cover the entire surface and contact holes 48 a, 48 b on the n⁺- impurity implantation layer 43 a and a recessed portion 41a having, a sidewall insulating film 49 which is formed on the side wall portions of the contact hole 48 b of the interlayer 48 and the recessed portion 41 a, a lower capacitor electrode 50 a low-resistance polycrystalline silicon film having a large amount of impurities (phosphorus (P) of 4-8 × 10 ²⁰ / cm ³ ) is electrically connected to the n⁺ impurity implantation layer 44 at the bottom portion of the recessed portion 41 a and extends along the side wall insulating film 49 and the interlayer insulating film 48 , a dielectric capacitor film 51 made of a single layer such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like on the lower capacitor electrode 50 , an upper capacitor electrode 52 made of a polycrystalline silicon film with low resistance, the almost same amount of impurities (4-8 × 10 ²⁰ / cm ³⁾ as the lower capacitor electrode 50 and being formed on the capacitor dielectric film 51, an n⁺- type impurity diffusion layer 45 which is formed by thermal diffusion of the impurity (phosphorus) in the lower capacitor electrode 50, an interlayer 53 of the total for covering surface is formed and a contact hole 53 a, 48 a 43 a having on the N + impurity implantation, a polycrystalline silicon film 54 a, which is the n⁺- impurity implantation layer 43a in the contact holes 48 a, 53 a are electrically connected and extending along extends the surface of the interlayer insulating film 53 , e a silicide film 54 b made of WSi or the like, which is formed on the polycrystalline silicon film 54 a, an interlayer insulating film 55 , which is formed on the silicide film 54 b, and aluminum wirings 56 , which are formed on the interlayer insulating film 55 at a predetermined distance from each other .

A switching MOS transistor is formed by a pair of n⁺ impurity implantation layers 43 a, 43 b, the n⁺ impurity implantation layer 44 and the gate electrode 47 . A bit line 54 for transmitting a data signal is formed from the polycrystalline silicon film 54 a and the silicide film 54 b. A stacked capacitor with the trench 41 a for storing charges corresponding to the data signal consists of the lower capacitor electrode 50 , the dielectric capacitor film 51 and the upper capacitor electrode 52 .

In the third embodiment, a trench 41 a is formed in the single crystal silicon substrate 41 , and a side wall insulating film 49 is formed on side wall portions of the trench 41 a and the interlayer insulating film 48 , so that the lower capacitor electrode 50 is only in electrical contact with the bottom region of the trench 41 a the n⁺ impurity implantation layer 44 is.

That is, in the third embodiment, the lower capacitor electrode 50 is in electrical contact with the n⁺ impurity implantation layer 44 to such a depth that the n⁺ impurity diffusion layer 45 eventually formed by impurity diffusion from the lower capacitor electrode does not overlap the area where the channel region 57 is formed. Even if the diffusion region of the n⁺- impurity diffusion layer is expanded by a heat treatment for planarization of interlayer insulating films 53, 55 45, overlapped by this structure, the n⁺-type impurity diffusion layer 45 to the channel region 57 between the n⁺- Störstellenimplantationsschichten 43 a and 43 b does not. As a result, the effective gate length is not shortened, and like the first and second embodiments, a short channel effect in which the threshold voltage drops and a penetration can be effectively prevented. Even if the position of the diffusion n⁺- impurity diffusion layer varies depending on variations in the alignment of the gate electrode 47 and the capacitor lower electrode 50 in the pattern 45, the channel length of the embodiment is further defined by the n⁺- b impurity implantation layer 43, which in self-aligning manner is formed so that the transistor properties do not fluctuate.

A manufacturing method for the DRAM according to the third embodiment will now be described with reference to FIGS. 23 to 33.

The manufacturing steps shown in FIGS. 24 to 27 correspond to those of the first embodiment, which are shown in FIGS. 4 to 7.

As shown in Fig. 28, after these steps by known lithography and dry etching, the trench 41 a and the contact hole 48 b are created in an area having a predetermined distance from the gate electrode 47 of the n + impurity implantation layer 43 b. The n⁺ impurity implantation layer 44 is formed in the side surface and the bottom surface of the trench 41 a using an oblique ion implantation method so that it has almost the same impurity concentration as the n⁺ impurity implantation layer 43 b.

As shown in Fig. 29, an oxide film 49 a with a thickness of not less than 500 Å is formed on the entire surface by the CVD method.

As shown in Fig. 30, anisotropic etching of the side wall insulating film 49 is formed only on the side wall portions of the contact hole 48 a and the trench 41 a.

As shown in FIG. 31, the lower capacitor electrode 50 is patterned after a low-resistance polycrystalline silicon layer (not shown) doped with phosphorus of 4-8 × 10 ²⁰ / cm ^{3 is} formed by the CVD method. When the lower capacitor electrode 50 is formed, a temperature of 700 ° C. is reached, so that the impurities (phosphorus) in the lower capacitor electrode 50 are thermally diffused to the single-crystal silicon substrate 41 . The n⁺ impurity diffusion layer 45 is thus formed and the n⁺ impurity implantation layer 44 and the lower capacitor electrode 50 are electrically connected.

As shown in Fig. 32, a dielectric capacitor film 51 made of a single layer such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like is formed on the lower capacitor electrode 50 . The upper capacitor electrode 52 made of a low resistance polycrystalline silicon film with almost the same impurity concentration (4-8 × 10 ²⁰ / cm ³ ) as the lower capacitor electrode 50 is formed on the dielectric capacitor film 51 by means of CVD, lithography and dry etching. The interlayer insulating film 53 is formed on the entire surface using the CVD method. To flatten the surface of the interlayer insulating film 53 , heat treatment is carried out at a temperature of 850 ° C by the reflow process.

As shown in Fig. 33, contact holes 48 a, 53 a are created in a region of the interlayer insulating films 48 and 53 on the n + impurity implantation layer 43 a. The polycrystalline silicon film 54 a is formed by means of the CVD process so that it is in electrical contact with the n-impurity implantation layer 43 a in the contact holes 48 a, 53 a and extends along the interlayer insulating film 53 . A silicide film 54 b made of WSi ₂ or the like is created on the polycrystalline silicon film 54 a using the sputtering method. The interlayer 55 wi 24308 00070 552 00004 001000280000000200012000285912419700040 0002004300357 24189rd on the silicide film 54 b formed by the CVD method. To flatten the surface of the interlayer insulating film 55 , heat treatment is carried out at a temperature of 850 ° C by the reflow process.

Finally, aluminum wirings 56 are formed at a predetermined distance from each other on the interlayer insulating film 55 , as shown in FIG. 23. This completes the DRAM according to the third embodiment.

As shown in FIG. 34, in a fourth embodiment, an insulating oxide film 62 for insulating devices in a predetermined area is formed on the main surface of a p-type silicon substrate 61 . A pair of n⁺ impurity implantation layers 63 a, 63 b is formed in a region surrounded by the insulating oxide film 62 at a predetermined distance so that a channel region 77 lies therebetween. A gate electrode 66 is formed on the channel region 77 over a gate oxide film 65 . An interlayer insulating film 67 with contact holes 67 a, 67 b is formed on the n-impurity implantation layers 63 a and 63 b, in order to cover the entire surface. A polycrystalline silicon film 68 a, which forms the bit line 68 , is created so that it is connected to the n-impurity implantation layer 63 a in the contact hole 67 a and extends on the interlayer insulating film 67 . A silicide film 68 b made of WSi ₂ or the like, which forms the bit line 68 , is created on the polycrystalline silicon film 68 a. An interlayer insulating film 69 with a contact hole 67 b, 69 a over the n + impurity implantation layer 63 b is formed to cover the silicide film 68 b. An interlayer insulating film 70 is formed with a predetermined thickness on the surface of the contact holes 67 b, 69 a. An epitaxial silicon layer 71 is created by epitaxial growth on the n + impurity implantation layer 63 b in an area surrounded by the side wall insulating film 70 . A lower capacitor electrode 72 made of a low-resistance polycrystalline silicon film with an impurity concentration (4-8 × 10 ²⁰ / cm ³ ) higher than that of the epitaxial silicon layer 71 is formed on the epitaxial silicon layer 71 by epitaxial growth. The lower capacitor electrode 72 extends on the side wall insulating film 70 and the interlayer insulating film 69 . The n⁺ impurity diffusion layer 64 is formed by thermal diffusion of the impurities contained in the lower capacitor electrode 72 in order to overlap the n⁺ impurity implantation layer 63 b. A dielectric capacitor film 73 made of a single layer such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like is formed on the lower capacitor electrode 72 . An upper capacitor electrode 74 made of a low-resistance polycrystalline silicon film with almost the same impurity concentration (4-8 × 10 ²⁰ / cm ³ ) as the lower capacitor electrode 72 is formed on the dielectric capacitor film 73 . An interlayer insulating film 75 , the surface of which is flattened, is provided on the upper capacitor electrode 74 . Aluminum wirings 76 are formed on the interlayer insulating film 75 with a predetermined distance from each other.

In the fourth embodiment, the epitaxial silicon layer 71 with an impurity concentration (1 × 10 ¹⁵ before the diffusion of the impurities in the lower capacitor electrode) is lower than that of the lower capacitor electrode 72 as in the first embodiment between the lower capacitor electrode 72 and the n⁺- Impurity implantation layer 63 b, so that the impurity diffusion in the lower capacitor electrode 72 can be reduced. This does not cause a disadvantage, so that the end portion of the n⁺ impurity diffusion layer 64 on the gate electrode 66 side is not expanded by the end portion of the n⁺ impurity implantation layer 63 b on the gate electrode 66 side, and the effective gate Long shortened. A short channel effect and penetration can be effectively prevented as in the first embodiment.

In the fourth embodiment, unlike the first embodiment shown in FIG. 1, the bit line 68 is located under the lower capacitor electrode 72 .

As shown in FIG. 35, in a DRAM according to a fifth embodiment, an insulating oxide film 82 for isolating devices in a predetermined area is formed on a p-type single crystal silicon substrate 81 . A pair of n⁺ impurity implantation layers 83 a, 83 b is formed in a region surrounded by the insulating oxide film 82 at a predetermined distance so that a channel region 97 is located therebetween. A gate electrode 86 is formed on the channel region 97 with a gate oxide film 85 therebetween. An interlayer insulating film 87 with contact holes 87 a, 87 b is formed on the n + impurity implantation layers 83 a and 83 b to cover the entire surface. A polycrystalline silicon film 88 a, which forms the bit line 88 , is created so that it is connected to the n-impurity implantation layer 83 a in the contact hole 87 a and extends on the interlayer insulating film 87 . A silicide film 88 b made of WSi ₂ or the like, which forms the bit line 88 , is created on the polycrystalline silicon film 88 a. An interlayer insulating film 89 with a flattened surface and a contact hole 89 a over the n + impurity implantation layer 83 b is formed on the silicide film 88 b. A side wall insulating film 90 is formed with a predetermined thickness on the surface of the contact holes 87 b, 89 a. A polycrystalline silicon film 91 with a high resistance and a small amount of impurities (1 × 10 ¹⁵ / cm ³ before impurities are diffused from the lower capacitor electrode 92 ) is with the n⁺ impurity implantation layer 83 b in an area surrounded by the side wall insulating film 90 , electrically connected. The high resistance polycrystalline silicon film 91 is formed so as to extend on the surface of the interlayer insulating film 90 and the surface of the interlayer insulating film 89 . A lower capacitor electrode 92 made of a low-resistance polycrystalline silicon film doped with a larger amount of impurities (phosphorus) than the polycrystalline silicon film 91 is formed on the polycrystalline silicon film 91 . A dielectric capacitor film 93 is made of a single layer such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like is formed on the lower capacitor electrode 92 . An upper capacitor electrode 94 made of a low resistance polycrystalline silicon film with almost the same impurity concentration (4-8 × 10 ²⁰ / cm ³ ) as the lower capacitor electrode 92 is formed on the dielectric capacitor film 93 . On the upper capacitor electrode 94 , an interlayer insulating film 95 with a flattened surface is created. Aluminum wirings 96 are formed on the interlayer insulating film 95 with a predetermined distance from each other.

In the fifth embodiment, like the second embodiment shown in FIG. 13, a high-resistance polycrystalline silicon film 91 having an impurity concentration (1 × 10 ¹⁵ / cm ³ before impurities are diffused from the lower capacitor electrode 92 ) is lower than that of the lower capacitor electrode 92 between the lower capacitor electrode 92 and the n⁺ impurity implantation layer 83 b, so that the diffusion of the impurities from the lower capacitor electrode 92 can be reduced. The end portion of the n⁺ impurity diffusion layer 84 , which is formed by the diffusion of impurities, on the gate electrode 86 side is not extended from the end portion of the n⁺ impurity implantation layer 83 b on the gate electrode 66 side , and therefore the effective gate length not shortened. As in the second embodiment, a short-channel effect in which the threshold voltage is reduced and a penetration can thus be effectively prevented. In the fifth embodiment, in contrast to the embodiment shown in FIG. 13, the bit line 88 is located under the lower capacitor electrode 92 .

As shown in FIG. 36, in a sixth embodiment, an insulating oxide film 102 is formed in a predetermined area of the p-type single crystal silicon substrate 101 . A trench 101 a is formed in a region of the single crystal silicon substrate 101 adjacent to the insulating oxide film 102 . An n⁺ impurity implantation layer 103 b is formed so that its end portion is in contact with a side portion of the trench 101 a. An n⁺ impurity implantation layer 103 a is formed such that the channel region 117 lies between the n⁺ impurity implantation layers 103 a and 103 b. A gate electrode 107 is formed on the channel region 117 with a gate oxide film 106 therebetween. An n⁺ impurity implantation layer 104 is created along a side wall section and a bottom surface of the trench 101 a. In the bottom region of the trench 101 a, an n⁺ impurity diffusion layer 105 is formed such that it overlaps the n⁺ impurity implantation layer 104 . An interlayer insulating film 108 with openings 108 a, 108 b is formed on the n + impurity implantation layer 103 a or the trench 101 a in order to cover the entire surface. A polycrystalline silicon film 109 a, which forms a bit line 109 , is created so that it is connected to the n-impurity implantation layer 103 a in the contact hole 108 a and extends along the interlayer insulating film 108 . A silicide film 109 b made of WSi ₂ or the like, which forms the bit line 109 , is created on the polycrystalline silicon film 109 a. On the silicide film 88 b, an interlayer insulating film 110 is formed with a leveled surface and a contact hole 110 a over the trench 101 a. A side wall insulating film 111 is formed with a predetermined thickness on the side wall portion of the trench and the surfaces of the contact holes 108 b, 110 a. A lower capacitor electrode 112 is formed electrically with the n + impurity implantation layer 104 in the bottom region of the trench 101 a within a section which is surrounded by the side wall insulating film 111 . The lower capacitor electrode 112 is formed of a low-resistance polycrystalline silicon film doped with a large amount of impurities (phosphorus) (4-8 × 10 ²⁰ / cm ³ ).

A dielectric capacitor film 113 is made of a single layer such as. B. a thermal oxide film, a multilayer film with a structure of z. B. a silicon oxide film / a silicon nitride film / a silicon oxide film or Ta ₂ O ₅ or the like is formed on the lower capacitor electrode 112 . An upper capacitor electrode 114 made of a low resistance polycrystalline silicon film having almost the same impurity concentration (4-8 × 10 ²⁰ / cm ³ ) as the lower capacitor electrode 112 is formed on the dielectric capacitor film 113 . On the upper capacitor electrode 114 , an interlayer insulating film 115 with a flattened surface is created. Aluminum wirings 116 are formed on the interlayer insulating film 115 with a predetermined distance from each other.

In the sixth embodiment, as in the third embodiment shown in FIG. 23, the lower capacitor electrode 112 is in contact with the n + impurity implantation layer 104 only in the bottom portion of the trench 101 a. Therefore, although the diffusion area of the n⁺ impurity diffusion layer 105 formed by thermal diffusion of impurities (phosphorus) in the lower capacitor electrode 112 is enlarged, the n⁺ impurity diffusion layer 105 does not overlap the channel region 117 between the n⁺ impurity implantation layers 103 a and 103 b. As in the third embodiment, the channel length is not shortened and a short channel effect and crackdown can be effectively prevented. In the sixth embodiment, in contrast to the third embodiment shown in FIG. 23, the bit line 109 is located under the lower capacitor electrode 112 .

Fig. 37 shows a cross-section of the structure of a DRAM having a stacked capacitor according to the seventh embodiment of the present invention. As shown in FIG. 37, in the seventh embodiment, an epitaxial silicon layer 208 is formed on a contact portion of the bit line 13 to a single crystal silicon substrate 1 , and not on a contact portion of the DRAM shown in FIG. 1 according to the first embodiment lower capacitor electrode 9 . This means that through the epitaxial silicon layer 208 between the polycrystalline silicon film 13 a, which forms the bit line 13 , and the n⁺ impurity diffusion layer 204 , which is formed by thermal diffusion from the polycrystalline silicon film 13 a, the diffusion of impurities in the polycrystalline silicon film 13 a is reduced to the single-crystal silicon substrate 1 by a heat treatment. This leads to a reduction in the degree of diffusion of the n⁺ impurity diffusion layer 204 , even if e.g. B. is carried out a heat treatment at about 850 ° C to level the interlayer insulating film 14 or the like. This effectively prevents the end portion of the n⁺ impurity diffusion layer 204 on the gate electrode 6 side from being expanded from the end portion of the n⁺ impurity implantation layer 3 b on the gate electrode 6 side. This makes it possible to effectively prevent a short channel effect without shortening the length of the channel region 16 .

Accordingly, the semiconductor device is located in the present invention a first conductive layer with a lower impurity concentration than that of a second conductive one Layer between the second conductive layer and one with it connected first impurity area so that impurities in the second conductive layer can be prevented by thermal Diffuse to diffuse into the semiconductor substrate. Even if then a heat treatment is carried out, the Diffusion of the impurities in the second conductive layer in the Heat treatment can be reduced. Therefore, it effectively prevents that an end portion of a third impurity region, the is finally formed on the side of the gate electrode an end portion of the first impurity region on the side of the Gate electrode expanded. This does not make the effective gate length shortened, and a short channel effect and a penetration can be effective can be prevented at which the threshold voltage is reduced. Even if there are fluctuations in the alignment of the gate electrode and the second conductive layer when patterning occurs is expanded the third impurity region does not differ from the end section of the second impurity region on the gate electrode side, and Fluctuations in transistor properties can also be effective be prevented.  

In another embodiment of the present invention a second impurity area along the side wall and the Bottom surface of a recessed section in the main surface of the Semiconductor substrate is formed, a side wall insulating film is formed on the second impurity area on the side wall of the recessed Section created, and the second impurity area and the second conductive layer are recessed in the bottom area Section electrically connected. This effectively prevents the third impurity region caused by thermal diffusion of Impurities in the second conductive layer from the bottom portion of the recessed area is formed, a channel area between the first impurity region and the second impurity region overlaps. This does not shorten the channel length, and one Short channel effect and penetration can be effectively prevented.

According to another aspect of the present invention, a second impurity region along the surface of a side wall and the bottom of a recessed portion that is in one predetermined area in the main surface of the semiconductor substrate is formed, created a sidewall diffusion reduction film is on the second impurity area on the side wall of the recessed section created, and the second impurity area is electrically recessed with a conductive layer at the bottom of the Section connected. This effectively prevents a third Impurity area caused by thermal diffusion of impurities in the second conductive layer from the bottom portion of the recessed Area is formed, a channel area between a first Impurity area and the second impurity area overlap. The leads to an effective prevention of a short channel effect and a penetration without reducing the channel length.

In the manufacturing method for a semiconductor device according to present invention, a first conductive layer on a created the first impurity area with which a second conductive Is connected to a second conductive layer with a layer Impurity concentration higher than that of the first conductive layer  is formed on the first conductive layer, and a third Impurity area is caused by thermal diffusion of the impurities created, which are contained in the second conductive layer. This allows the diffusion of the impurities in the second conductive Layer can be reduced so that the impurities in the second conductive layer can be effectively prevented from continuing into the Diffuse semiconductor substrate. This expands End portion of the third impurity region on the gate side Electrode not from an end portion of the first Impurity area on the side of the gate electrode, and therefore can can be effectively prevented from reducing the effective gate length becomes.

In another manufacturing process for a The semiconductor device of the present invention is disclosed in the Main surface of a semiconductor substrate in a predetermined one A recessed section from a first impurity region created, a second impurity area is along the Main surface of the recessed portion is formed Sidewall insulation film is recessed on the sidewall of the Section created, and a conductive layer is formed, the electrically connected to the bottom portion of the recessed portion and extends along an interlayer insulating film. So that the conductive layer is recessed only in the bottom section Section connected to the second impurity area. Even if the diffusion area of the impurity area caused by thermal Diffusion is created by the subsequent heat treatment is expanded, it can be effectively prevented that the Impurity area overlaps with the channel area. With that the effective gate length not shortened, and a short channel effect and a Penetration can be effectively prevented.

According to a further aspect of the present invention, in Main surface of a semiconductor substrate in a predetermined one A recessed section from a first impurity region created, a second impurity area is along the Main surface of the recessed portion formed, a side wall  Diffusion reduction film is recessed on a side wall of the Section created a conductive layer with a predetermined Amount of impurities is formed so that it is with the bottom of the recessed portion is in electrical contact and along an interlayer insulating film, and a third Impurity area is caused by thermal diffusion of the impurities created in the conductive layer.

The conductive layer is thus connected to the second Impurity area only in the bottom section of the recessed section. Even if the diffusion area of the third Impurity area by a subsequent one Heat treatment step extended, can thus be effectively prevented that the third impurity area is a channel area overlaps. This effectively prevents one Short channel effect and a penetration without the effective gate Shorten length.

Claims (31)

1. Semiconductor device, characterized by
a semiconductor substrate ( 1 , 21 ) of a first conductivity type with a main surface,
a first and a second impurity region ( 3 a, 23 a, 3 b, 23 b) of a second conductivity type, which are formed at a distance from one another on the main surface of the semiconductor substrate on opposite sides of a channel region ( 16 , 36 ) enclosed between them,
a third impurity region ( 4 , 24 ) of the second conductivity type formed in the first impurity region, a gate electrode ( 6 , 26 ) formed on the channel region with a gate insulating film ( 5 , 25 ) therebetween, a first conductive layer ( 8 , 28 ) formed on the first and third impurity regions, and
a second conductive layer ( 9 , 29 ) formed on the first conductive layer and having predetermined impurities, the impurity concentration of the first conductive layer being lower than that of the second conductive layer. 2. Semiconductor device according to claim 1, characterized in that that the second conductive layer has a lower capacitor electrode forms. 3. A semiconductor device according to claim 1 or 2, characterized characterized in that the first conductive layer comprises silicon. 4. Semiconductor device according to claim 3, characterized in that the first conductive layer has an epitaxially grown silicon layer ( 8 ). 5. A semiconductor device according to claim 3, characterized in that the first conductive layer has a polycrystalline silicon layer ( 28 ). 6. Semiconductor device according to one of claims 2 to 5, characterized in that
an upper capacitor electrode ( 11 ) is formed on the lower capacitor electrode ( 9 ) with a capacitor insulating layer ( 10 ) in between,
a bit line ( 13 ) is connected to the second impurity region, and
the bit line is formed such that it extends on the upper capacitor electrode with a first intermediate insulating layer ( 12 ) in between. 7. A semiconductor device according to claim 6, characterized in that a wiring layer ( 15 ) is formed on the bit line with a second intermediate insulating layer ( 14 ) therebetween. 8. Semiconductor device according to one of claims 2 to 5, characterized in that
an upper capacitor electrode ( 74 , 94 ) is formed on the lower capacitor electrode ( 72 , 92 ) with a capacitor insulating layer ( 73 , 93 ) in between,
a bit line ( 68 , 88 ) is connected to the second impurity region ( 63 a, 83 a), and
the bit line is formed so that it extends under the lower capacitor electrode with a first intermediate insulating layer ( 69 , 89 ) therebetween. 9. A semiconductor device according to claim 8, characterized in that a wiring layer ( 76 , 96 ) on the upper capacitor electrode ( 74 , 94 ) with a second intermediate insulating layer ( 75 , 95 ) is formed therebetween. 10. Semiconductor device, characterized by
a semiconductor substrate ( 41 , 101 ) of a first conductivity type with a main surface and a recessed section ( 41 a, 101 a) in a predetermined area of the main surface,
a first impurity region ( 43 a, 103 a) of a second conductivity type, which is formed in a predetermined region on the main surface of the semiconductor substrate,
a second impurity region ( 43 b, 44 , 103 b, 104 ) of the second conductivity type which is formed along the surface of the recessed portion of the semiconductor substrate and is at a distance from the first impurity region so that a channel region ( 57 , 117 ) lies between them,
a gate electrode ( 47 , 107 ) formed on the channel region with a gate insulating film ( 46 , 106 ) therebetween,
a sidewall insulating film ( 49 , 111 ) formed on the second impurity region in a sidewall of the recessed portion, and
a conductive layer ( 50 , 112 ) bonded to the second impurity region at the bottom of the recessed region and extending along the sidewall insulating film. 11. The semiconductor device according to claim 10, characterized in that that the conductive layer forms a lower capacitor electrode. 12. A semiconductor device according to claim 11, characterized in that
an upper capacitor electrode ( 52 ) is formed on the lower capacitor electrode ( 50 ) with a capacitor insulating layer ( 51 ) therebetween,
a bit line ( 54 ) is connected to the second impurity region, and
the bit line is formed to extend on the upper capacitor electrode with a first intermediate insulating layer ( 53 ) therebetween. 13. A semiconductor device according to claim 12, characterized in that a wiring layer ( 56 ) is formed on the bit line with a second intermediate insulating layer ( 55 ) therebetween. 14. A semiconductor device according to claim 11, characterized in that
an upper capacitor electrode ( 114 ) is formed on the lower capacitor electrode ( 112 ) with a capacitor insulating layer ( 113 ) therebetween,
a bit line ( 109 ) is connected to the second impurity region ( 103 a), and
the bit line is formed to extend under the lower capacitor electrode with a first intermediate insulating layer ( 110 ) therebetween. 15. The semiconductor device according to claim 14, characterized in that a wiring layer ( 116 ) is formed on the upper capacitor electrode ( 114 ) with a second intermediate insulating layer ( 115 ) therebetween. 16. Semiconductor device, characterized by
a semiconductor substrate ( 41 , 101 ) of a first conductivity type with a main surface and a recessed section ( 41 a, 101 a) in a predetermined area of the main surface,
a first impurity region ( 43 a, 103 a) of a second conductivity type, which is formed in a predetermined region on the main surface of the semiconductor substrate,
a second impurity region ( 43 b, 44 , 103 b, 104 ) of the second conductivity type formed along the surface of the recessed portion of the semiconductor substrate to enclose a channel region ( 57 , 117 ) at a predetermined distance from the first and impurity region,
a third impurity region ( 45 , 105 ) of the second conductivity type, which is formed so as to overlap the second impurity region in the bottom surface of the recessed portion of the semiconductor substrate,
a gate electrode ( 47 , 107 ) formed on the channel region with a gate insulating film ( 46 , 106 ) therebetween,
a sidewall diffusion reduction film ( 49 , 111 ) formed on the second impurity region in the sidewall of the recessed portion, and
a conductive layer ( 50 , 112 ) having predetermined impurities bonded to the second and third impurity regions at the bottom of the recessed region and formed along the sidewall diffusion reduction film. 17. The semiconductor device according to claim 16, characterized in that that the conductive layer forms a lower capacitor electrode. 18. Manufacturing method for a semiconductor device, characterized by the steps:
Forming a gate electrode ( 6 , 26 ) on a main surface of a semiconductor substrate ( 1 , 21 ) of a first conductivity type with a gate insulating film ( 5 , 25 ) therebetween,
Forming a first and a second impurity region ( 3 a, 23 a, 3 b, 23 b) of a second conductivity type by incorporating impurities,
Forming an insulating layer ( 7 , 27 ) with an opening ( 7 b, 27 b) on the first impurity region ( 3 b, 23 b),
Forming a first conductive layer ( 8 , 28 ) on the first impurity region within the opening,
Forming a second conductive layer ( 9 , 29 ) with a higher impurity concentration than that of the first conductive layer on the first conductive layer, and
Forming a third impurity region ( 4 , 24 ) of the second conductivity type by thermal diffusion of the impurities in the lower capacitor electrode to the semiconductor substrate through the first conductive layer. 19. Manufacturing method according to claim 18, characterized in that the second conductive layer has a lower capacitor electrode forms.   20. The manufacturing method according to claim 18 or 19, characterized in that the step of forming the first conductive layer comprises the step of forming a first conductive layer ( 8 , 28 ) with an impurity concentration of approximately 1 × 10 ¹⁵ / cm ³ and a thickness of about 0.2µm. 21. Preparation process according to any one of claims 18 to 20, characterized in that the first conductive layer (8) comprises an epitaxial silicon layer (8) is formed by epitaxial growth on the main surface of the semiconductor substrate where the first impurity region is formed. 22. The production method according to claim 21, characterized in that that the epitaxial silicon layer at 700 ° C for several tens Minutes grows. 23. Manufacturing method according to claim 18, characterized in that the first conductive layer has a polycrystalline silicon layer ( 28 ). 24. Manufacturing method according to claim 23, characterized in that that the polycrystalline silicon layer is formed by patterns, after the polycrystalline silicon layer on the first Impurity region and a second conductive layer on the polycrystalline silicon layer have been formed. 25. Manufacturing method for a semiconductor device, characterized by the steps:
Forming a gate electrode ( 47 , 107 ) on a main surface of a semiconductor substrate ( 41 , 101 ) of a first conductivity type with a gate insulating film ( 46 , 106 ) therebetween,
Forming a first impurity region ( 43 a, 103 a) of a second conductivity type by embedding impurities,
Forming a recessed section ( 41 a, 101 a) on the main surface of the semiconductor substrate at a distance from the first impurity region,
Forming a second impurity region ( 44 , 104 ) of the second conductivity type along the main surface of the recessed portion,
Forming a sidewall insulating film ( 49 , 111 ) in a sidewall portion of the recessed portion, and
Forming a conductive layer ( 50 , 112 ) electrically connected to the bottom portion of the recessed portion and extending along the side wall insulating film. 26. Manufacturing method for a semiconductor device, characterized by the steps:
Forming a gate electrode ( 47 , 107 ) on a main surface of a semiconductor substrate ( 41 , 101 ) of a first conductivity type with a gate insulating film ( 46 , 106 ) therebetween,
Forming a first impurity region ( 43 a, 103 a) of a second conductivity type by embedding impurities,
Forming a recessed section ( 41 a, 101 a) on the main surface of the semiconductor substrate at a distance from the first impurity region,
Forming a second impurity region ( 44 , 104 ) of the second conductivity type along the main surface of the recessed portion,
Forming a sidewall diffusion reduction film ( 49 , 111 ) in a sidewall portion of the recessed portion,
Forming a conductive layer ( 50 , 112 ) with predetermined impurities electrically connected to the bottom of the recessed portion and extending along the sidewall diffusion reducing film, and
Forming a third impurity region ( 45 , 105 ) by thermal diffusion of impurities in the conductive layer in the bottom portion of the recessed portion. 27. The production method according to claim 26, characterized in that that the bottom portion of the recessed portion in one is such a depth that the third impurity region is deeper than the channel area between the first and second impurity area is formed.   28. Semiconductor device, characterized by
a semiconductor substrate ( 1 , 21 ) of a first conductivity type with a main surface,
a first and a second impurity region ( 3 a, 23 a, 3 b, 23 b) of a second conductivity type, which are formed on the main surface of the semiconductor substrate such that they enclose a channel region ( 16 , 36 ) with a predetermined width,
a third impurity region ( 4 , 24 ) of the second conductivity type overlapping the first impurity region, a gate electrode ( 6 , 26 ) formed on the channel region with a gate insulating film therebetween,
a first insulating layer ( 7 , 27 ) which is formed to cover the gate electrode and has first and second openings on the first and second impurity regions,
a conductive layer ( 8 , 28 ) with impurities, which is connected to the first and third impurity regions within the first opening,
a capacitor consisting of a lower capacitor electrode ( 9 , 29 ) having impurities and extending along the first insulating layer on the conductive layer and an upper capacitor electrode ( 11 , 31 ) thereon with a capacitor insulating film ( 10 , 30 ) therebetween is formed, is created,
a second insulating layer ( 12 , 32 ) which is formed to cover the upper capacitor electrode and has a third opening on the second opening,
a bit line ( 13 , 33 ) electrically connected to the second impurity region within the second and third openings and extending along the second insulating layer, a third insulating layer ( 14 , 34 ) formed on the bit line, and
a wiring layer formed on the third insulating layer, the impurity concentration of the conductive layer being lower than that of the lower capacitor electrode. 29. Semiconductor device, characterized by
a semiconductor substrate ( 41 ) of a first conductivity type with a main surface and a recessed section ( 41 a) in a predetermined area of the main surface,
a first impurity region ( 43 a) of a second conductivity type, which is formed in a predetermined region on the main surface of the semiconductor substrate,
a second impurity region ( 44 ) of the second conductivity type formed along the surface of the recessed portion of the semiconductor substrate and including a channel region ( 57 ) at a predetermined distance therefrom from the first impurity region,
a third impurity region ( 45 ) of the second conductivity type, which is formed to overlap the second impurity region in the bottom surface of the recessed portion of the semiconductor substrate,
a gate electrode ( 47 ) formed on the channel region with a gate insulating film ( 46 ) therebetween,
a first insulating layer ( 48 ) which is formed to cover the gate electrode and has a first and second opening ( 48 a, 48 b) on the first and second impurity regions,
a side wall insulating film ( 49 ) formed on the second impurity region in a side wall of the recessed portion and on a surface of the second opening ( 48 b),
a capacitor consisting of a lower capacitor electrode ( 50 ) connected to the second and third impurity regions in a bottom portion of the recessed portion and extending along the side wall insulating film and the third insulating layer, and an upper capacitor electrode ( 52 ) thereon is formed with a capacitor insulating film ( 51 ) therebetween,
a second insulating layer ( 53 ) which is formed to cover the upper capacitor electrode and has a third opening ( 53 a) on the first opening ( 48 a),
a bit line ( 54 ) which is electrically connected to the second impurity region within the first ( 48 a) and third opening ( 53 a) and extends along the second insulating layer,
a third insulating layer ( 55 ) formed on the bit line, and
a wiring layer ( 56 ) formed on the third insulating layer. 30. Semiconductor device, characterized by
a semiconductor substrate ( 61 , 81 ) of a first conductivity type with a main surface,
a first and a second impurity region ( 63 a, 83 a, 63 b, 83 b) of a second conductivity type, which are formed on the main surface of the semiconductor substrate such that they enclose a channel region ( 77 , 97 ) with a predetermined width,
a third impurity region ( 64 , 84 ) of the second conductivity type overlapping the first impurity region, a gate electrode ( 66 , 86 ) formed on the channel region with a gate insulating film ( 65 , 85 ) therebetween,
a first insulating layer ( 67 , 87 ), which is formed to cover the gate electrode and has a first ( 67 b, 87 b) and second opening ( 67 a, 87 a) on the first and second impurity region, a bit line ( 68 , 88 ), which is electrically connected to the second impurity region ( 63 a, 83 ) within the second opening ( 67 a, 87 a) and extends along the first insulating layer ( 67 , 87 ),
a third insulating layer ( 69 , 89 ) which is formed on the bit line and has a third opening ( 69 a, 89 a) on the first opening ( 67 b, 87 b),
a side wall insulating film ( 70 , 90 ) formed with a predetermined thickness on the surface of the first opening ( 67 b, 87 b) and the third opening ( 69 a, 89 a),
a conductive layer ( 71 , 91 ) with impurities connected to the first and third impurity regions within a region surrounded by the side wall insulating film,
a capacitor consisting of a lower capacitor electrode ( 72 , 92 ) extending along the side wall insulating film and the second insulating layer on the conductive layer, and an upper capacitor electrode ( 74 , 94 ) thereon with a capacitor insulating film ( 73 , 93 ) is formed in between, is created,
a third insulating layer ( 75 , 95 ) formed on the upper capacitor electrode, and
a wiring layer ( 76 , 96 ) formed on the third insulating layer, the impurity concentration of the conductive layer being lower than that of the lower capacitor electrode. 31. Semiconductor device, characterized by
a semiconductor substrate ( 41 ) of a first conductivity type with a main surface and a recessed section ( 102 a) in a predetermined area of the main surface,
a first impurity region ( 103 a) of a second conductivity type, which is formed in a predetermined region on the main surface of the semiconductor substrate,
a second impurity region ( 104 ) of the second conductivity type, which is formed along the surface of the recessed portion of the semiconductor substrate and includes a channel region ( 117 ) at a predetermined distance from the first impurity region,
a third impurity region ( 105 ) of the second conductivity type, which is formed to overlap the second impurity region in the bottom surface of the recessed portion of the semiconductor substrate,
a gate electrode ( 107 ) formed on the channel region with a gate insulating film ( 106 ) therebetween,
a first insulating layer ( 108 ) which is formed to cover the gate electrode and has a first and second opening ( 108 a, 108 b) on the first impurity region or the recessed section,
a bit line ( 109 ) which is electrically connected to the first impurity region ( 103 a) within the first opening ( 108 a) and extends along the first insulating layer,
a second insulating layer ( 110 ) which is formed on the bit line and has a third opening ( 110 a) on the second opening,
a side wall insulating film ( 110 ) formed with a predetermined thickness on the surfaces of the recessed portion ( 101 a), the second opening ( 108 b) and the third opening ( 110 a),
a capacitor composed of a lower capacitor electrode ( 112 ) connected to the first and third impurity regions in a bottom portion of the recessed portion within an area surrounded by the side wall insulating film and along the side wall insulating film and the third insulating layer and an upper capacitor electrode ( 114 ) formed thereon with a capacitor insulating film ( 113 ) therebetween,
a third insulating layer ( 115 ) formed to cover the upper capacitor electrode, and
a wiring layer ( 56 ) formed on the third insulating layer.