DE4416881A1 - Data processing device - Google Patents

Abstract

An integrated circuit chip carries a number of mutually-orthogonal homogeneously-structured cells, each with a number of logically and structurally-identical components. The cells are combined in rows and columns, possibly also in groups, for connection to chip input/output connections. A charging logic is associated with the cells, via which they can be programmed individually and in groups so that optional logical functions and/or networks can be verified. Manipulation of the data flow processor chip's configuration, i.e. the modification of functional parts or macros can be performed during operation without stopping other functional parts or adversely affecting their functioning.

Description

The present invention relates to a data processing equipment, d. H. a hardware unit for logical manipulation (linking) of in binary form available data (information).

Such data processing devices are meanwhile long known and they already have wide application and Recognition found. The basic structure and work structure of the known data processing equipment is something like that to define an arithmetic-logical Linking unit is provided, in which the link fenden data of a program statement (software) According to be processed. The data is about a Control unit in more or less complex addressing processes are called accordingly and first in working provided with registers; after the logical link then the new data will be in a given memory filed again. The arithmetic-logic link Fung unit consists of logical link construction stones (gates, limbs), each with each other ge Coupled are that the data to be manipulated on the basis lying software according to the four basic operations be processed logically.

It is easy to understand that on the basis of be Structures needed a relatively large amount of computing time  It is necessary to read the data to be manipulated and the To transfer work registers, the specific logic building stones in the arithmetic-logical linking unit zuzuleiten and finally save again. It is further, that the hardware structure of arith metic-logical linking unit insofar not as optimally considered, as finally the hard according to existing integrated logic components always in one and the same way in the whole system be actively used. Likewise is by strict Hardware preset a stringing of functions in so-called pipelines very difficult or restricted, which inevitably involves frequent reloading between Working registers and arithmetic means. Such construction stones are furthermore poorly cascadable and he then require a lot of programming work.

An additional advantage of the present invention is in that a parallel over a wide space scalable parallel quality is available. This will be a basis for fast and flexible construction of neural structures created, as the hitherto only with considerable Auf wall can be simulated.

The object underlying the present invention consists of using one in the following flow processor (DFP) to specify said data processing device, in the a higher or better flexibility of the Forest structure and data flow as well as pipelining and cascading possibilities to increase the computers or linking power leads.

In addition to the use as a pure data flow processor, the DFP can perform the following additional tasks:

• - Use as a universal building block for the construction of her conventional computers, the structure easier and to become cheaper.
• - Use in neural networks.

This object is achieved in that an integrated circuit (chip) is provided with a plurality of particular ortho gonal to each other arranged cells each having a plurality of logically identical and structurally identical angeord Neter cells whose arrangement, and the internal bus structure to facilitate programming extremely is homogeneous. Nevertheless, within a data flow processor, it is conceivable to accommodate cells with different cell logics and cell structures so as to increase performance by, for example, having cells other than arithmetic operations for memory drives. In particular, a certain specialization may be advantageous for neural networks. The cells are assigned a Ladelo gik over which the cells are grouped together in groups and so called in so-called MACROs so programmable so that on the one hand any logical functions, but on the other hand, the combination of cells with each other are verifiable in a wide range. This is achieved by providing each cell with a certain storage space in which the configuration data are stored. Based on these data multiplexer or transistors in the cell be switched to the respective cell function to ensure (see Fig. 12).

With other than in claim 1 used words the core of the present invention is a To propose data flow processor that is cellular and its cells via an external charging logic in the arith metic-logical sense virtually arbitrarily reconfigured can be. It is of utmost necessity  that the lines concerned individually and without interference the rest of the lines or even a shutdown of the whole Modules can be reconfigured. The data flow Processor according to the present invention can thus during a first cycle as an adder and during a later work cycle as a multiplier "per be grammed, with the number of additions or the multiplication required cells can be quite different. The Pla receive the already loaded MACROs; the ark logic or the compiler, it is up to the new loading MACRO within the free cells to partition (ie to decompose the MACRO to be loaded so that it is optimally insert). The flow control of the program is taken over by the charging logic, in accordance with the currently running program section the corre sponding The MACROs load into the device while charging Mitge mitge from the synchronization logic described later is controlled by determining the time of reloading sets. Therefore, the DFP does not comply with the known Neumann architecture, since the data and program memory are separated. However, this means a height at the same time re security, because programs with no code, son They can only destroy DATA.

To make the flow processor a workable structure give, some cells, including the Input / output functions (I / O) and memory management functions are loaded and remain before loading the programs usually constant throughout the run. This is required to the data flow processor to its hard ware environment. The remaining cells become soge called MACROs summarized and can be used during the run time almost arbitrarily and without influencing the neighbor cells are reconfigured. These are the cells individually and directly addressable.  

To restructure (reload) the cells or Synchronizing MACROs with the charging logic can - where necessary, since only reloading is allowed, if the MACROs finished with their old activity - a synchronisa tion as MACRO on the data flow processor under be brought to the corresponding signals to the Charge logic sends off. This may possibly be a modification of the ordinary MACROs be necessary, since these then the Synchronization circuit Status information for Ver need to provide.

This state information usually signals the synchronization logic that individual MACROs have done their job, which from a programming point of view can mean, for example, the termination of a procedure or the achievement of the termination condition of a loop. This means that the program will be continued at another location and the MACROs sending the status information can be reloaded. In addition, it may be of interest that the MACROs are reloaded in a particular order. For this purpose, an evaluation of the individual synchronization signals can be carried out by a priority decoder. One of the - simple - logic is drawn in Fig. 13. The logic has seven input signals through which the seven MACROs output their status information. In this case, 0 stands for "in progress" and 1 for "finished". The logic has three output signals, which are fed to the charging logic, the state 000 is considered to be at rest. If a signal is present at one of the seven inputs, then a decimal-to-binary conversion takes place, for example, Sync6 is represented as 110, which indicates to the load logic that the MACRO serving Sync6 has completed its task. If several synchronization signals are present at the same time at the input, the synchronization circuit forwards the signal with the highest priority to the charging logic; If, for example, Sync0, Sync4 and Sync6 are applied, then the syncronisation circuit first passes Sync6 to the loading logic. After the corresponding MACROs are reloaded and thus Sync6 is no longer present, Sync4 is passed on, etc. To illustrate this principle, the standard TTL module 74148 can be considered.

About the loading logic of the data flow processor can each optimal and possibly dynamic to be solved Task be set. This is for example the Great advantage associated with new standards or the like solely by reprogramming the data Flow processors can be implemented and not - like so far - an exchange with appropriate fit of Electronic waste condition.

The data flow processors can be cascaded with one another, what an almost arbitrary increase of the parallelism degree of efficiency, the computing power, as well as the network size in neural networks. Especially important here is one clear homogeneous connection of the cells with the on / off gangs-pins (IO-Pin) of the data flow processors, if possible have no restrictions on the programs.

For example, FIG. 14 shows the cascading of four DFPs. They appear to the environment like a large homogeneous building block ( Fig. 15). In principle, two methods of kadening are conceivable:

• a) Only the local connections between the cells are led out, which in the present example, two IO pins per edge cell and four IO pins per corner cell be. However, the compiler / programmer has to keep in mind that the global connections are not routed out, which means that the cascading is not completely homogeneous. (Global connections between multiple cells, usually between a complete cell row or column - see Fig. 6 - Local links exist only between two cells). Fig. 16a shows the structure within a DFP, Fig. 17a shows the resulting cascading of several DFPs (three drawn).
• b) The local and global connections are out led what the number of required drivers / IO pins and lines increased dramatically, in our example six IO pins per edge cell and twelve IO pins per Corner cell. This ensures complete homogeneity given the cascading.

Since the global connections can become very long, in particular when using the cascading technique b), the unpleasant effect can occur that the number of global connections is insufficient, since it is known that each connection can only be used by one signal. To minimize this effect, a driver can be inserted after a certain length of the global connections. The driver has on the one hand an amplification of the signal to task, which is absolutely necessary for long distances and correspondingly high loads; on the other hand, the driver can go into Tristate and thus interrupt the signal. As a result, the sections on the left and right, or above and below the driver of different signals can be used, if the driver is in Tristate, otherwise a signal is looped through. It is important here that the drivers of the individual global lines can also be controlled individually, ie a global signal can be interrupted, but the neighboring signal is looped through. Thus, various signals can be present in sections on a global connection, while the global neighboring connection is actually used globally by one and the same signal (see FIG. 22).

For better communication between the data flow processors and the charging logic can use so-called shared Memories are used. For example, Pro gramme from a hard disk in the IO area of a data flow processor is passed to the charging logic, by the data flow processors the data from the disk in write the shared memory and the charging logic write them off get. This is especially important because here, as he already did not a von Neumann but a Harvard architecture is present. Similarly, the shared memories are beneficial if Constants that are in the program - that in the memory area of Loading logic is - defined, with data - in the Memory operation of the data flow processors are linked should be.

Further developments of the above defined and rewritten nen invention are the subject of the dependent claims.

A particular use of the data according to the invention Flux processor is to be seen in that he is in connection with suitable input / output units on the one hand and a Memory on the other hand, the basis for a complete (com plexen) can form computers. Here, a large part of the IO functions as MACROs on the data flow processor are implemented and currently only need it Special modules (Ethernet driver, VRAMS ...) supplied externally to be added. For a standard change or improvement must then, as already indicated only the MACRO softwaresei be changed; is an intervention in the hardware unnecessary. It makes sense here, an IO- (Ein input / output) plug on which then the additional modules can be connected.

Fig. 20 shows the much simplified structure of a computer today. Considerable parts can be saved by using a DFP module ( Figure 21), with the corresponding conventional modules (CPU, memory management, SCSI, keyboard and video interface, as well as the parallel and serial interfaces) being MACROs in the cascaded DFPs be filed. Only parts that can not be replicated by a DFP, such as memory and line drivers with non-TTL levels or for high loads, must be switched externally. By using the DFPs a favorable production is given, since one and the same building block is used very frequently, the layout of the board is correspondingly simple due to the homogenous networking. In addition, the structure of the computer is determined by the charging logic, which here usually only at the beginning of the processing (after a reset) loads the DFP array, whereby a favorable error correction and expansion option is given. Such a computer can in particular simulate several different computer structures by simply loading the structure of the computer to be simulated into the DFP array. It should be noted that in this case the DFP does not work in its function as a DFP but merely provides a highly complex and freely programmable logic array, but in this case differs from conventional components in its particular good cascadability.

Another application of the device is the structure large neural networks. Its special advantage lies here at in its high gate density, its excellent Cascadability, as well as its homogeneity. A learning advance a change of single axiomatic verbin ments or individual cell functions is just as bad to perform on common building blocks, like building large homogeneous and at the same time more flexible Cell structures. The dynamic reconfigurability made possible For the first time the optimal simulation of learning processes.

The present invention will be described below with reference to FIGS further figures explained in more detail. Overall show  

Fig. 1 is a circuit symbol for an 8-bit adder;

FIG. 2 is a circuit diagram for an eight-bit adder consisting of eight 1-bit adders as shown in FIG. 1; FIG.

Fig. 3 is a logical structure of a 1-bit adder according to Fig. 2;

FIG. 4 shows a cell structure of the 1-bit adder according to FIG. 3; FIG.

FIG. 5 shows an 8-bit adder constructed in accordance with the cell structure of FIG. 1; FIG.

Fig. 6 is an existing four-cell unprogrammed SUBMACRO X (analogous to a 1-bit adder of FIG 4 or FIG. 5.) With the erforder handy lead terminals;

Fig. 7 is a partial section of an integrated circuit (chip) having a plurality of cells and a separated SUBMACRO X of FIG. 6;

Fig. 8 is an integrated circuit (chip) having a Orthogonalstruktur a quasi any plurality of cells and an externally associated load logic;

Fig. 9 shows a first embodiment of a plurality with each other to an arithmetic unit coupled integrated circuits (Data flow) of Fig. 8;

Fig. 10 shows a second embodiment of a plurality with each other to an arithmetic unit coupled integrated circuits (Data flow) of Fig. 8;

Figure 11 is an embodiment of a MACRO for the addition of two number series.

Fig. 12 shows an exemplary structure of a cell with multiplexers for selecting the respective logical components;

Fig. 13 shows a synchronization logic implemented, for example, with a standard TTL module 74148;

Figure 14 shows the cascading of four DFPs, with the connection between the IO pins only schematically illustrated (in fact, a signed connection means a plurality of lines);

Fig. 15 shows the homogeneity achieved by cascading;

FIG. 16a, the structure of the I / O cells, said global connections are not drawn out,

FIG. 16b shows the structure of the I / O cells but with global connections taken out; FIG.

Fig. 17a resulting from Fig. 16a cascading, where at a corner cell, as well as the two kommu ning with them driving cells of the cascaded construction stones (see Fig. 14) are drawn;

Fig. 17b resulting from Fig. 16b cascading, where at a corner cell, as well as the two Kommu ning with them driver cells of the cascaded construction stones (see Fig. 14) are drawn;

Fig. 18a shows a multiplication circuit (see Fig. 11a);

Fig. 18b shows the internal structure of the DFP after loading (see Fig. 11b);

Fig. 19c shows the operation of the DFP in memory, as well as the states of the counters 47 , 49 ;

FIG. 19 shows a cascade circuit, wherein the adder from FIG. 11 and the multiplier from FIG. 18 are connected one behind the other to increase the computing power; FIG.

FIG. 20 shows the highly schematic structure of a conventional computer; FIG.

21 shows the possible structure of the same computer with the aid of an array of cascaded DFPs.

FIG. 22 shows a section with drawn (line) drivers of a DFP.

In Fig. 1 is a switching symbol of an 8-bit adder Darge presents. The switching symbol consists of a square block 1 with eight inputs A 0. , , 7 for a first data word A and eight inputs B 0. , , 7 for a second (to be added) data word B. The eight inputs Ai, Bi are supplemented by a further input Uein via the block 1, if necessary, a carry is supplied. The function block 1 has functionally and correctly eight outputs S 0. , , 7 for binary summands and a further output Oaus for the possibly existing carry.

The switching symbol shown in FIG. 1 is shown in FIG. 2 as an arrangement of so-called SUBMACROS. These SUBMACROS 2 each consist of a 1-bit adder 3 , each having an input for the corresponding bits of the data word and a further input for a carry bit. The 1-bit adder 3 furthermore have an output for the summand and an output for the carry-over.

FIG. 3 shows the binary logic of a 1-bit adder or a SUBMACROS 2 according to FIG. 2. Analogous to FIG. 2, this switching logic has an input Ai, Bi for the conjugate bits of the data to be linked; Furthermore, an input Uein is provided for the transfer. These bits are linked to the illustrated connections or links correspondingly into two OR gates 5 and three NAND gates 6 , so that at the output terminal Si and at the output for carryover, the link adder corresponding to a full adder (Si, OUT) is present.

The invention begins where, as shown in FIG. 4, it is a question of implementing the SUBMACRO 2 shown in FIG. 3 or one or more arbitrary function (s) in a suitable manner in a cell structure. This ge happens on the basis of logically and structurally identical cells 10 , whose individual logical components of the logic function to be performed are correspondingly coupled to each other, by means of the charging logic to be described. According to the shown in Fig. 4, derived from the switching logic of FIG. 3 logic linkage for a 1-bit adder are two cells 10.1 , 10.2 with respect to the logic blocks in so far the same that each have an OR gate 5 and a NAND Member 6 are activated. A third cell 10.3 is used only as a line cell (interconnect cell) and the fourth cell is 10.4 be connected to the third NAND gate 6 is active. That from the four cells 10.1 . , , 10.4 existing SUBMACRO 2 is thus representative of a 1-bit adder, ie a 1-bit adder of a data processing device according to the present invention is four accordingly programmed (configured) cells 10.1 . , , 10.4 verified. (For the sake of completeness, it should be noted that the individual cells have a considerably more extensive network of logical building blocks, ie logic gates, and inverters, which can each be activated according to the current command of the charging logic Network of interconnections between the respective neighboring blocks and to build line and column-wise bus structures for data transmission on the other hand provided so that can be implemented via a corresponding programming tion on the part of the charging logic quasi arbitrary logical Ver knüpfungsstrukturen).

For the sake of completeness, FIG. 5 shows the cell structure of an 8-bit adder in its entirety. The structure shown in Fig. 5 corresponds to that of FIG. 2, wherein the in Fig. 2 symbolically as SUBMACROS 2 represents 1-bit adder each by a four-cell unit 10.1 . , , 10.4 are replaced. Based on the inventions to the invention data flow processor, this means that zweiund thirty cells of the available set of cells of a cell with a geometrically identical layout gefer ended circuit board on the part of the charging logic controls and be configured or programmed so that these thirty-two cells an 8-bit Add adders.

In the illustration according to FIG. 5, a SUBMACRO "X" is graphically separated by means of a dot-dash frame, which is ultimately to be regarded as consisting of four cells ( 10 according to FIG. 4) consisting of four 1-bit adders.

The SUBMACRO "X" separated in FIG. 5 is shown in FIG. 6 as part of an integrated circuit (chip) 20 together with line and data connections. The SUB MACRO "X" consists of the four cells 10 which according to the orthogonal structure per page four data ports (ie a total of sixteen data ports per cell) aufwei sen. The data ports each connect adjacent cells, so that it becomes apparent, for example, how a data unit is passed through from cell to cell. The control of the cells 10 takes place on the one hand via sogenann te local controls, these are local lines that are connected to all cells, and on the other hand via so-called global lines, ie lines that are on the ge entire integrated circuit (chip) 20 out.

In Fig. 7, an enlarged section of an integrated th circuit 20 is shown, which is occupied by a orthogona len grid of cells 10 . As hinted at in FIG. 7, for example, a group of four cells 10 can be selected as SUBMACRO "X" and be programmed or confi gured to the 1-bit adder according to FIG .

A complete integrated circuit (chip) 20 is shown in FIG . This integrated circuit 20 be available from a plurality in the orthogonal grid arrange ter cells 10 and has at its outer edges a ent speaking number of line terminals (pins) on the signals, in particular drive signals and data supplied leads and can be forwarded. In FIG. 8, in turn, the SUBMACRO "X" according to FIG. 5 / FIG. 6 is delimited; In addition, other SUBMACROS are separated, the specific functions and networks are summarized according to subunits. The integrated circuit (chip) 20 is assigned a charging logic 30 or higher, via which the integrated circuit 20 is programmed and configured. The charging logic 30 ultimately tells the integrated circuit 20 how to work arithmetically and logically. . Referring to Figures 1 to 5 is shown in Figure 8 on the one hand SUBMACRO "X" according to Figures 4 and 5 highlighted...; On the other hand, a MACRO "Y" corresponding to Fig. 1 and Fig. 2 is also indicated, which corresponds as a unit to an 8-bit adder.

A computer structure will be described below with reference to FIG. 9 or FIG. 10, which is based on the integrated circuit 20 defined and explained above.

According to the first game Ausführungsbei shown in Fig. 9 is - analogous to the arrangement of the cells - in Orthogo nalraster a plurality of integrated circuits 20 are arranged, each of which adjacent to each other via local bus lines 21 are coupled or networked. The - for example, from sixteen integrated scarf circling 20 existing - computer structure has input / output lines IO, via which the computer is quasi with the outside world in connection, ie corresponding. The computer according to FIG. 9 furthermore has a memory 22 , which according to the exemplary embodiment shown consists of two separate memories, each composed of RAM, ROM and a dual-ported RAM as shared memory to the charging logic, which functions equally as a write processor. Read memory or even as a read memory can be realized. The computer structure described so far is the charge logic 30- or superordinate orders, by means of which the integrated circuits (data flow processor) 20 are programmed and configured and ver networked.

The loading logic 30 is based on a transputer 31 , ie a processor with a microcoded instruction set, which in turn is assigned a memory 32 . The connection between the transputer 31 and the data flow processor is based on an interface 33 for the so-called load data, ie the data program the data flow processor task specific and configure and an interface 34 for the aforementioned computer memory 22 , ie the shared memory memory.

The structure shown in FIG. 9 thus represents a complete computer which can be programmed and configured in each case via the charging logic 30 in a case-specific or task-specific manner. For completeness, it should be noted that - as indicated in connection with the charging logic 30 via arrows - several of these computers ver networked, that can be coupled together.

Another embodiment of a computer structure is shown in FIG . In contrast to FIG. 9, in addition to the local BUS lines between the adjacent integrated circuits 20 , higher-level central BUS lines 23 are provided in order to be able to solve specific input or output problems, for example. Also, the memory 22 (shared memory) is verbun via central BUS lines 23 to the integrated circuits 20 , as shown in each case with groups of these integrated circuits. The computer structure shown in FIG. 10 has the same charging logic 30 as explained with reference to FIG. 9.

In connection with FIG. 11a, an adder circuit constructed on data flow processors according to the invention is intended to be explained. The starting point is two series of numbers An and Bn for all n between 0 and 9; the task is to form the sum Ci = Ai + Bi, where the index i can assume the values 0 ⇐n <9.

Referring to the illustration of Fig. 11a, the number series An is stored in a first memory RAM1, for example, from a memory address 1000h; the number series Bn is stored in a memory RAM2 at a memory address 0dfa0h; the sum Cn is written in the RAM1 under the address 100ah.

A further counter 49 is switched on, which only counts up the individual clock cycles enabled by the control circuit. This will serve to clarify the reconfigurability of individual MACROs without influencing the MACROs not involved in the reconfiguration.

Fig. 11a first shows the actual addition circuit 40 , which consists of a first register 41 for receiving the number series An and a second register 42 for receiving the number series Bn. The two registers 41/42 , an 8-bit adder according to the presented in Fig. 1 Darge MACRO 1 is connected downstream. The output of the MACRO 1 leads via a driver circuit 43 back to the memory RAM1. The timing of the addition circuit 40 via a controlled by a clock generator T timing (STATEMACHINE) 45 , which is connected to the registers 41 , 42 and the driver circuit 43 .

The addition circuit 40 is functionally supplemented by an address circuit 46 for generating the address data for the addition results to be stored. The Adreßschal device 46 in turn consists of three MACROs 1 (as shown in FIG. 1) for forming the address data, these MACROs 1 are connected as follows: About one input to be linked addresses for An, Bn, Cn are supplied. These addresses are added to the output signals of a counter 47 and linked to the state machine 45 so that the new destination address is present at the output. The counter 47 and the comparator 48 have the task to ensure that each of the correct summands are linked and that in each case at the end of the series of numbers, that is broken off at n = 9 abge. If the addition is completed, then in the time control 45, a STOP signal is generated and the circuit switched passive. Similarly, the STOP signal can be used as an input signal for a synchronization circuit ver in that the synchronization logic can recognize from this signal that the total function "Add" according to the ML1 program described below is completed and the MACROs can thus be replaced by new ( for example, STOP could be the signal Sync5).

The time sequence in the time control 45 (STATEMACHINE) can be represented as follows, wherein it should also be noted that in the time control 45 a delay time T (in the form of clock cycles) is implemented between the address generation and the data retention:

• In cycle 1, counter 47 is incremented by 1 and comparator 48 checks whether n <9 is reached; synchronously with these operations, the addresses for A, B, C are calculated;
• - In the cycle (T + 1) the summands A, B are read out and added;
• - in the cycle (T + 2) the sum C is stored.

In other words, this means that the operation loop and the actual addition is even (T + 2) clock cycles requires. In general, for T 2. , , 3 bars required so that compared with the conventional Prozes soren (CPU), which is generally 50 to several hundred Clock cycles, a very important computation time Reduction is possible.

The configuration shown with reference to FIG. 11 will be explained again below using a hypothetical MACRO language ML1:
There are the number series An and Bn

n: 0 ⇐ n ⇐ 9

The sums Ci = Ai + Bi with I ∈ N are to be formed.
const n = 9;
array A [n] in RAM [1] at 1000h;
array B [n] in RAM [2] at 0dfa0h;
array C [n] in RAM [1] at 100ah;
for i = 0 to n with (A [i], B [i], C [i])
Δ1;
C = Δ1 = A + B;
next;
RAM1 is the 1st memory block
RAM2 is the 2nd memory block
at follows the base address of the arrays
for is the beginning of the loop
next is the loop end
with () are followed by the variables whose addresses are determined by the count variable i
Δ T follows the delay time for a state machine in clock cycles.

The timing of the state machine looks accordingly as follows:

cycle activity 1 Increase counter, compare to <9 (yes ⇒ cancel) and calculate addresses for A, B, C T + 1 A, B, bring and add T + 2 Save to C

That means - as already mentioned - the loop and the Addition just needs T + 2 clock cycles.

Fig. 11b shows the rough structure of the individual functions (MACROs) in a DFP. The MACROs are shown in their possible position and size and provided with the corresponding numbers explained with reference to FIG. 11a.

Fig. 11c shows the rough structure of the individual functions on the RAM blocks 1 and 2: The summands are successively read from the RAM blocks 1 and 2 from address 1000h or 0dfa0h and in RAM block 1 from address 100ah in ascending order saved. In addition, the counters 47 and 49 are given, both count from 0 to 9 during the course of the circuit.

After completion of the program described is a new Program that will continue to use the results tet. The transhipment should take place at runtime. The program is given below:  

There are the number series An and Bn, where An through given the result Cn of the previously executed program is:

n: 0⇐n⇐9

The products Ci = Ai _* Bi with I ∈ N are to be formed.
const n = 9
array A [n] in RAM [1] at 100ah
array B [n] in RAM [2] at 0dfa0h
array C [n] in RAM [1] at 1015h
for i = 0 to n with (A [i], B [i], c [i])
Δ1;
C = Δ1 = A _* B;
next;
The description of the individual commands is already known
_* symbolizes the multiplication.

The MACRO structure is described in FIG. 18a, FIG. 18b indicates in a known manner the position and size of the individual MACROs on the chip, the size of the multiplier 2 in particular being considered in comparison with adder 1 from FIG. 11b. FIG. 18c again shows the effect of the function on the memory. Counter 47 again counts from 0 to 9, ie it is reset when the MACROs are reloaded.

Of particular note is the counter 49 . Suppose the reload of MACROs is 10 clock cycles. Then, the counter 49 runs from 9 to 19, because the block is dynamically reloaded, ie only the parts to be reloaded are stopped, the rest continues to work. This will cause the counter to run from 19 to 29 during the program. (Here the dynamic independent reloading is to be demonstrated with, in each module known so far, the counter would again run from 0 to 9 because it is reset).

A closer look at the problem raises the question why not both operations, the addition and the multi plikation be performed in a cycle, so the Surgery:

There are the number series An and Bn, where An through the result of Cn of the previously executed program gege Ben is:

n: 0⇐n⇐9

The products Ci = (Ai + Bi) _* Bi with I ∈ N are to be formed.
path D;
const n = 9;
array A [n] in RAM [1] at 1000h
array B [n] in RAM [2] at 0dfa0h
array C [n] in RAM [1] at 100ah
for i = 0 to n with (A [i], B [i], C [i])
Δ1;
D = Δ1 = AbB;
C = Δ1 = D _* B;
next;

path D does not define an internal one out of the DFP led double path. The surgery needed because of one too additional Δ1 one clock cycle more than before, is in the overall, however, faster than the two programs above Sequence executed, because on the one hand, the loop only once is passed through, the second is not reloaded.  

In principle, the program could also be formulated as follows:
const n = 9;
array A [n] in RAM [1] at 1000h
array B [n] in RAM [2] at 0dfa0h
array C [n] in RAM [i] at 100ah
for i = 0 to n with (A [i], B [i], C [i])
Δ- 1;
C = Δ2 = (A + B) _* B;
next;

If the gate times of the adder and of the multiplier together are less than one clock cycle, the operation (A + B) _* B can also be carried out in one clock cycle, which leads to a further considerable speed increase:
const n = 9;
array A [n] in RAM [1] at 1000h
array B [n] in RAM [2] at Odfa0h
array C [n] in RAM [1] at 100ah
for i = 0 to n with (A [i], B [i], C [i])
Δ1;
C = Δ1 = (A + B) _* B;
next;

Referring to Fig. 12, a simple example of a Zel lenaufbaus will be explained. The cell 10 includes the case of an AND gate 51 , an OR gate 52 , an XOR gate 53 , an inverter 54 and a register cell 55th The Zel le 10 also has on the input side two multiplexers 56 , 57 with (the sixteen inputs of the cell corresponding to FIG. 6), for example, sixteen input terminals IN1, IN2. By means of this (16: 1) -multiplexer 56/57 , in each case the said logical elements AND, OR, XOR 51 . , , 53 to be supplied data selected. These logic gates are coupled on the output side to a (3: 1) multiplexer 58 , which in turn is coupled to the input of the inverter 54 , an input of the register cell 55 and another (3:16) multiplexer 59 . The latter multiplexer 59 is additionally connected to the output of the inverter 54 and an output of the register cell 55 , and outputs the output signal OUT.

For completeness, it should be noted that the register cell 55 is coupled to a reset input R and a clock input.

The above-explained cell structure, ie the cell 10 is now superordinate a Ladelogik 30 which is connected to the multiplexers 56 , 57 , 58 and 59 and this controls the desired functions accordingly.

If, for example, the signals A2 are to be rounded to B5, the multiplexers 56 , 57 are switched to the lines "TWO" or "FIVE"accordingly; the summands then go to the AND gate 51 and are given at the appropriate output of the multiplexer 58 , 59 at the output OUT. If, for example, a NAND operation is to be performed, the multiplexer 58 switches to the inverter 54 and the output OUT is then the negated AND result.

Claims (8)

1. Data processing device, wherein a (in the following data flow processor - DFP - said) integrated circuit circuit (chip) is provided with a plurality, in particular orthogonal to each other to ordered homogeneous structured cells, each having a plurality of logically identical and structurally identical table arranged components whose cells line - and in columns, optionally combined in groups, are connected to input / output terminals of the integrated circuit, characterized in that the cells is associated with a charging logic, they summarized by themselves and possibly groupwise together so programmable (configurable) that any logical functions and / or interconnections are verifiable with each other, such that a manipulation of the DFP configuration during operation (or at runtime), ie the modification of functional parts (MACROS) of the DFP can be done without other functional parts must be stopped or impaired in their function. 2. Data processing device according to claim 1, characterized,  that the charging logic is coupled to storage means, about which the configuration of the cells can be specified is. 3. Data processing device according to one of the claims 1 to 2, characterized, that the loading logic consists of a processor that the entire program based on in ver various stored data and programs in the Managed according to a Harvard structure. 4. Data processing device according to claim 3, characterized, that the charge logic in turn from cells with one each The majority are logically the same and structural is constructed identically arranged blocks. 5. Data processing device according to one of the claims 1 or 4, characterized, that the cells dynamically during a program run can be reconfigured without the to be edited Data itself. 6. data processing device, where a (in the following data flow processor - DFP - mentioned) integrated circuit (chip) with a plurality in particular orthogonal to each other ordered homogeneously structured cells with one each The majority are logically identical and structurally identical is arranged table arranged blocks, its cells in rows and columns, optionally Grouped together, with input / output connected connections of the integrated circuit are,  characterized, a plurality of them can be coupled in cascade form are. 7. Data processing device according to one of the claims 1 to 6, marked by, the assignment of suitable data input / output units and at least one memory for building a (com plexen, complete) calculator. 8. Data processing device according to one of the claims 1 to 7, characterized, that the functions of the input / output units partially implemented in integrated circuit (chip) are.