DE4447853C2 - Storage system input=output system with exclusive controller - Google Patents

Abstract

A large computer system has multiple control processors that use common data and freely exchange information. For this an input/output system with memory capability is provided. The system has channel adapters (21a-21c) that connect with a common I-O memory (22) and to an exclusive operations management controller (23). The controller has a control table with a logical channel number listed and an indication of whether the channel is busy. This is stored in non-volatile memory to protect against power loss. Requests for access by processors involve the accessing of the table and the setting of flags.

Description

The present invention relates to an auxiliary I / O system and a data storage method in an auxiliary I / O system.

A new, significantly enlarged large computer system is made up of several Central processing units (CPU) together. In such a system the common one is Use of data and the exchange (communication) of data between several CPUs necessary. For this reason, an auxiliary I / O system with an external Storage unit needed, which in turn with multiple host interfaces (or host or Main interfaces) should be provided.

To meet these requirements, the auxiliary I / O system has a variety of Input / output controllers (Ca: channel adapter) with multiple input / Output interfaces connected to the host CPUs. To access multiple Controlling CPUs exclusively is the auxiliary I / O system with an exclusive control manager (RM: Resource Manager) with an exclusive control table.

Fig. 1 shows the structure of a semiconductor disk device, for example an I / O subsystem. In Fig. 1, reference numerals 1 a, 1 b each designate a CPU, 2 a semiconductor plate controller and 3 a semiconductor plate with a plurality of semiconductor memory modules 3 a, 3 b, 3 c,. , .. The semiconductor disk device has the same structure (command code, data transmission method, etc.) as that of a magnetic disk device, except that the magnetic disk as a recording medium is replaced by a semiconductor memory. Therefore, the interface between the CPU 1 a ( 1 b) and the semiconductor disk controller 2 completely matches the interface between the CPU 1 a ( 1 b) and a magnetic disk controller. This semiconductor disk device has the advantage that quick access is possible since the movement of the head required for a magnetic disk is unnecessary and that the software means between the CPU and the magnetic disk controller can be used unchanged.

In the semiconductor disk controller 2, the reference numerals 2 designate a and 2 b are each a channel adapter CA with a single or multiple interfaces (Host Interface) from and to a host apparatus (CPU), 2 c and 2 d are each a storage interface adapter for controlling the writing and reading out the data on or from the semiconductor plate 3 , 2 e, a resource manager RM with an exclusive control table ECT, which executes an exclusive control to enable the host interface to use the semiconductor module 3 a, 3 b or 3 c if another host interface does not do so, while excluding use if another host interface uses the semiconductor module. Exclusive control is carried out in each semiconductor memory module.

Two physical interfaces (physical ports, connection points for peripheral devices) 2 a ₀ , 2 a ₁ ( 2 b ₀ , 2 b ₁ ) are provided between the channel adapter 2 a ( 2 b) and the CPU 1 a ( 1 b). The exclusive control table ECT of the resource manager 2 e records whether each of the semiconductor memory modules 3 a, 3 b, 3 c (device number 0 to 2 ) is occupied by a combination (path) of a channel adapter (channel number) and a physical interface that, how shown in Fig. 2, is placed on each channel adapter. There are four different types of paths (for example, (00), (01), (10) and (11) in the semiconductor plate controller 2 .

Is appropriate in this I / O subsystem a command to access the semiconductor memory module 3 b of the CPU 1b to the channel adapter 2 b via the physical interface 2 b ₁ is output, such as calls, the channel adapter 2 b the resource manager 2 e, which To allow use of the memory module 3 b. If the resource manager 2 e receives the request for use, it is checked whether the semiconductor memory module 3 b is used via a different path by referring to the exclusive control table ECT. If the answer is YES, the resource manager 2 e does not allow the channel adapter 2 b to use the semiconductor memory module. On the other hand, if the answer is NO, the resource manager 2 e allows the channel adapter 2 b to use the semiconductor memory module, and at the same time sets a flag (flag) that indicates "occupied" in the field of the semiconductor memory module 3 b in accordance with the path ( 11 ). The channel adapter 2 b, which was allowed to use the semiconductor memory module 3 b, then receives data from the CPU 1 b via the physical interface 2 b, and writes this data into the semiconductor memory module 3 b via the memory interface adapter 2 d. As soon as the write operation has ended, the resource manager 2 e changes the “busy” flag with respect to the path ( 11 ) to a flag that indicates “free”.

Exclusive control problems

As previously described, in the conventional I / O subsystem, a table or Table section from the exclusive control table ECT one in advance Channel adapter assigned in the I / O subsystem. If the number of channel adapters in the I / O support system are housed, is increased and the number of physical Interface is increased in each channel adapter, the size increases for this reason the exclusive control.

With the new development and change in data transmission technology, many exist Types of interface systems (for example electrical interface systems, optical Interface systems and OC connections) side by side. To now in this situation It is necessary to connect the I / O auxiliary system with as many CPUs as possible to match existing interface systems. That is, it is necessary to have various Provide channel adapter types in the auxiliary I / O system to accommodate each interface system correspond, which therefore increases the number of channel adapters. This happens through also because not only the physical data transmission devices but also also the number of physical interfaces that are provided in a channel adapter can be different in interface systems. For this reason, the Exclusive control table further enlarged.

If multiple logical interfaces are defined on one physical interface, the exclusive control table must be created while considering each logical interface. Fig. 3 is an exemplary view of an OC link interface system. In Fig. 3, reference numeral 4 denotes a a channel adapter for an OC link, an OC link changer / amplifier which is provided between a (... I = 1, 2,) CPU 4 _ci and the I / O subsystem to switch the interface dynamically. It is possible to define a maximum of 256 CPUs on one physical interface via the OC connection switch / amplifier. If several logical interfaces are defined on one physical interface in this way, it is necessary to create an exclusive control table ECT which treats each of the logical interfaces as if they were different physical interfaces.

A so-called multi-access system enables one Multiple access by defining multiple I / O device addresses related to one I / O device become. This multi-access system is used as an I / O device access system that to multiple areas simultaneously in one I / O device, such as a magnetic drum a semiconductor disk device and a disk cash (cash = fast buffer) can access via different paths. A computer has an architecture, the virtual one Machines (separate execution systems that are independent of each other from a single CPU be operated). If several such virtual machines (Drain systems) are operated, an access (English: exposure) an operating system assigned to ensure independence of I / O device access for each operating system to back up. In this way, several logical interfaces exist on one physical Interface if there are multiple virtual machines. In this case it is also necessary to generate the exclusive control table ECT while the logical interfaces are so treated as if they were different physical interfaces.

Fig. 4 is an exemplary view of a multi-access system. It is now assumed that 256 I / O device addresses, for example (00) _hex to (FF) _hex , can be defined on an interface. At the same time, the area bits of an address are assigned to an access number. As shown in Fig. 4a, for example, the first two bits are assigned to an access number and the last six bits to a device number. This means that accesses 0, 1, 2, and 3 are defined. If the number of the physical I / O device in the auxiliary I / O system is assumed to be one and the device number is 0, the relationship shown in Fig. 4B is held between the access number and an I / O device address. These four I / O device addresses designate the same physical device (multiple definition). The number of the accesses can differ from four and the bit positions which indicate the access number can also be other positions.

As described above, in the conventional I / O auxiliary system, a table section is permanently assigned to an exclusive control table in accordance with the maximum possible structure of the I / O auxiliary system. In this system, it is necessary to save a large table area on the exclusive control table so that a large memory area is required. Fig. 5 shows an example of a structure of a conventional exclusive control table. In this table, the symbol n1 represents the maximum number of channel adapters installed in an I / O auxiliary system, n2 the maximum number of physical interfaces installed on a channel adapter and n3 the maximum number of logical interfaces defined on a physical interface. The number of data words in the column is n1 × n2 × n3. In this auxiliary system, however, the number of physical interfaces on a channel adapter and the number of logical interfaces on a physical interface vary. Much of the table remains generally free, so it is unnecessary to create a large exclusive control table.

Problems in semiconductor memory

In a semiconductor disk device, a semiconductor memory chip is used as a data storage medium used. For this reason, the storage cost per bit is higher than that in one Magnetic disk device. In addition, the storage capacity is one Semiconductor disk device less than that of a magnetic disk device. To the problem to solve the storage capacity, the shape of a semiconductor memory chip is revised or improves the method of building a semiconductor memory chip. Both improvements however, there are restrictions and the cost issue remains unsolved. Around To solve this cost problem, a storage technology is necessary, where possible large amount of data is stored on the same physical semiconductor memory means.

In a conventional semiconductor plate device, the current one Magnetic disk device appropriate format (CDK format) during emulation used. That is, an area in the semiconductor memory is assigned to gap information, to control the input / output of data from and to a magnetic disk medium necessary is.  

Fig. 6 shows a data format in a conventional semiconductor disk device. The DIR symbol represents a directory that was recorded at the head of a track field. This data is essential in a semiconductor disk, but does not exist in a current magnetic disk device. After the directory DIR, several data fields Ri are recorded, each of which is composed of a counting area Ci (i = 1, 2,...), A key area Ki and a data area Di. The count area Cl contains a track address, a data field number and the length of the key area Ki and the data area Di. The key area Ki is not always necessary, but records a key or index for searching using an access method. The data area Di records data which are generally referred to as "user data". All adjacent recording areas are separated from one another by a gap g.

Such a gap g is not necessary when accessing a semiconductor memory. For this The reason is a larger amount of data on the same physical semiconductor memory means saved if all columns g are removed. However, as compared to these gap areas to the total area of the auxiliary system are very small, the removal of the gap areas cannot be called a very effective solution.

Another technique is data compression described in US 5,167,034. / Restore technology. Data is compressed to the original data size without reducing the data content, reduce the compressed data on one external storage medium and the original data from the compressed data restored when the data is processed. There are different procedures for this Technology. A typical method is to match data in accordance with the Encode data continuation in a block of data chains, and includes a run-length Coding method and a universal coding method. For example, with the Run-length coding method the character "a" are compressed, it results in the compressed character "a2" for a character "aa" or the compressed character for "aaaaa" Character "a5".  

In the universal coding method, the input data is encoded by the information is used, which represents a partial data chain that has already been encoded. The typical one Universal coding method uses a Ziv-Lempel code (see for example Munakata, "Data Compression Method by Ziv-Lempel" Information Processing Volume 26, No. 1, 1985). Two algorithms are proposed in this Ziv-Lempel coding method, namely (1) a universal type and (2) a step-by-step analysis type. A universal type A practical method using the algorithm is, for example LZSS coding method (T. C. Beil, "Better OMP / L Text Compression", IEEE trans. On Commun, volume COM-34, No. 12, Dec. 1986). As a practical process that the an LZW is used, for example, step-by-step analysis algorithm (Lempel-Ziv-Welch) coding method (T. A. Welch, "A Technique for High-Performance Data Compression ", Computer June 1984).

In the event that a large amount of data in the same physical semiconductor memory to enroll, consideration will be given to choosing a method that writes compressed data and reads it into the original data when it is read reconverts. However, this data compression technique still leaves unsolved There are problems.

A first problem, for example, is that it takes a long time for data compression Time is needed. Although there are small differences in data compression methods there, data compression is basically buffered to monitor the data compression Data patterns and the registration and recovery of the encoded data. For this The reason is that the data transmission time for the compressed data is longer than that Transmission time for data that are not processed. Such Excess time can occur in a semiconductor disk device that has uniform access allowed very high speed regardless of the data type, not disregarded stay.

A second problem is that the size of the compressed data before actual compression cannot be estimated. For example, if saved Data is read out and written back after a change in a part,  it is often no longer possible to store this data in the same place because of the size of the compressed data differs from the size before the change. Becomes for example, in the run-length coding method which is encoded as "a4" and in Semiconductor memory saved data "aaaa" changed to "aabaa", so the Compression to the data word "a2ba2", reducing the size of the compressed date grows. Unless the data is continuous or the pattern of the data or the Frequency of data appearance is not constant, compression in general impossible. In the worst case, the size of the compressed data exceeds that of the original data.

A third problem is that if there is an abnormality in one Compression mechanism or the like comes, this abnormality is not found can be as long as the compressed data is not in the original data be converted back.

It is necessary to solve these problems to the amount of data stored in the semiconductor memory is saved using the data compression recovery method, to increase.

Memory initialization time issues

If in the case of a storage unit which has volatile memory, for example a Semiconductor plate device used, the voltage source is turned on or the PCB with memory modules put on or removed, the content of the memory undefined. In this case, an initialization of the memory for writing is more specific Data (initialization data) required in the memory. Since the device during the Initialization cannot be used, the user has to wait for some time after the voltage source has been switched on. In addition, memory access is during initialization is impossible because the access controller is performing the initialization. It is therefore necessary, such inconvenience in a storage unit as much as possible to reduce by shortening the initialization time or the memory access path is improved.  

Fig. 7 shows a conventional initialization mechanism. If the voltage source is switched on, an initialization start signal INS is generated in a host module or an access controller 11 . A data register 12 receives this initialization start signal INS and accepts write-in data IDT for initialization. An initialization address counter 13 outputs an initialization address IAD. An address switch 14 converts an address signal AD from the host module to the initialization address IAD, and outputs the initialization data IDT to a data bus 15 , the initialization address signal IAD to an address bus 16, and a memory access synchronization signal (not shown) to perform the initialization of a memory unit 10 , Here, REF denotes a refresh command signal and IED an initialization end signal.

Fig. 8 shows the structure of another conventional initialization mechanism. In this mechanism, two access controller access 11 a, 11 b on three memory areas 10 a, 10 b and 10 c separated from each other to. Each of the access controllers 11 a, 11 b has the same structure as the access controller 11 shown in FIG. 7. If the memory area 10 b in the middle by placing a printed circuit board for a memory module is completed, the upper access controller 11 a accesses the memory area 10 b to initialize them in the same way as the mechanism shown in Fig. 7. During the initialization of the memory area 10 b, the lower access controller 11 b receives an address signal AD and a data signal DT from the host module and outputs these signals to the address bus 16 and the data bus 15, respectively. Furthermore, it emits a memory access synchronization signal (not shown) in order to access the other two memory areas 10 a and 10 c depending on the access request from the host module.

As described above, the initialization is carried out in a conventional manner by generating an initialization address and writing initialization data into a memory depending on the address of an access controller. If volatile memory is to be initialized, a refresh operation is required to hold the data in memory. Therefore, if a refresh command signal REF (see Fig. 7) is input, the initialization address counter 13 stops generating an initialization address signal IAD for the time of the refresh operation. As a result, the time required for initialization is the sum of the time for writing in the initialization data IDT and the time for performing the refresh operation.

If the initialization takes a long time, for example because the access request from the host module cannot be processed until the end of the initialization, the user who has switched on the power supply has to wait for a long time before he can actually use the device. In the mechanism shown in Fig. 8, the other access controller can process the access request from the host module. Overall, the device's memory access performance is reduced by half during this time. That is, even with this mechanism, the performance is greatly degraded if the initialization takes a long time.

As previously described, the exclusive control table is in a conventional I / O Auxiliary system large, with a large memory for storing this exclusive control table is needed.

In addition, the process of writing compressed data in one suffers conventional semiconductor disk device under various problems such as (1) an increase in the transmission time that cannot be disregarded, (2) one not predictable size of the compressible data and (3) an impossible Detection of an abnormality if such an abnormality in the Compression control mechanism is caused as long as the data is not be recovered or restored.

In addition, since a refresh operation for initializing a semiconductor memory or the waiting time for access is extended.

The object of the present invention is an auxiliary I / O system or a data storage method specify that allow a large amount of data with high data security on a Semiconductor disk device (memory chips) for data processing in host devices save.  

In particular, the data processing speed when using Data compression method when storing the data on the memory chips compared to the known systems increased or constant and an "overflow" of the Semiconductor memory can be prevented during the memory operations.

This object is achieved according to the features of independent claims 1 and 10 solved. The invention is developed by the features of the dependent claims.

Further details and advantages of the present invention will become apparent from the following Description clearly with the help of the accompanying drawings.

Fig. 1 shows the construction of an EI A auxiliary system as a semiconductor disk device;

Fig. 2 is an explanatory view of an exclusive control table;

Fig. 3 is an explanatory view of an OC connection interface system;

FIGS. 4A and 4B are explanatory views of an access;

Fig. 5 shows the structure of a conventional exclusive control table;

Fig. 6 shows a data format used in a conventional semiconductor disk device;

Fig. 7 shows a conventional initialization mechanism;

Fig. 8 shows the structure of another conventional initialization mechanism;

Fig. 9 is a first schematic view of the present invention;

Fig. 10 is a second illustrative view of the present invention;

Fig. 11 is a third schematic view of the present invention;

Fig. 12 shows the structure of one embodiment of an exclusive control method of the invention;

Fig. 13 shows the structure of the hardware of each unit in the embodiment of Fig. 12;

Fig. 14 is an explanatory view of a logical path control table in the embodiment shown in Fig. 12;

Fig. 15 is an explanatory view of an exclusive control table in the embodiment;

Fig. 16 is an explanatory view of the assignment of a logical path number if a host interface matches a physical interface in the embodiment;

Fig. 17 is an explanatory view of the contents of a logical path control table;

FIG. 18A and 18B are explanatory views of the assignment of a logical path if a host interface matches a logical interface in the embodiment;

Figs. 19A to 19C are explanatory views showing a logical path number assignment control in an access system;

Figure 20 is a flowchart of resource manager processing in logical path number assignment control;

Fig. 21 is a first flow diagram of processing by the channel adapter in logical path number assignment control;

FIG. 22A and 22B are explanatory views of the registration of a logical path number by a channel adapter;

Fig. 23 is a second flowchart of processing by a channel adapter in logical path number assignment control;

Fig. 24 is a flowchart of exclusive control;

Fig. 25 shows the entire structure of a current semiconductor plate;

Fig. 26 shows the structure of an embodiment of a data storage control method for storing compressed data in a semiconductor memory module of a semiconductor disk device according to the present invention;

Fig. 27 shows the structure of the channel adapter in the embodiment shown in Fig. 26;

Fig. 28 shows the structure of the data control adapter in the embodiment shown in Fig. 26;

Fig. 29 shows the structure of the backup disk adapter in the embodiment of Fig. 26;

Fig. 30 is an explanatory view of the data format according to the invention;

Fig. 31 is an explanatory view of the operation of the data write control;

Fig. 32 is an explanatory view of the operation of the data write control in the event that a semiconductor memory module has overflowed;

Fig. 33 is an explanatory view of the operation of the data read controller;

Fig. 34 is an explanatory view of the storage area of the backup disk device in the embodiment shown in Fig. 26;

FIG. 35A and 35B are explanatory views of a conventional Speicherinitialisierungsverfahrens;

FIG. 36A and 36B are explanatory views of a refresh operation;

FIG. 37A and 37B are explanatory views of an initialization according to the invention;

Fig. 38 shows the structure of an embodiment of a Speicherinitialisierungsverfahrens according to the present invention;

Fig. 39 is a timing chart illustrating the operation of the embodiment shown in Fig. 38;

Fig. 40 shows the structure of another embodiment of a Speicherinitialisierungsverfahrens according to the present invention;

Fig. 41 shows the structure of an initialization address counter used in a high-speed access mode;

Fig. 42 is an explanatory process is a further embodiment of a Speicherinitialisierungsverfahrens of the present invention which allows high-speed access;

Fig. 43 shows the construction of another embodiment of a memory initialization method according to the present invention, in which the memory is divided into several blocks;

Fig. 44 shows the structure of the initialization address counter used in the embodiment shown in Fig. 43; and

FIG. 45 is an explanatory view of a data write method of the embodiment shown in FIG. 43.

(a) Schematic structure of the invention

FIGS. 9 and 10 are schematic views of the structure of the present invention.

(a-1) Exclusive control ( Fig. 9)

Referring to FIG. 9, reference numerals 21 a to 21 c plurality of input / output interface regions (channel adapter), each comprising a single or multiple interfaces (Host Interface) between a host device (ie, a host computer) and the interface region , Reference numeral 22 denotes an I / O device (semiconductor memory) which is shared between the multiple interface areas 21 a to 21 c, and 23 denotes an exclusive controller (resource manager) which is provided with an exclusive control table ECT and a logical path control table LPT and which enables a host interface to use an I / O device if it is not being used by another host interface, whereas use is prohibited if the other host interface uses it.

The exclusive controller 23 assigns a logical path number to each host interface of each input / output interface area 21 a to 21 c, manages the state of use of the I / O device in accordance with the logical path number in the exclusive control table ECT and checks whether the I / O device 22 is used by another host interface via a different logical path by accessing the exclusive control table ECT when the exclusive controller 23 receives the request to use the I / O device 22 via a host interface with one receives its assigned predetermined logical path number. If the answer is NO, the exclusive controller 23 prohibits the host interface that issued the usage request from using the I / O device 22 and sets a flag indicating that the I / O device is "busy" , in the exclusive control table ECT according to the logical path number of the host interface. After the end of use of the I / O device 22 , the exclusive controller 23 changes the flag to "free", which indicates that the I / O device is free again.

In this case it can be a host interface with a physical interface to match. But if there are several logical interfaces in one physical interface are defined, a host interface corresponds to a logical interface. That is, everyone logical interface is assigned a logical path number as a host interface if at least two interfaces are defined on one physical interface. If further assigned multiple I / O machine numbers to a single I / O device and the operating systems in a host device simultaneously for the I / O device become available through a physical interface by the respective I / O machine numbers are used, becomes a host interface number assigned physical interface, depending on the respective I / O device number, and a logical path number becomes each of the host interfaces (Host interface numbers).

According to this structure, it is not necessary to set a large exclusive control table prepare that can cope with the maximum build, as opposed to one conventional auxiliary I / O system. That is, an exclusive control table in which only the Host interfaces currently connected to the I / O subsystem are listed, enough. It is therefore possible to set the size of the exclusive control table and that for it Table to reduce required storage capacity.

The assignment of logical path numbers is controlled in the following way. A logical path control table LPT is provided in the exclusive controller 23 . If the power supply is turned on or logical interfaces are defined, each of calls for the input / output interface areas 21 a to 21 c to when exclusive controller 23, each of host ports that are connected thereto, to assign a logical path number. The exclusive controller 23 dynamically assigns a free logical path number to a host interface depending on the request for assigning a logical path number, and registers the assigned logical path number in the logical path control table LPT according to the identification information (CA number) of the input / output interface area and the identification information (host interface number) of the host interface.

The exclusive controller 23 also stores the logical path control table LPT in a non-volatile memory which does not lose its content even if the power supply fails. It also assigns a logical path number, either based on the logical path control table LPT or on the basis of the aforementioned dynamic assignment of the logical path number, depending on the on / off state of a command device (switch). According to this structure, since it is possible to assign a logical path number before the power failure, the same environment is restored at the time of analyzing an error or a reproduction test of the error.

(a-2) Data storage controller ( Fig. 10)

Referring to Fig. 10, reference numeral 31 denotes a channel adapter for controlling the input / output operation between a host device (CPU) 30 and a memory interface adapter, 32 an exclusive controller (resource manager) for executing exclusive control of access to a semiconductor memory module, 33 a to 33 n semiconductor memory modules, each of which consists of a plurality of semiconductor memory chips, 34 a memory interface adapter for controlling the writing process and the reading process of data to and from a semiconductor memory module, 35 a data control adapter for checking the compressed data which are written into a semiconductor memory module, 36 a backup Disk device and 37 a backup disk adapter.

If data is stored in one of the semiconductor memory modules 33 a to 33 n (hereinafter referred to as semiconductor memory module 33 ) in the I / O system, the channel adapter 31 compresses the data stored in the data buffer and writes the compressed data into the semiconductor memory module 33 . The data control adapter 35 reads and stores the compressed data from the semiconductor memory module 33 to check the compressed data by comparing the newly stored data with the data (uncompressed data) before compression. In this case, after the compressed data have been written into the semiconductor memory module 33 , the uncompressed data which are stored in the data buffer are written into an additional semiconductor memory module 33 s. The uncompressed data are then read out from the additional semiconductor memory module 33 s in order to be compared with the newly stored data.

If an error or an abnormality is recognized as a result of the data comparison, the data control adapter 35 compresses the data read out from the additional semiconductor memory module 33 s and writes this compressed data into the semiconductor memory module 33 . The compressed data is then re-stored and this newly stored data is compared with the uncompressed data in order to check the compressed data written into the semiconductor memory module 33 . The result of the check is recorded in the directory area at the head of the track of the semiconductor memory module 33 .

If the semiconductor memory module becomes full while the compressed data is being written, the uncompressed data is stored in the backup disk device 36 . The uncompressed data from the backup disk device 36 is then written into the semiconductor memory module.

This solves the problems that arise when data is compressed become. This gives you the opportunity to have a large amount of data in one Store semiconductor memory by writing in the compressed data.

(a-3) initialization ( Fig. 11)

In Fig. 11, reference numeral 41 denotes volatile memory in need of refresh, and symbol CA denotes a column address and RA a row address.

The volatile memory 41 is accessed by combining the selected column address CA with the selected row address RA, and is refreshed for each row. In order to initialize the volatile memory 41 , initialization data are written into all memory cells (1 to 2) in an i-th column, while the row addresses RA are generated one after the other in ascending order, the column address CA being kept at a constant value i. The initialization data are then written in the same way in the successive columns (at the row addresses 3 to 4). Since the writing of the initialization data refreshes the memory at the same time, provided that the time required for writing the data into a column is shorter than the time interval between two refresh cycles, a separate refresh cycle is not necessary. This leads to a reduction in the initialization time. If high speed memory is used, the column address CA is divided into an upper column address and a lower column address, with the initialization data being written into the memory cells, while the lower column addresses are generated in ascending order while the upper column address and the row address are being held. The initialization data are then written into the following line in the same way. After the initialization data is written in all rows, the data writing is repeated while the upper column address is increased step by step. This process also avoids a separate refresh cycle, which reduces the initialization time.

(b) Embodiment of the exclusive control method of the invention (b-1) Overall structure

Fig. 12 shows the structure of one embodiment of an exclusive control method of the invention. Reference numeral 20 denotes a semiconductor disk device as an auxiliary I / O system, and reference numerals 30 ₀ , 30 ₁ and 30 ₂ denote CPUs (CPU-0 to CPU-2) as host devices. In the semiconductor disk device 20 , reference numerals 21 a, 21 b and 21 c channel adapter (CA-0 to CA-2), each having a single or more interfaces (host interfaces) to and from a host device (CPU), 22 a semiconductor plate with a plurality of semiconductor memory modules 22 a to 22 n is provided, with each module serving as an I / O device for CPUs 30 ₀ to 30 ₂ . Reference numeral 23 denotes an equipment manager (RM) which is provided with an exclusive control table ECT and a logical path control table LPT, so that a logical path control and an exclusive control can be carried out. The exclusive control table ECT and a logical path control table LPT are stored in a non-volatile memory area. The logical path controller adds a logical path number to a host interface connected to each adapter and controls the path between the CPUs and the semiconductor disk. The exclusive control allows a host interface to use a semiconductor memory, unless it is already being used by another host interface, otherwise the use of the semiconductor memory is prohibited. Exclusive control is performed for each semiconductor memory module.

The reference numeral 24 denotes a memory interface adapter for controlling the data writing and the reading out of data to or from the semiconductor plate 22 , the reference numeral 25 denotes a service adapter (SA) with which, for example, a repair or maintenance or module monitoring is carried out, and 26 denotes a monitoring / Maintenance control panel, which has a switch SW, with which the method for assigning a logical path number is determined. There are two methods of assigning a logical path number: 1 one method (called an unfixed logical path number mode) of assigning a free logical path number when an assignment request of a logical path number is made by one of the channel adapters 21 a to 21 c, and 2 a method (referred to as fixed logical path number mode) for assigning a logical path number based on the logical path control table stored in the non-volatile memory area prior to the power failure. If the switch SW is turned off, a logical path number is assigned by the non-fixed logical path number mode, and if the switch SW is turned on, the logical path number is assigned by the fixed logical path number mode.

Reference numeral 27 denotes an internal bus which has a C-BUS, D-BUS and S-BUS (not shown). The C-BUS is a control bus with which each unit transmits messages and has access to control information. The D-BUS is a data transmission bus, via which each unit feeds data to the semiconductor plate 22 or receives data therefrom, and the S-BUS is a service bus, via which a service module 25 as master controls the state of each unit.

The channel adapter 21 a is provided with a physical interface (physical port) 0, the channel adapter 21 b with two physical interfaces 0, 1, and the channel adapter 21 c with three physical interfaces 0, 1, 2. The physical interface 0 of the channel adapter 21 a also forms the interface of the CPU 30 ₀ , the physical interfaces 0, 1 of the channel adapter 21 b form the interfaces of the CPUs 30 ₀ and 30 ₁ , and the physical interfaces 0, 1, 2 of the channel adapter 21 c form the interfaces of the CPUs 30 ₀ , 30 ₀ , 30 ₂ .

Each of the channel adapters 21 a to 21 c, the resource manager 23 , the memory interface adapter 24 and the service adapter 25 consist of a microprocessor which has essentially the same structure as that shown in FIG. 13. In FIG. 13, reference numeral 101 denotes a microprocessor (MPU), 102 a control memory area (CS) with a RAM (Random Access Memory = random access memory) structure, 103 a control memory area (CS) with a ROM (Read Only Memory, Read Only Memory) construction, 104 a driver / receiver (DV / RV) connected to the internal bus 27 , 105 a bus interface logic (BIL), 106 a driver / receiver (DV / RV) connected to a connected to an external interface, 107 a buffer or a table memory area (TS), and 108 an individual LSI (gate array). The number of drivers / receivers (DV / RV) 106 depends on the number of connected external interfaces.

(b-2) Logical path control table

The logical path control table LPT stores a logical path number, a channel adapter number (CA number) and a host interface number in correspondence with each other, as shown in FIG. 14. If no logical interface is defined on the physical interface, a host interface corresponds to a physical interface (physical port). If, on the other hand, several logical interfaces are defined on one physical interface, a host interface corresponds to one logical interface.

In the case of the unfixed logical path number mode, the logical path control table LPT is generated in the following manner. When the voltage switch is turned on, each of the channel adapters 21 a to 21 c instructs the resource manager 23 to assign a logical path number to each host interface connected to the corresponding channel adapter. The resource manager 23 assigns a free logical path number to the host interface in response to the assignment request, and registers the channel adapter number (CA number) and the host interface number in the logical path control table LPT in accordance with the logical path number. This logical path control table LPT is created by now performing this registration for all channel adapters. In Fig. 14, the host interface is 0 of the channel adapter 21 a logical path number 0 assigned to the logical path number 1 is Interface Host 0 of the channel adapter 21 associated with b of the logical path number 2, the host interface 1 of the channel adapter 21b assigned,. , , (the same rule applies to the following accordingly).

If a host interface of a channel adapter is added, the channel adapter prompts the resource manager 23 to assign a logical number to the added host interface. The resource manager 23 then assigns a free logical path number to the host interface in the same manner and registers the channel adapter number (CA number) and the host interface number in the logical path control table LPT in accordance with the logical path number. , , , additional dynamic allocation

If a particular host interface of a channel adapter is removed or a channel adapter itself is removed from the auxiliary I / O system (for repair reasons, for example), the resource manager 23 removes the logical path number (s) that were assigned to the corresponding host interfaces , , , , dynamic elimination.

With this method of assigning the logical path numbers, a logical path number is assigned if the event requires it, for example when the I / O auxiliary system is started or when an additional device (additional interface) is added. For this reason, the logical path numbers can vary depending on the switch-on order of the voltage switches in the CPU or the I / O subsystem. Normally this is not a problem, but if an error is caused, it is difficult to recreate the same environment for analyzing the error or replaying the error. As a countermeasure, a non-volatile memory area is provided to store the logical path control table LPT. In addition, the switch SW, which can be operated externally by a maintenance person, for example, is provided on the maintenance control panel 26 , as described above.

If the switch SW is switched off, one is issued each time it is issued A logical path number assignment request from a channel adapter is a logical one Path number assigned as previously described (dynamic assignment). Will the switch SW, on the other hand, is the same logical path number as defined by the in table information stored in the non-volatile area is marked, assigned. The switch SW is turned on when the maintenance person is stationary assigns logical path number. , , , fixed logical path number mode.

(b-3) Exclusive control table

The exclusive control table ECT stores the occupancy data, which indicates whether an I / O device (semiconductor memory module) is used. In addition, reservation data indicating whether an I / O device (semiconductor memory module) is reserved, path group information (path name), etc. are stored in accordance with a logical path number as shown in FIG. 15. The exclusive control table ECT is provided for each semiconductor memory module.

If a host interface uses a semiconductor memory module 31 , a flag "1" is set in the column of the occupancy data on the line of the logical path number of the host interface. When the use of the semiconductor memory module 33 is finished, the flag "1" is reset to "0". When a host interface issues a reservation command to use a particular semiconductor memory module 32 exclusively, a flag is set to "1" in the reservation data column and in the line of the host interface logical path number. If the reservation command is withdrawn, the flag is reset from "1" to "0". Even if another host interface issues a request to access the semiconductor memory module 33 , the answer is "busy" as long as the flag in the reservation data column is set to "1".

(b-4) Assignment of the logical path number

Figure 16 is a logical path mapping view when a host interface corresponds to a physical interface. The physical interfaces placed on each channel adapter 21 a to 21 c serve as host interfaces, and the logical path control table LPT, as shown in FIG. 17, is generated by the logical path number assignment control.

FIGS. 18A and 18B are views of logical path assignment if a host interface corresponds to a logical interface. The channel adapter 21 b is an adapter for an OC connection and a physical interface 21 b 'is connected to four CPUs 20 a to 20 d via a changeover switch / amplifier 28 . That is, four interfaces 29 are defined on the one physical interface 21 b '. In such a case, a host interface corresponds to a logical interface, and a logical path number is assigned to each of the host interfaces (0 to 3). If it is assumed that the channel adapter 21 shown in Fig. 16 b with each CPU, as shown in Fig. 18A, is connected to the logical path control table LPT how generates, by the logical path number mapping control shown in Fig. 18.

FIG. 19A to 19C are views of a logical path number allocation control in an access system. If the CPU 20 b with the channel adapter 21 via a physical interface 21 b '(see Fig. 19A) is connected, two machine addresses on the semiconductor memory module 22 are a set through an access. Due to the access, the CPU 20 behaves as a two virtual machines VM1, VM2, so that each virtual machine over a physical interface 21 b on the semiconductor memory module 22 can send an access request Vm1 and VM2 'a. This means that two logical interfaces on one physical interface 21b '(see Fig. 19b) are defined. Since a host interface corresponds to a logical interface, a logical path number is assigned to each of the host interfaces (0 and 1). Therefore, if the CPU, which with the physical interface of the channel adapter 21b in Fig. 16 is connected, two sets accesses, the logical path control table LPT shown in Fig. 19C is generated.

(b-5) Logical path number assignment control

Fig. 20 is a flowchart showing the processing by the resource manager 23 in a logical path number assignment control.

When the power source of the resource manager 23 is turned on, a function program is started to check whether the switch SW is on or off after the initial diagnosis (step 201 ) is carried out. If the switch SW is turned off, the contents of the logical path control table LPT are initialized (step 202 ), while they are not initialized if the switch SW is turned on.

Regardless of whether a request for assigning a logical path number (assignment request command + CA number + host interface number) is issued by a channel adapter, this is checked (step 203 ) and if the answer is YES, it is checked whether the switch SW is on or off (step 204 ). If the switch SW is turned off, a new logical path number is dynamically allocated, and the logical path number is registered in the logical path control table LPT in accordance with the CA number and the host interface number (step 205 ). Subsequently, the channel adapter that issued the mapping request is informed of the logical path number (step 206 ), and the flow returns to step 203 to repeat the subsequent processing.

If the switch SW is turned on in step 204 , the logical path number is retrieved from the logical path control table LPT based on the CA number and the host interface number contained in the mapping request (step 207 ). The channel adapter that issued the mapping request is then informed of the recovered logical path number (step 106 ). The flow then returns to step 203 to repeat the subsequent processing.

The logical path numbers are serial numbers that all host interfaces in the I / O subsystem are assigned.

Fig. 21 is a flowchart showing the processing of the channel adapter 21 a to 21 c in the logical path number assignment control. If the power supply is switched on, a logical path number of the host interface that corresponds to a physical interface or the logical path number of the host interface that is assigned to an access is registered.

If the voltage source of a certain channel adapter is switched on, a function program is started after the initial diagnosis. The channel adapter counts and confirms the number of host interfaces connected to it and prompts the resource manager 23 to assign a logical path number to an i-th host interface (step 301 ). The mapping request consists of a mapping request command, a CA number, and an interface number.

It is then checked whether the resource manager 23 has informed the channel adapter of the logical path number (step 302 ). If the answer is yes, the channel adapter registers the logical path number received from the resource manager 23 in the logical path control table in accordance with the host interface number (step 303 , see Fig. 22A). It is then checked whether the assignment of a logical path number with regard to all host interfaces has been completed (step 304 ). If the answer is NO, the processing at step 301 is repeated with respect to the (i + 1) th host interface. In this way, the logical path numbers of all host interfaces are registered.

In the case of an OC connection, logical interfaces are defined during the operation of the system. Fig. 23 shows a flowchart of processing by a channel adapter in the logical path number assignment control in this case.

A channel adapter for an OC connection checks whether a CPU has instructed the establishment of a connection (step 401 ). If YES, the OC connection number is registered in accordance with the host interface number (step 402 , see Fig. 22B). The channel adapter then prompts the resource manager to assign a logical path number to the host interface (step 403 ).

It is then checked whether the resource manager 23 has communicated the logical path number to the channel adapter (step 404 ). If YES, the channel adapter registers the logical path number received from the resource manager 23 in the logical path control table in accordance with the interface number and the OC connection number (step 405 ) as shown in Fig. 22B. The flow returns to step 401 to repeat the subsequent processing.

(b-6) Exclusive control

Fig. 24 is a flowchart of exclusive control.

If an access request (read / write command) is transmitted from a specific CPU to a specific channel adapter via a host interface (step 501 ), the channel adapter specifies the physical interface and the logical interface that issued the request, the host recognizes Interface number and obtains the logical path number from the logical path control table based on the host interface number (step 502 ). The request to use the I / O device (semiconductor memory module) with the added logical path number is transmitted to the resource manager 23 (step 503 ). The resource manager 23 is then waited for (step 504 ). When the resource manager 23 receives the request to use the I / O device, it is checked whether the semiconductor memory module is occupied or reserved by another logical path (host interface) by referring to the exclusive control table ECT (step 505 ). If the module is neither busy nor reserved, a flag in the exclusive control table ECT is set to "1", which means "busy", in accordance with the logical path number added to the usage request (step 506 ). The resource manager 23 then provides permission to use the I / O device to the channel adapter that issued the usage request (step 507 ). If the semiconductor memory module is in use, the resource manager 23 answers the channel adapter negatively ("busy").

When the channel adapter receives permission, the data is transferred between the CPU and the semiconductor memory module (step 508 ) and when the access is complete, the channel adapter informs the resource manager 23 of the end of use (step 509 ) and the CPU of the command end (Steps 510 ).

When the resource manager 23 is informed of the end of use, it changes the flag from "1" to "0", which means "free", with which the exclusive control is ended.

(b-7) Other controls

Sometimes a CPU is newly added to a computer system, for example to do this Enlarge system. If the new CPU uses the existing I / O subsystem, it is necessary to add an interface or a channel adapter to the auxiliary I / O system. After adding an interface / channel adapter, a request for the Assign a logical path number in the same way to the resource manager issued, as when switching on the power supply. A new logical path number is assigned and registered. Then the channel adapter / interface as an object the exclusive control.  

If an error occurs in part of the hardware and the adapter from the I / O subsystem is removed to be serviced or repaired, the data stored in the area in the logical path control table LPT are registered which are related to the logical path number of the channel adapter, deleted.

Such addition or removal of a logical path number during the operation of the Systems does not affect the operation of one interface through another logical path number is executed. It is therefore possible to add an additional device To change modules and to maintain a module while the auxiliary I / O system is operating and of the entire computer system continues.

In the logical path number assignment method in the present invention The logical path numbers can vary depending on the switch-on sequence of the Supply switch in the auxiliary I / O system, even if the internal structure (the number of Channel adapter, the number of interfaces) of the I / O subsystem is the same. in the practical operation, this is not a problem, but if an exclusive control Error occurs in part of the hardware or a microprogram, it is necessary that Analyze the problem and reproduce the error. In such a case, it is important to create the same environment. For this reason, the previously described switch SW switched on to fix the logical path numbers, so that the mode on the fixed logical path number mode is switched. This operation secures the same assignment of logical path numbers. In the fixed logical path number mode it is possible to assign a new logical path number. If, however, a logical one Path number is eliminated due to an error or the like, the logical Path number not removed from the logical path control table LPT. This is because the same logical path number is assigned to the module after it is repaired. Of a control method can also be introduced by switching the switch SW to ON is held after the system is set up for use.

(b-8) Structure of Current Semiconductor Plate Device

Fig. 25 shows the entire structure of a semiconductor disk device as an I / O subsystem. The semiconductor disk device has a dual structure, wherein modules with an index 1 belong to a first semiconductor plate device G0, modules with an index 2 belong to a second semiconductor plate device G1, and modules with no index are shared.

The symbol CA represents a channel adapter that acts as an interface to and from one Serves host device. Various duct adapters that form an electrical duct correspond, an optical channel and an OC connection are provided, provided required. A resource manager RM performs the logical path control and Exclusive control and manages all resources of the auxiliary system. A service adapter SA serves as a master that controls the states of the other units.

A C-BUS is a control bus through which each unit transmits messages and access on control information. A D-BUS is a data transfer bus through which each unit Sends data to or from a semiconductor disk, and an S-BUS is on Service bus, via which a service module as master controls the status of each unit. The Symbols BH-1 and BH-2 represent bus controllers (handlers) to the competition control the buses or feed the bus clock. The MDK symbol denotes one Magnetic disk device for temporarily storing (backup) the memory contents, if one Problem occurred, DA marks a device adapter that acts as an interface between the magnetic disk device and the channel adapter DA, and BANK indicates a semiconductor disk (shared memory) that has a maximum of 10 Semiconductor memory modules can accommodate MSs.

The symbols ESP1 to ESP4 indicate ports (additional memory ports) for controlling the Access to the semiconductor disks, ESA1 to ESA4, characterize memory interface adapters to carry out a synchronization control between the semiconductor memory modules MSs, memory refresh and data correction based on an error check code, and PANEL denotes a maintenance control panel.  

The first and second semiconductor plate devices G0 and G1 have a symmetrical structure with respect to the broken line in Fig. 25. A host CPU is symmetrically connected to the channel adapters CA ₁ and CA _{2 of} the first and second semiconductor devices, and the respective ports ESP2 and ESP3 are connected to the memory interface adapters ESA3, ESA4 on the other side. Therefore, even if there is a problem on one side in a channel adapter, the CPU has access to the semiconductor plate through a channel adapter on the other side. Even if a problem occurs on one side in a semiconductor plate, it is possible to access the semiconductor plate on the other side. This increases reliability.

In this embodiment, an exclusive control method in one Semiconductor disk device explained as an auxiliary I / O system. An exclusive control process However, the present invention is not limited to this, but can also be in one I / O auxiliary system, for example a magnetic disk device or a disk cash, be applied.

(c) Embodiment of a data storage control method of the invention (c-1) Overall structure

Fig. 26 shows the structure of an embodiment of a data storage control method for storing compressed data in a semiconductor memory module of a semiconductor disk device according to the present invention. Reference numeral 30 denotes a host device such as a CPU, 31 a channel adapter for controlling the data input / output operation between the host device (CPU) 30 and a memory interface adapter ESA, 32 a resource manager for performing exclusive access control to a semiconductor memory module, 33 a to 33 n semiconductor memory modules, each being composed of a plurality of semiconductor memory chips, 33 s a free semiconductor memory module, 34 a memory interface adapter for controlling the writing and reading of data into or from a semiconductor memory module, 35 a data control adapter for verifying the compressed ones Data written in a semiconductor memory module, 36 a backup disk device, 37 a backup disk adapter, and 38 an internal data bus. The channel adapter 31 and the data control adapter 35 have a data buffer 31 a with a large capacity and a data compression mechanism 31 b or a data buffer 35 a and a data compression mechanism 35 b. The backup disk adapter 37 has a data compression mechanism 37 a.

When data is stored in a semiconductor memory modules 33 a to 33 n (hereinafter referred to as "semiconductor memory module" 33 hereinafter) in the I / O subsystem, compressed, the data compression mechanism 31b of the channel adapter 31, the compressed in the data buffer 31 a stored data and writes Data in the semiconductor memory module 33 . The data before compression (uncompressed data), which are stored in the data buffer 31 a, are written in the additional semiconductor memory module 33 s.

After writing this data, the data compression mechanism 35 b of the data control adapter 35 reads out the compressed data from the semiconductor memory module 33 and stores it again so that it is stored in the data buffer 35 a. The uncompressed data are then read out from the additional semiconductor memory module 33 s in order to verify the compressed data written into the semiconductor memory module 33 by comparing the data which have been stored again with the uncompressed data. If a request to access the data is made by any channel adapter during the comparison and verification, the resource manager 32 replies "busy".

If an error or an abnormality is detected as a result of the data comparison, the data control adapter 35 compresses the data read out from the additional semiconductor memory module 33 s and writes this compressed data into the semiconductor memory module 33 . Thereafter, the compressed data is restored and the restored data is compared with the uncompressed data to verify the compressed data written in the semiconductor memory module 33 . The result (comparison error flag, recovery flag or the like) of the verification is recorded in the directory area at the head of the track of the semiconductor memory module 33 . A flag indicating whether the data is compressed is added to the header of each date. The directory area contains, in addition to the result of the verification, logical address information, physical memory address information, a compression flag indicating that the data has been subjected to compression, and the latest date (update information) on which the data on the track was changed or written were.

If the semiconductor memory module 33 overflows while writing the compressed data (for example, if the size of the compressed data is larger than the size of the uncompressed data), the channel adapter 31 stores the uncompressed data in the backup disk device 36 via the backup disk adapter 37 . After storage, the backup disk adapter 37 reads the uncompressed data from the backup disk device 36 and writes it into the semiconductor memory module 33 .

If the data stored in a semiconductor memory is stored (backup-stored) in the backup disk device 36 , the data is compressed by the backup disk adapter 37 and stored in the backup disk device 36 . When the data is read out of the backup disk device 36 , it is restored. In this case, the backup completion date is stored, and if the data stored in the semiconductor memory 33 is back-stored again, the date contained in the directory area is compared with the backup completion date so as not to store the data older with respect to the backup completion date. This shortens the backup time.

(c-2) Structure of a duct adapter

Fig. 27 shows the structure of a channel adapter 31st The channel adapter 31 contains a data buffer 31 a with a large capacity for storing the transmitted data, the data compression mechanism 31 b for compressing / restoring the data transmitted between the channel interface and the internal bus interface, a dictionary memory 31 c for assisting the compression / restoration operation, a channel interfaces -Protocol controller 31 d, a selection device 31 e for the selective output of the data from the data buffer 31 a and the data compression mechanism 31 b and for the selective input of the data into the data buffer 31 a and the data compression mechanism 31 b, an internal bus interface controller 31 f, which with the internal Bus 38 is connected, an MPU 31 g for controlling this hardware equipment by a microprogram, a control memory 31 h for storing the program and a bus 31 i.

The channel interface protocol controller 31 d analyzes the content of the command transmitted between the channel adapter and the host device and controls the transmission of the data based on a certain sequence in the interface. When the channel interface protocol controller 31 d receives the data to be stored in the semiconductor memory module 33 from the host device, the channel interface protocol controller 31 d briefly stores the data in the data buffer 31 a with a large capacity. The data compression mechanism 31 b compresses the input data from the data buffer 31 a. The selector 31 e selects the data compressed by the data compression mechanism 31 b or the original data (uncompressed data) stored in the data buffer 31 a under the control of the MPU 31 g, and executes them as input signals to the internal bus interface controller 31 f to. The internal bus interface controller 31 f, which has received the data coming from the selection device 31 e, transmits this data to the memory interface adapter 34 . During writing, the compressed data from the compression mechanism 31 via the data selector 31 e, the internal bus interface 31 f and the memory interface adapter are written into the semiconductor memory module 33 34th The uncompressed data are written into the additional semiconductor memory module 33 f via the data buffer 31 a, the selection device 31 e, the internal bus interface 31 f and the memory interface adapter 34 .

On the other hand, if the data written in the semiconductor memory module 33 is transferred to the host device, the selector 31 e selectively guides the data to the data compression mechanism 31 b or the data buffer 31 a depending on the identification flag that was written shortly before the data, to indicate whether the data is compressed or uncompressed. That is, if the data that the internal bus interface controller 31 f receives from the memory interface adapter 34 is compressed data, the selector 31 e delivers the data to the data compression mechanism 31 b, whereas it is delivered to the data buffer 31 a if it is uncompressed data. The data compression mechanism 31 b restores the compressed data and stores it in the data buffer 31 a. The data stored in this data buffer 31 a are transmitted to the channel interface protocol controller 31 d and via the channel interface to the host device.

(c-3) data control adapter

Fig. 28 shows the structure of the data control adapter 35th The data control adapter 35 includes the data buffer 35 a with a large capacity, the data compression mechanism 35 b for compressing / restoring the data to be transferred, a dictionary memory 35 c for assisting the compression / restoration operation, an internal bus interface controller 35 b, which is connected to the internal bus 38 is a data comparator 35 e for verifying compressed data by comparing the compressed and restored data with the original uncompressed data, a selector 35 f for selectively outputting the input data to the data compression mechanism 35 b or the data comparator 35 e depending on whether it is when the data input from the internal bus interface controller 35 d is compressed or uncompressed data, an MPU 35 g for controlling these hardware resources by means of a microprogram, a control memory 35 h for storing the program and e a bus 35 i.

When the channel adapter 31 has finished writing the compressed data into the semiconductor memory module 33 and the uncompressed data into the additional semiconductor memory module 33 s, the data control adapter 35 reads out the compressed data. These compressed data are used as input data to the data compression mechanism 35 b via the internal bus interface 35 d and the selection means 35 f supplied. The data compression mechanism 35 b restores the compressed data and stores the restored data in the data buffer 35 a.

The data control adapter 35 then reads out the uncompressed data stored in the additional semiconductor memory module 33 s. These uncompressed data are transmitted to the data comparator 35 e via the internal bus interface controller 35 d and the selection device 35 f. The data comparator 35 e compares the restored data which are stored in the data buffer 35 a with the uncompressed data which have been read out from the additional semiconductor memory module 35 s.

If an abnormality or an error is recognized as a result of this comparison, the data is repaired in the following manner. The uncompressed data are read out again from the additional semiconductor memory module 33 s and stored in the data buffer 35 a via the internal bus interface controller 35 d and the selection device 35 f. After the reading of the uncompressed data has ended, the data compression mechanism 35 b compresses the data stored in the data buffer 35 a and writes the compressed data into the semiconductor memory module 33 via the selection device 35 f and the internal bus interface controller 35 d. After the compressed data has been written in, the data comparison is carried out again in the manner described above in order to confirm the normality of the data.

(c-4) Backup disk adapter

Fig. 29 shows the structure of the backup plate adapter 37th The backup disk adapter 37 comprises a data compression mechanism 37 a for compressing / restoring data, a dictionary memory 37 b for assisting the compression operation, an internal bus interface controller 37 c for controlling the data transfer via an internal bus interface, a magnetic disk interface controller 37 d, which is connected to the backup disk device 36 is connected, a selector 37 e for selectively outputting the data input through the internal bus interface 37 c to the data compression mechanism 37 a or the magnetic disk interface controller 37 d and selectively outputting the output of the data compression mechanism 37 a or the magnetic disk interface controller 37 d to the internal bus interface controller 37 c, an MPU 37 f for controlling these hardware resources by means of a microprogram, a control memory 37 g for storing the program and a bus 37 h.

When the backup storage of the data stored in the semiconductor memory module 33 is started, the data received via the internal bus interface controller 37 c is transmitted to the data compression mechanism 37 c by the selection device 37 e. The data compression mechanism 37 a compresses all data including those data that have already been compressed by another data compression mechanism, and transmits this compressed data to the magnetic disk interface controller 37 d. This magnetic disk interface controller 37 d the received data writes to the backup disk device 36 without considering whether it is compressed or uncompressed data. It is possible to write data to the backup disk device 36 by operating the selector 37 e without having the data compressed by the data compression mechanism 37 a.

(C-5) data format

A conventional auxiliary I / O system uses the same data format as that used in a normal magnetic disk 43552 00070 552 001000280000000200012000285914344100040 0002004447853 00004 43433 as shown in Fig. 6 to emulate a magnetic disk. The symbol DIR represents a directory that is inscribed at the head of a track field. This date is typical of a semiconductor disk and does not exist in a current magnetic disk device. After the directory DIR, several data fields Ri are written, each of which is composed of a counting area Ci (i = 1, 2,...), A key area Ki and a data area Di. The count area Ci records a record number and the lengths of the subsequent key area Ki and the data area Di. The key area Ki is not always necessary, but records a key for searching in an access method. The data area Di records data which are generally referred to as user data.

In the present invention, the data in the semiconductor memory module 33 is compressed, with the directory area DIR, the count area Ci and the key area Ki removed (for example only the data area Di). The semiconductor plate device eliminates as many unnecessary gap areas as possible, instead, additional information for the semiconductor plate is written in the area corresponding to a gap.

Fig. 30 shows the data format which is written according to the present invention, in a semiconductor memory module. In this data format, an identification flag Fi for distinguishing between compressed and uncompressed data is written after the directory area DIR, the count area Di and the key area Ki, and data Di 'compressed by the data compression mechanism is written after the identification flag Fi.

The directory area DIR comprises logical address information d1, physical memory address information d2, a compression flag d3 which indicates whether the data has been subjected to compression, the most current date d4 (update information) on which the data in the track area was changed or written , a backup disk usage flag d5, which indicates that part of the data on the track is stored on the backup disk 36 , and a comparison error flag d6 and a recovery success flag d7, which are the result of the verification by the data control adapter Mark 35 .

(c-6) Data write control

Fig. 31 is a view of the operation of the data write control.

A semiconductor device is accessed by an auxiliary device in the same manner as on a magnetic disk with high speed access. That is, a positioning command, which specifies the position for the search or the like, a read command and a write command for Perform data transfer from a host device in the same way be released as in the case of a conventional magnetic disk.

The channel adapter 31 , which has received a positioning command, requests the resource manager 32 to allow the use of a semiconductor memory module. If the use of the semiconductor memory module is permitted, the address of the corresponding semiconductor memory module is calculated from the selected physical positioning parameter. The directory information of the track in which the obtained address exists is read out from the semiconductor memory module. Processing on the logical address information and the physical address information is carried out.

When a write command is issued from the host device after the positioning operation is completed, the channel adapter 31 stores the data received through the channel interface protocol controller 31 d in the data buffer 31 a. The MPU 31 g of the channel adapter 31 controls the selector 31 e, to the output side of the data compression mechanism b select 31 when the data corresponds to the data area d i.

The data compression mechanism 31 b compresses the input / output data stored in the data buffer 31 a and passes this compressed data as input data to the internal bus interface controller 31 f. This compressed data is in turn transmitted to the memory interface adapter 34 via the internal bus and stored in the address area which corresponds to the specific semiconductor memory module 33 .

When the compressed data are stored, writes the MPU 31 g of the channel adapter 31, the identification flag Fi, which indicates that the data is compressed corresponding to the semiconductor memory module 33 to the data format. The MPU 31 g also controls the selection device 31 e in order to transmit the original data (uncompressed data), which are stored in the data buffer 31 a, to the internal bus interface controller 31 f, and writes them into the additional semiconductor memory module 33 s.

After completing the registration, the MPU 31 g updates the update information, the identification flag which indicates that the data is compressed and the like in the directory area DIR. After renewing the directory area DIR, this is written back to the head of the track of the corresponding semiconductor memory module 33 .

After all write operations with regard to the semiconductor memory module 33 and the additional semiconductor memory module 33 s have been carried out by the channel adapter 31 , the resource manager 32 prevents access by a host device to the corresponding data for a specific time, by the exclusive control with "busy" is answered. The resource manager 32 then commands the data control adapter 35 to begin verifying the compressed data.

The MPU 35 g of the data control adapter 35 reads out the directory area DIR of the compressed data from the semiconductor memory module 33 , and continues to read out the compressed data. The data transmitted by the semiconductor memory module 33 are fed to the data compression mechanism 35 b as input data via the internal bus interface controller 35 d and the selection device 35 f.

The data compression mechanism 35 b restores the input data and stores it in the data buffer 35 a. The data compression mechanism 35 b then reads the uncompressed data from the additional semiconductor memory module 33 s and feeds this uncompressed data as input data to the data comparator 35 e. The data comparator 35 e compares the restored data with the uncompressed data.

If the normality of the data is confirmed as a result of the comparison, the data control adapter 35 informs the resource manager 32 of the normal end of the write operation without performing any processing, such as restoring the directory area DIR. The resource manager 32 , which has received the information, removes the temporary ban on accessing the data with a host device.

If an abnormality or an error in the data is recognized as a result of the data comparison, the MPU 35 g of the data control adapter 35 reads out the uncompressed data from the additional semiconductor memory module 33 s. The data compression mechanism 35 b compresses the data on the basis of the uncompressed data read out and writes the compressed data into the semiconductor memory module 33 . When the compression of the compressed data is finished, the data control adapter 35 performs the data verification described above. If the normality of the compressed data stored in the semiconductor memory module 33 is again confirmed by the second verification, both the comparison error flag d6 and the normality recovery flag d7 are set to "1" in the directory area DIR of the compressed data. Then the directory area DIR is written back into the semiconductor memory module 33 . As soon as the restore of the directory area DIR has ended, the resource manager 32 is informed of the end of the verification, whereby the process is ended. The resource manager 32 then removes the temporary ban on the host device from accessing the data.

On the other hand, if an abnormality is detected as a result of the data recovery, the data control adapter 35 sets the comparison error flag d6 (not the normality recovery flag d7) to "1" and writes the directory area DIR back to the semiconductor memory module 33 . As soon as the directory area DIR has been restored, the resource manager 32 is informed of the end of the verification, whereby this process ends. The resource manager 32 then removes the temporary ban on a host device from accessing the data.

The sequence described above can then be used as long as a semiconductor memory module does not overflow. Fig. 32 is a view of the operation of the data write control in the event that a semiconductor memory module overflows.

If the compressed data is larger than the original data, it is sometimes physically impossible to write the compressed data into a selected semiconductor memory module 33 . In such a case, the resource manager 32 is informed of an error due to the area overflow. When the resource manager receives this error information, the channel adapter 31 is instructed to suspend writing the compressed data to the semiconductor memory module 33 and instead to write the uncompressed data to the backup disk device 36 . The channel adapter 31 then interrupts the writing of the compressed data into the semiconductor memory module 33 and starts the short-term storage of the uncompressed data in the backup disk device 36 . The backup disk adapter 37 then switches the selector 37 e to write the data transferred from the channel adapter 31 via the internal bus interface to the backup disk device 36 without compression. Since a sufficiently large area is temporarily allocated for short-term storage in the backup disk device 36 , there is no possibility that the user data already stored as backup data will be damaged.

As soon as the writing into the backup disk device 36 has ended, the MPU 31 g of the channel adapter 31 writes the uncompressed data stored in the data buffer 31 a into the additional semiconductor memory module 33 s via the internal bus interface controller 31 f. After this operation, the MPU 31 renews g of the channel adapter 31, the update information is d4, the compression flag d3, which indicates that the data is compressed, and the flag d5, which indicates that the data stored in the backup disk device 36 and writes the renewed directory area DIR back to the semiconductor memory module 33 .

Once the writing is completed in the backup disk device 36, the backup disk adapter calls 37 the resource manager 32, to allow the use of the semiconductor memory module 33 to the uncompressed data to be written that are briefly stored in the memory module 33rd If the use of the semiconductor memory module 33 is permitted, the backup disk adapter 37 reads out the uncompressed data from the backup disk device 36 and writes it into the semiconductor memory module 33 . When the enrollment is complete, the backup disk adapter 37 informs the resource manager 32 of the end of the enrollment, thereby completing the process. The resource manager 32 then removes the temporary ban on a host device from accessing the data.

(C-7) data read control

Fig. 33 shows an explanatory illustration of the sequence of data reading control.

The channel adapter 31 , which has received a positioning command, requests the resource manager 32 to allow the use of a semiconductor memory module in the same way as when writing. If the use of the semiconductor memory module is permitted, the address of the corresponding semiconductor memory module is calculated from the selected physical positioning parameters. The directory information of the track in which the received address occurs is read out from the semiconductor memory module. Then processing is performed on the logical address information and the physical address information.

When a read command is issued from the host device after completion of the positioning, starts the MPU 31 g of the channel adapter 31 with the reading of the data from the semiconductor memory module 33 in which the data is stored. The MPU 31 g checks whether the data is compressed or uncompressed by referring to the identification flag Fi. If the data is compressed, provides the MPU 31 g of the compressed data through the internal bus interface 31 f and the selector 31 e to the data compression mechanism 31 e. The data compression mechanism 31 b restores the data and transfers it via the data buffer 31 a and the data interface protocol controller 31 d to the channel interface. On the other hand, if the data is uncompressed, the MPU 31 g stores the uncompressed data directly in the data buffer 31 a. The MPU 31 g then transmits the data to the channel interface via the data interface protocol controller 31 d.

In the above-mentioned read operation, the MPU 31 checks g of the channel adapter 31 sets the state of the data based on the contents of the directory area DIR. That is., That the MPU g 31 the status of the data checks based on the flag d5 to d7, which were written by the channel adapter 31 or the data control adapter 35 at the time of data registration, and transmits the status to the host device. For example, if the backup use flag d5 is set to "1", the normal data can be read out. However, since there is a risk of an area in the semiconductor memory module being too small, a warning is issued. When the comparison error flag d6 is set to "1" and the recovery flag d7 is set to "0", the abnormal data is notified in the same manner as in the data verification so that the data is rewritten and transmitted become.

(C-8) backup control

Since a semiconductor memory is a volatile recording medium, the Data in the semiconductor memory is backed up in a magnetic disk device (backup), if that System is stopped or in an emergency. This is the Magnetic disk device around a non-volatile recording medium.

As shown in FIG. 34, areas 36 a n up to 36 and 36 s, said semiconductor memory modules 33 a n to 33 and 33 s correspond, and a temporary storage area 36 p in advance of the backup disk device 36 assigned to it. Each of the areas 36 a to 36 n and 36 s is ultimately divided into areas for tracks, each of which corresponds to the track emulated in the semiconductor memory module. The backup disk device 36 also includes areas 36 q and 36 r for storing the time at which the backup operation ends and the time at which the write-back operation (operation to restore the data from the backup disk device to the semiconductor memory module) ends. If a backup operation is to be carried out, the backup disk adapter 37 outputs the data transmitted from the semiconductor memory modules 33 a to 33 n and 33 s via the internal bus interface controller 37 c and the selection device 37 d to the data compression mechanism 37 a. The data compression mechanism 37 a compressed together the input data and writes the compressed data in the corresponding areas of the backup disk device 36 via the magnetic disk interface controller 37 d.

The backup disk adapter 37 writes the date indicating the completion time of the backup operation in the area 36 q of the backup disk device 36 and internally reads and stores the date on which the data was written back. If a backup operation is normally instructed, the backup disk adapter 37 compares the stored time with the update information of the directory stored in the header of the semiconductor memory module track. If the date of the directory is older than the latest backup completion date, the date stored on the track is not written into the backup disk device 36 . In this way it is possible to shorten the backup time.

(c-9) modification

Although only one channel adapter 31 , one memory interface adapter 34 and one backup disk adapter 37 are used in the previously described embodiment, the number of these devices can be increased.

Although only one data control adapter 35 is provided in the semiconductor disk device in this embodiment, a plurality of data control adapters may be provided to enable parallel processing.

Although the data for each track is stored as a unit in the backup disk device 36 in this embodiment, the data for each cylinder or the data for each sector can be stored as a unit.

Although in this embodiment, an additional semiconductor memory module for storage uncompressed data is provided, a part of each semiconductor memory module as Additional semiconductor memory module can be used instead.

(c-10) advantages

Since, as previously described, some of the data is compressed before storage, it is possible a semiconductor disk device for storing a compared to the capacity a larger amount of data to provide a semiconductor memory.

Since a data buffer with a large capacity is provided inside the channel adapter it is possible to transfer data while respecting the data transfer speed of a host device is kept constant. This can reduce the strain that is caused will be alleviated if data is processed.

In addition, since a data control adapter is used, it is possible to restore the normality of the to verify compressed data within the auxiliary system without the connection with  a host device. Even if incorrect data as a result of the verification are recognized, it is possible to restore the data within the auxiliary system.

As update information in the directory area and in the backup disk device saved, the time required for the data backup is also reduced.

(d) Memory initialization (d-1) Schematic explanation of the initialization

FIG. 35A and 35B are explanatory views of a conventional Speicherinitialisierungsverfahrens, which is applied to a semiconductor disk or the like in a I / O subsystem. In Fig. 35A, the symbol INCT represents a conventional initialization address counter, where the symbols CA0 to CAn represent the column addresses of (n + 1) bits, and RA0 to RAm the row addresses of (m + 1) bits. A dynamic RAM, which is volatile memory, is supplied with both the row addresses which represent an address in the row direction of the memory and with column addresses which identify an address in the column direction of the memory. In the conventional initialization address counter, the least significant bit of the counter output signal is CA0 and the most significant bit is RAM. With the help of the INCT counter, serial address signals are generated in ascending order. Initialization data are written into the memory cells in the counter INCT, the sequence being indicated by the arrows with solid lines in FIG. 35b.

The dynamic RAM must be refreshed at constant time intervals. To refresh the dynamic RAM, the data of all the memory cells in a row identified by the address RA are read by a sense amplifier SA in the memory as shown in Fig. 36A and written back to the memory cells in the same row to

To keep the charges stored in the cells above a constant value. This operation is repeated at a constant interval with respect to the data of all lines. If this refreshing of the data is not carried out for all cells at a constant time interval, the data stored in the memory will be lost. If data is written into the memory, the effect is the same as that of refreshing. That is, if data is written into a cell 3 in Fig. 36B, the data in the row which is externally designated by the row address RA is read into the sense amplifier SA. After the data in the cell identified by the column address CA has been renewed by externally supplied data, all data are written back to the memory cells in the same row. In this way, the data write produces the same effect as refreshing the data in all cells of the row.

Referring now to Figure 35B. If the initialization data is sequentially written into the cells in the row of memory, the time to hold the charges expires before the data is written into the cells of the row, so that the charges in the cells of the row are lost. For this reason, the refresh explained in Fig. 36A is necessary during the initialization in the conventional memory initialization method, thereby extending the initialization time.

On the other hand, in the initialization address counter INCT of the present invention, as shown in Fig. 37A, the least significant bit of the counter output signal RA0 and the most significant bit CAn. By using this counter, the generated addresses are non-serial compared to those generated by a conventional counter, and data is continuously written into the memory cells in the order of the columns as indicated by the solid line arrows in Fig. 37b. According to this data writing method, the time for writing the data into the cells is up to and shorter than the interval between two refresh operations, so that the charges are stored in the memory cell unchanged until the data is written into the memory cell. At the time of writing the data into the memory cell, the memory cell that is on the same row as the memory cell is refreshed due to the refreshing effect explained in Fig. 36B. That is, according to the initialization method using the initialization address counter of the present invention, it is not necessary to perform refresh individually, thereby shortening the initialization time by this amount.

(d-2) Structure of the embodiments of the memory initialization method of the invention

Fig. 38 shows the structure of an embodiment of a Speicherinitialisierungsverfahrens the present invention. In Fig. 38, reference numeral 41 denotes volatile memory such as dynamic RAM that needs refresh, 42 an access controller, 43 an initialization address generator, 44 a data generator, and 45 an address switching area. In the Initialisierungsadreßerzeuger 43, reference numeral 43 denotes a an up counter by (n + 1) bits to output Initialisierungsspaltenadressen CA0 to CAn and 43b of an up-counter (m + 1) bits to output Initialisierungszeilenadressen RA0 to RAM. At the start of the initialization, both counters 43 a and 43 b output a logical zero. The data generator 44, the reference numeral 44 designate a is a register for storing the initialization data 44b, a selector for selecting the initialization data or the write data 44c and a data memory register. In Adreßumschaltbereich 45, reference numeral denote 45 a selection means for switching between a Initialisierungsspaltenadresse and a data access column address, 45b a selector for switching between a Initialisierungszeilenadresse and a data access row address and 45c a selection device for selecting a row address or a column address depending on a switch signal SWS.

Fig. 39 is a timing chart of the operation of the embodiment shown in Fig. 38, showing the operations of the counters 43 a, 43 b and the selector 45 c.

When the power switch is turned on, and an initialization signal IS is generated, the selector switch 44 b to a data signal DT from a host module as the input signal to a Initialisierungsschreibdatensignal IDT, which is output from the register 44 a, and stores the Initialisierungsschreibdatensignal IDT in the register 44 c. The selection device 45 a switches the column addresses CA0 'to CAn' as an input signal from a host module to the initialization column addresses CA0 to CAn as the output signal from the counter 43 a, and the selection device 45 b switches the row addresses RA0 'to RAm' as an input signal from the host Module to the initialization row addresses RA0 to RAm as an output signal from the counter 43 b.

An AND gate 43 c gives a clock signal CL to the counter 43 b and to an AND gate 43 d. Since a carry signal CRY from the counter 43 b remains in the state of a logic 0, the clock signal CL is not supplied to the counter 43 a. The counter 43 b counts up according to the clock signal CL. Since the switch signal SWS changes half of the clock signal period CL, the selector 45 c alternately outputs an address signal AD, which is composed of the row address RA and the column address CA, during a clock, as shown in FIG. 39. At this time, data is written in the order of the memory cells to, (in the serial order of the rows) in Fig. 37B. When the counter 43 b counts up and all initialization line address signals Ra0 to Ram become "1", the carry signal CRY of the counter 43 b is output and the AND gate 43 b is opened. The counter 43 a counts up at the next clock, and all output signals of the counter 43 b become logic "0". Therefore, the carry signal CRY is again logical 0. While the counter 43b counts up data are written in the order of the memory cell 3 to 4 in Fig. 37b. When the data is written in the second column, the memory cells 12 are refreshed due to the refresh effect described above.

This process is repeated and when all the output signals of the counters 43 a and 43 b become logic "1" (shown in FIG. 37B in cell), both carry signals CRY ', CRY of the counters 43 a and 43 b become "1". An initialization end signal IED is output as the output signal of an AND gate 43 e and the host module is informed of the end of the initialization of the memory 41 .

Fig. 40 shows the structure of another embodiment of a Speicherinitialisierungsverfahrens the present invention. In each memory module 40 ₁ to 40 ₄ , the same reference numerals are used for the elements that correspond to those of the exemplary embodiment shown in FIG. 38. In this exemplary embodiment, the access controller 46 can access each of the memory modules 40 ₁ to 40 ₄ separately from one another. For example, if the second memory module 40 ₂ is added from above because, for example, a printed circuit board is used, the access controller 46 transmits an initialization command signal ISTb in response to a request for initialization from a host module. The flip-flop 47 in the memory module 40 ₂ is then set and the access controller 42 in the memory module generates an initialization address, as previously described, in order to carry out the initialization of the memory. When the initialization has ended, an initialization end signal IEDb is delivered, the flip-flop is reset and the access controller 46 is informed of the end of the initialization. In this embodiment, since the refresh is not necessary during the initialization, and the initialization of the memory module 40 _{2 is carried out} as a single unit, the access controller 46 can access another memory module during the initialization between the transmission of the initialization command signal IEDb and the receipt of the initialization end signal IEDb ,

It is also possible to provide another access controller 46 (not shown) so that the two access controllers can individually access a plurality of memory modules 40 ₁ to 40 ₄ . If a memory module is added in this configuration, for example because a printed circuit board is used, one of the access controllers 46 s transmits the initialization command signals ISTa to ISTd. Then the initialization of the selected memory module is carried out as a single unit. Therefore, two access controllers 46 can process a request to access a host module even during the initialization of the memory module.

(d-3) Initialization procedure when high-speed access is possible

In order to carry out high-speed initialization, dynamic RAM which permits high-speed access, for example in a nipple mode and a high-speed side mode, is introduced. In nipple mode or high speed page mode, it is possible to read / write data in consecutive four memory cells in one row or any four cells in one row. Fig. 41 shows this structure of an initialization address counter used in a high speed page mode. The initialization address counter consists of a counter 51 of 2 bits, a counter 52 of (n - 1) bits, a counter 53 of (m + 1) and AND gates 54 to 56 .

A clock signal CL is constantly supplied to the counter 51 . A clock signal CL is supplied to the counter 53 only when a carry signal CRY1 is output from the counter 51 (all output signals of the counter 51 are logic "1"). A clock signal CL is supplied to the counter 52 when the carry signal CRY1 and a carry signal CRY3 are output from the counters 51 and 53 at the same time. The counter 51 outputs the lower 2 bits CA0, CA1 of the column address, the counter 52 outputs the upper (n - 1) bits CA2 to CAn of the column address, and the counter 53 outputs the row addresses RA0 to RAm of (m + 1) Bits out. If all the carry signals CRY1 to CRY3 of the counters 51 to 53 are output, the output signal IED of the AND gate 54 becomes logic "1", which indicates the end of the initialization.

The data is written into the memory cells in the order of 1 to 8 during the initialization by using the initialization address counter as shown in FIG. 42. The data written in the memory cells 11 to 12 are refreshed when the data are written in the memory cells 11 to 12. The time required for the data to be written into cells 1 to 4 is shorter than the interval between two refresh operations.

Fig. 43 shows the structure of a further embodiment of a memory initialization method according to the present invention, in which the memory 41 is divided into a plurality of memory blocks 41 a to 41 d. In this case, the address signal AD from a host module contains column address signals CA0 'to CAn', row address signals RA0 'to RAm' and a signal BSL for selecting a memory block. The selector 45 outputs one of selection signals d SLa to SLd from based on the signal BSL so that on one of the memory blocks 41 is a to 41 d, which have received the selection signal SLa to SLd, accessed. Selecting one of the memory blocks 41a to 41d simultaneously with the transfer of the address signal is required at the time of initialization. The initialization address counter 43 therefore has a structure as shown, for example, in FIG. 44. The initialization address counter 43 is generated by adding a 2-bit counter 57 , a decoder 58 for decoding the outputs of the counter 57, and AND gates 59a , 59b to the structure shown in Fig. 41, assuming that the high speed page mode described above is used.

A clock signal CL is constantly supplied to the counter 51 , and a clock signal CL is supplied to the counter 53 only when a carry signal CRY1 is output from the counter 51 . A clock signal CL is supplied to the counter 57 only when the carry signal CRY1 and a carry signal CRY3 are output from the counters 51 and 53 at the same time, and a clock signal CL is supplied to the counter 52 only when the carry signal CRY1 is a carry signal CRY2 and a carry signal CRY4 are simultaneously output by counters 51 , 52 and 57 .

In this initialization method using the initialization address counter 43 , the data is written into the memory cells in the order shown in FIG. 45. The internal cells of the memory blocks 41a to 41d , as shown in Fig. 43, are shown in Fig. 45. Data is written into the cells in the same manner as shown in Fig. 43. After the data is written into the cell, the output of the counter 57 and the memory block 41 changes b is selected so that the data are then written in the cell of the memory block 41b. Subsequently, data in the memory blocks 41 c and 41 d is written in the same way. When the writing of the data into the memory block 41d has ended, the memory block 41a is selected again, but since the counter 52 then counts up, the data are written into the memory cell. Since the cells are refreshed until while the data is being written into the cell bis, there is no possibility of losing the content of the memory cells bis.

(d-4) advantages

During the initialization, which requires a refresh, the generation of the Addresses the individual refresh operations according to a specific rule, which shortens the initialization time.

In addition, a host module and the access controller can perform the initialization without Impact the refresh. It can be prevented that the  Memory access performance is reduced due to the initialization, thereby reducing the Performance of the information processing device is increased.

As described above, according to the invention it is not necessary to have a large stationary one To prepare an exclusive control table for the maximum configuration of an I / O auxiliary system in Contrary to a conventional auxiliary I / O system. An exclusive control table is sufficient by listing only the host interfaces currently connected to the auxiliary I / O system are. It is therefore possible to reduce the size of the exclusive control table and thus also the memory requirement for this table. Since the logical path control table LPT in stored in a non-volatile memory that does not lose the content even then, when the power is turned off and a logical path number on the Based on the logical path control table LPT is assigned, it is possible to Restore a logical path number before the power failure, so that the same environment can be reproduced at the time the error was analyzed or a reproduction test of the error can be carried out. According to the invention, it is based on this Possible way to increase the performance of the I / O subsystem.

Since, according to the invention, part of the data is compressed before being stored, it is possible to to provide a semiconductor disk device for storing a large amount of data Comparison to the capacity of a semiconductor memory. At the time of data compression it is possible to compress data while the data transfer speed is kept constant with respect to a host device and thereby by the Compression of the data caused load is alleviated, since a data buffer with a large capacity is provided within the channel adapter. It is possible to normalcy to verify the compressed data within the auxiliary system without the connection with a host device. Even if abnormal data or error data as a result the verification are recognized, it is possible to restore the data in the auxiliary system. Since such data compression allows a large capacity of the data to be stored, it is possible to increase the performance of the auxiliary I / O system.

If, according to the invention, the initialization data are stored in volatile memory for each Line needs a refresh, the initialization data will be in  all memory cells of an i-th column are written while the row addresses are in succession RA are generated in an ascending order, with the column address CA on is kept at a constant value i. The step of writing the initialization data is in the same way for successive columns repeated while the column address CA is gradually increased. Because refreshing and data registration at the same time be carried out, it is not necessary to refresh separately from data registration to be carried out if the time required to enroll the data is shorter than the Period between two refresh operations. This shortens the Initialization time. If a high-speed memory is used, the Column addresses CA divided into an upper column address and a lower column address, and the initialization data is written into the memory cells while successively lower column addresses are generated in ascending order, whereby the upper column address and the row address RA are recorded. The Initialization data are then written into the following line in the same way. After the initialization data has been written in all lines, the letter is written of the data is repeated while the upper column address is incremented by one. With With this method, a separate refresh can also be avoided, which results in the initialization time is reduced. According to the invention it is possible in this way, the To increase the performance of the I / O subsystem.

Claims (17)

1. I / O auxiliary system with
a plurality of channel adapters, each having a single or multiple host interfaces to and from a host device ( 30 );
multiple I / O devices shared by the multiple host interfaces;
multiple device adapters that serve as interfaces to and from the I / O devices; and
a resource manager ( 32 ) for managing the resources of the auxiliary I / O system as a whole; full:
a semiconductor memory module ( 33 ) consisting of a plurality of semiconductor memory chips and serving as an I / O device ( 22 );
a memory interface adapter ( 34 ) which controls the writing and reading of the data into or from the semiconductor memory module ( 33 ), the memory interface adapter being provided as a device adapter;
a data compression / recovery mechanism (31 b), the data is compressed and restores compressed data; and
a verification device that restores the compressed data and verifies the compressed data by comparing the restored data with the data before compression.
characterized in that
the verification device which (31 b) reads out and verified by the data compression / recovery mechanism compressed data from the semiconductor memory module (33). 2. I / O auxiliary system according to claim 1, characterized in that
a data buffer ( 35 a) with a large capacity and a data compression mechanism ( 35 b) in the channel adapter ( 21 , 31 ) is provided;
the input data stored in the data buffer ( 35 a) is compressed by the data compression mechanism ( 35 b) and this compressed data is written into the semiconductor memory module ( 33 ). 3. I / O auxiliary system according to claim 2, characterized in that
the data stored in the data buffer ( 35 a) are written into an additional semiconductor memory module ( 33 ) before compression after the compressed data have been written into the semiconductor memory module ( 33 ); and
the data are read out from the additional semiconductor memory module ( 33 ) prior to compression in order to compare this data with the compressed data. 4. I / O auxiliary system according to claim 3, characterized in that
the data read from the additional semiconductor memory module ( 33 s) is compressed and written into the semiconductor memory modules ( 33 a- 33 n) if an abnormality is found as a result of the data comparison;
the data written into the semiconductor memory modules ( 33 a- 33 n) are read out and restored; and
the compressed data written into the semiconductor memory modules ( 33 a- 33 n) are verified by comparing the restored data with the data read out from the additional semiconductor memory module ( 33 s). 5. I / O auxiliary system according to claim 1, characterized in that a signal indicating the "busy" state is supplied by the exclusive controller ( 23 ) in response to the request to access the semiconductor memory module ( 33 ) during the data comparison. 6. I / O auxiliary system according to one of claims 1 to 5, characterized in that the I / O auxiliary system is a semiconductor disk device ( 20 ) by emulating a magnetic disk device. 7. I / O auxiliary system according to claim 6, characterized in that
a directory containing control information of records is written into a track area at the head of a track area corresponding to a track of a magnetic disk device, and the records are written after or after the directory;
a flag is added to each record indicating whether the data of that record is compressed or not; and
added to the directory: logical address information, physical memory address information, a compression flag indicating that the data is compressed, and the current date when the track area was changed or registered. 8. I / O auxiliary system according to one of claims 1 to 7, characterized in that
the (n 33 33 a-) data stored be saved in a backup plate means (36) in the semiconductor storage module;
the backup completion date is saved when the data stored in the semiconductor memory module ( 33 ) is saved in the backup disk device ( 36 );
the date contained in the directory is compared with the backup completion date when the data stored in the semiconductor memory is backed up; and
data that is newer than the backup completion date is backed up in the backup disk device ( 36 ) while older data is not backed up. 9. I / O auxiliary system according to one of claims 1 to 8, characterized in that
a backup disk device and a backup adapter for controlling the input and output of data to and from the backup disk device ( 36 ) are provided;
uncompressed data is stored in the backup disk device (36) when said semiconductor memory module (33 a- 33 n) during the writing of the compressed data becomes full because the size of the compressed data that of the uncompressed data exceeds; and
then the recompressed data is written into the semiconductor memory module ( 33 ) by the backup disk device ( 36 ). 10. A data storage method in an auxiliary I / O system with multiple channel adapters, each having a single or multiple host interfaces to and from a host device ( 30 );
multiple I / O devices shared by the multiple host interfaces;
multiple device adapters that serve as interfaces to and from the I / O devices; and
a resource manager ( 32 ) for managing the resources of the auxiliary I / O system as a whole; full:
a semiconductor memory module ( 33 ) consisting of a plurality of semiconductor memory chips and serving as an I / O device ( 22 );
a memory interface adapter ( 34 ) which controls the writing and reading of the data into or from the semiconductor memory module ( 33 ), the memory interface adapter being provided as a device adapter;
a data compression / recovery mechanism (31 b), the data is compressed and restores compressed data; and
a verification device that restores the compressed data and verifies the compressed data by comparing the restored data with the data before compression,
with the steps:
Compressing (31 b) of the data transmitted from the host device (30);
Verifying the compressed data by recovering the data sent from the host device ( 30 ) from the compressed data and comparing the recovered data with the data before compression;
characterized in that
the compressed data after the compression ( 31 b) is written into the semiconductor memory module ( 33 ) and read out for verification from the semiconductor memory module ( 33 ). 11. Data storage method according to claim 10, characterized in that
the data sent by the host device ( 30 ) are buffered in a data buffer ( 35 a) with a large capacity; and
the data stored in the data buffer ( 35 a) is compressed and this compressed data is written into the semiconductor memory module ( 33 ). 12. Data storage method according to claim 11, characterized in that
the data stored in the data buffer ( 35 a) are written into an additional semiconductor memory module ( 33 ) before compression after the compressed data have been written into the semiconductor memory module ( 33 ); and
the data are read out from the additional semiconductor memory module ( 33 ) prior to compression in order to compare this data with the compressed data. 13. Data storage method according to claim 12, characterized by the steps:
Compressing and writing the data read from the auxiliary semiconductor memory module ( 33 s) into the semiconductor memory modules ( 33 a- 33 n) when an abnormality is detected as a result of the data comparison;
Reading and restoring the compressed data are written in the semiconductor memory modules (33 a-33 n); and
Verification of the compressed data written in the semiconductor memory modules ( 33 a- 33 n) by comparing the recovered data with the data before compression. 14. Data storage method according to one of claims 10 to 13, characterized in that a signal indicating the "busy" state is supplied when a request to access the semiconductor memory module ( 33 ) is made during the data comparison. 15. Data storage method according to one of claims 10 to 14, characterized by the steps:
Writing a directory containing control information of records to be stored in a track area at the head of the track area corresponding to a track of a magnetic disk device and the records being written after the directory;
Adding a flag to each record indicating whether the data in the record is compressed or not; and
Adding the directory: logical address information, physical memory address information, a compression mark indicating that the data is compression objects and the last date when the data in the track field was changed or written. 16. Data storage method according to one of claims 10 to 15, characterized by the steps:
Providing a backup disk device ( 36 ) and a backup adapter ( 39 ) for controlling the data input and output operation to the backup disk device ( 36 );
Securing the in semiconductor memory modules (33 a-33 n) data stored in the backup Plattenvorichtung (36);
Storing the backup completion date when the data stored in the semiconductor memory module ( 33 ) is saved in the backup disk device ( 36 );
Compare the date in the directory with the backup completion date when the data stored in the semiconductor memory is backed up; and
Backing up newer data to the backup disk device ( 36 ) than the backup completion date while not backing up older data. 17. Data storage method according to one of claims 10 to 15, characterized by the steps:
Providing a backup disk device ( 36 ) and a backup adapter ( 39 ) for controlling the data input and output operation to the backup disk device ( 36 );
Storing uncompressed data of the uncompressed data is because the size of the compressed data exceeds that in the backup disk device (36) when said semiconductor memory modules (33 a-33 n) full during writing of the compressed data; and
then writing the recompressed data from the backup disk device ( 36 ) into the semiconductor memory module ( 33 ).