DE50112519D1 - Testbarer festwertspeicher für datenspeicher-redundanzlogik - Google Patents

Testbarer festwertspeicher für datenspeicher-redundanzlogik

Info

Publication number
DE50112519D1
DE50112519D1 DE50112519T DE50112519T DE50112519D1 DE 50112519 D1 DE50112519 D1 DE 50112519D1 DE 50112519 T DE50112519 T DE 50112519T DE 50112519 T DE50112519 T DE 50112519T DE 50112519 D1 DE50112519 D1 DE 50112519D1
Authority
DE
Germany
Prior art keywords
testable
storage
read
memory
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE50112519T
Other languages
English (en)
Inventor
Rod Fleck
Paolo Ienne
Klaus Oberlaender
Sabeen Randhawa
Laurent Gaziello
Yannick Martelloni
Steffen Paul
Volker Schoeber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Application granted granted Critical
Publication of DE50112519D1 publication Critical patent/DE50112519D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/24—Accessing extra cells, e.g. dummy cells or redundant cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
DE50112519T 2000-02-08 2001-02-05 Testbarer festwertspeicher für datenspeicher-redundanzlogik Expired - Lifetime DE50112519D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/500,414 US6536003B1 (en) 2000-02-08 2000-02-08 Testable read-only memory for data memory redundant logic
PCT/EP2001/001211 WO2001059790A1 (de) 2000-02-08 2001-02-05 Testbarer festwertspeicher für datenspeicher-redundanzlogik

Publications (1)

Publication Number Publication Date
DE50112519D1 true DE50112519D1 (de) 2007-07-05

Family

ID=23989312

Family Applications (1)

Application Number Title Priority Date Filing Date
DE50112519T Expired - Lifetime DE50112519D1 (de) 2000-02-08 2001-02-05 Testbarer festwertspeicher für datenspeicher-redundanzlogik

Country Status (6)

Country Link
US (1) US6536003B1 (de)
EP (1) EP1254461B1 (de)
JP (1) JP3801506B2 (de)
KR (1) KR20020074511A (de)
DE (1) DE50112519D1 (de)
WO (1) WO2001059790A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10122619C1 (de) * 2001-05-10 2003-02-13 Infineon Technologies Ag Testschaltung zum Testen einer synchronen Schaltung
JP2003281899A (ja) * 2002-03-22 2003-10-03 Sony Corp 半導体記憶装置とその試験方法
EP1369878A1 (de) 2002-06-04 2003-12-10 Infineon Technologies AG Vorrichtung zum Testen einer Gruppe funktionell unabhängiger Speicher und zum Ersetzen defekter Speicherworte
JP2004303287A (ja) * 2003-03-28 2004-10-28 Hitachi Ltd 半導体集積回路装置
US7627029B2 (en) 2003-05-20 2009-12-01 Rambus Inc. Margin test methods and circuits
DE102005061719B3 (de) * 2005-12-22 2007-05-16 Infineon Technologies Ag Speichervorrichtung mit Fuse-Speicherelementen
US7958432B2 (en) 2007-04-11 2011-06-07 International Business Machines Corporation Verification of non volatile storage storing preserved unneeded data
US9286933B2 (en) * 2012-11-27 2016-03-15 Avago Technologies General Ip (Singapore) Pte. Ltd. Systems and methods for controlled data processor operational marginalization
CN106575525B (zh) * 2014-08-28 2020-09-25 东芝存储器株式会社 半导体存储装置

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105159B2 (ja) 1989-11-16 1995-11-13 株式会社東芝 半導体記憶装置の冗長回路
US5153880A (en) * 1990-03-12 1992-10-06 Xicor, Inc. Field-programmable redundancy apparatus for memory arrays
KR920005798A (ko) * 1990-04-18 1992-04-03 미타 가쓰시게 반도체 집적회로
US5708601A (en) 1993-12-09 1998-01-13 Sgs-Thomson Microelectronics S.R.L. Integrated circuitry for checking the utilization rate of redundancy memory elements in a semiconductor memory device
FR2716566B1 (fr) * 1994-02-23 1996-04-19 Sgs Thomson Microelectronics Circuit de sélection d'éléments de mémoire redondants et mémoire "Flash Eeprom" comportant ledit circuit.
GB9417269D0 (en) 1994-08-26 1994-10-19 Inmos Ltd Memory and test method therefor
US5523975A (en) * 1995-02-08 1996-06-04 Alliance Semiconductor Corporation Redundancy scheme for monolithic memories
US5636161A (en) 1995-10-30 1997-06-03 Cypress Semiconductor Corporation Eprom bit-line interface for implementing programming, verification and testing
US5841709A (en) * 1995-12-29 1998-11-24 Stmicroelectronics, Inc. Memory having and method for testing redundant memory cells
US6175936B1 (en) * 1998-07-17 2001-01-16 Lucent Technologies Inc. Apparatus for detecting faults in multiple computer memories
US6208570B1 (en) * 1998-08-13 2001-03-27 Texas Instruments Incorporated Redundancy test method for a semiconductor memory
US6181614B1 (en) * 1999-11-12 2001-01-30 International Business Machines Corporation Dynamic repair of redundant memory array

Also Published As

Publication number Publication date
JP3801506B2 (ja) 2006-07-26
KR20020074511A (ko) 2002-09-30
EP1254461B1 (de) 2007-05-23
JP2003523042A (ja) 2003-07-29
US6536003B1 (en) 2003-03-18
EP1254461A1 (de) 2002-11-06
WO2001059790A1 (de) 2001-08-16

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