DE50308653D1 - Verfahren zur herstellung einer nrom-speicherzellenanordnung - Google Patents
Verfahren zur herstellung einer nrom-speicherzellenanordnungInfo
- Publication number
- DE50308653D1 DE50308653D1 DE50308653T DE50308653T DE50308653D1 DE 50308653 D1 DE50308653 D1 DE 50308653D1 DE 50308653 T DE50308653 T DE 50308653T DE 50308653 T DE50308653 T DE 50308653T DE 50308653 D1 DE50308653 D1 DE 50308653D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- memory cell
- cell arrangement
- nrom memory
- nrom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE10226964A DE10226964A1 (de) | 2002-06-17 | 2002-06-17 | Verfahren zur Herstellung einer NROM-Speicherzellenanordnung |
PCT/DE2003/002025 WO2003107416A1 (de) | 2002-06-17 | 2003-06-17 | Verfahren zur herstellung einer nrom-speicherzellenanordnung |
Publications (1)
Publication Number | Publication Date |
---|---|
DE50308653D1 true DE50308653D1 (de) | 2008-01-03 |
Family
ID=29719164
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10226964A Ceased DE10226964A1 (de) | 2002-06-17 | 2002-06-17 | Verfahren zur Herstellung einer NROM-Speicherzellenanordnung |
DE50308653T Expired - Lifetime DE50308653D1 (de) | 2002-06-17 | 2003-06-17 | Verfahren zur herstellung einer nrom-speicherzellenanordnung |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE10226964A Ceased DE10226964A1 (de) | 2002-06-17 | 2002-06-17 | Verfahren zur Herstellung einer NROM-Speicherzellenanordnung |
Country Status (7)
Country | Link |
---|---|
US (1) | US7323383B2 (de) |
EP (1) | EP1514304B1 (de) |
JP (1) | JP2005534167A (de) |
CN (1) | CN1312761C (de) |
DE (2) | DE10226964A1 (de) |
TW (1) | TWI264088B (de) |
WO (1) | WO2003107416A1 (de) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10226964A1 (de) * | 2002-06-17 | 2004-01-08 | Infineon Technologies Ag | Verfahren zur Herstellung einer NROM-Speicherzellenanordnung |
JP2005277183A (ja) | 2004-03-25 | 2005-10-06 | Sharp Corp | 不揮発性半導体記憶装置及びその製造方法 |
KR100955720B1 (ko) * | 2004-12-28 | 2010-05-03 | 스펜션 엘엘씨 | 반도체 장치 |
TWI262595B (en) * | 2005-08-08 | 2006-09-21 | Powerchip Semiconductor Corp | Non-volatile memory and fabricating method thereof |
US7642158B2 (en) * | 2005-09-30 | 2010-01-05 | Infineon Technologies Ag | Semiconductor memory device and method of production |
JP5252169B2 (ja) * | 2007-03-22 | 2013-07-31 | 日本電気株式会社 | 半導体装置 |
US20100151677A1 (en) * | 2007-04-12 | 2010-06-17 | Freescale Semiconductor, Inc. | Etch method in the manufacture of a semiconductor device |
US20080315326A1 (en) * | 2007-06-21 | 2008-12-25 | Werner Graf | Method for forming an integrated circuit having an active semiconductor device and integrated circuit |
JP2009277782A (ja) * | 2008-05-13 | 2009-11-26 | Oki Semiconductor Co Ltd | 半導体記憶装置および半導体記憶装置の製造方法 |
US20100234125A1 (en) * | 2009-03-16 | 2010-09-16 | Steven Aoyama | High launch and low spin golf ball and golf club combination |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5071782A (en) * | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
US5278438A (en) * | 1991-12-19 | 1994-01-11 | North American Philips Corporation | Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure |
JP3381863B2 (ja) | 1993-06-04 | 2003-03-04 | ソニー株式会社 | Nor型フラッシュメモリ |
US5387534A (en) * | 1994-05-05 | 1995-02-07 | Micron Semiconductor, Inc. | Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells |
JPH08186183A (ja) | 1994-12-28 | 1996-07-16 | Sony Corp | 不揮発性半導体メモリ装置およびその製造方法 |
US5768192A (en) | 1996-07-23 | 1998-06-16 | Saifun Semiconductors, Ltd. | Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping |
DE19639026C1 (de) | 1996-09-23 | 1998-04-09 | Siemens Ag | Selbstjustierte nichtflüchtige Speicherzelle |
US6025626A (en) | 1996-09-23 | 2000-02-15 | Siemens, Aktiengesellschaft | Nonvolatile memory cell |
US6768165B1 (en) | 1997-08-01 | 2004-07-27 | Saifun Semiconductors Ltd. | Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping |
US6215148B1 (en) | 1998-05-20 | 2001-04-10 | Saifun Semiconductors Ltd. | NROM cell with improved programming, erasing and cycling |
US6136716A (en) * | 1998-11-09 | 2000-10-24 | Worldwide Semiconductor Manufacturing Corporation | Method for manufacturing a self-aligned stacked storage node DRAM cell |
DE10039441A1 (de) * | 2000-08-11 | 2002-02-28 | Infineon Technologies Ag | Speicherzelle, Speicherzellenanordnung und Herstellungsverfahren |
EP1307920A2 (de) | 2000-08-11 | 2003-05-07 | Infineon Technologies AG | Speicherzelle, speicherzellenanordnung und herstellungsverfahren |
US6580124B1 (en) * | 2000-08-14 | 2003-06-17 | Matrix Semiconductor Inc. | Multigate semiconductor device with vertical channel current and method of fabrication |
DE10129958B4 (de) | 2001-06-21 | 2006-07-13 | Infineon Technologies Ag | Speicherzellenanordnung und Herstellungsverfahren |
KR100487523B1 (ko) * | 2002-04-15 | 2005-05-03 | 삼성전자주식회사 | 부유트랩형 비휘발성 메모리 소자 및 그 제조방법 |
JP2003309192A (ja) | 2002-04-17 | 2003-10-31 | Fujitsu Ltd | 不揮発性半導体メモリおよびその製造方法 |
DE10225410A1 (de) * | 2002-06-07 | 2004-01-08 | Infineon Technologies Ag | Verfahren zur Herstellung von NROM-Speicherzellen mit Grabentransistoren |
US6777725B2 (en) * | 2002-06-14 | 2004-08-17 | Ingentix Gmbh & Co. Kg | NROM memory circuit with recessed bitline |
DE10226964A1 (de) * | 2002-06-17 | 2004-01-08 | Infineon Technologies Ag | Verfahren zur Herstellung einer NROM-Speicherzellenanordnung |
DE10240893A1 (de) * | 2002-09-04 | 2004-03-18 | Infineon Technologies Ag | Verfahren zur Herstellung von SONOS-Speicherzellen, SONOS-Speicherzelle und Speicherzellenfeld |
DE10324550B4 (de) * | 2003-05-30 | 2006-10-19 | Infineon Technologies Ag | Herstellungsverfahren für eine NROM-Halbleiterspeichervorrichtung |
-
2002
- 2002-06-17 DE DE10226964A patent/DE10226964A1/de not_active Ceased
-
2003
- 2003-04-29 TW TW092110069A patent/TWI264088B/zh active
- 2003-06-17 DE DE50308653T patent/DE50308653D1/de not_active Expired - Lifetime
- 2003-06-17 WO PCT/DE2003/002025 patent/WO2003107416A1/de active IP Right Grant
- 2003-06-17 JP JP2004514130A patent/JP2005534167A/ja active Pending
- 2003-06-17 CN CNB038140144A patent/CN1312761C/zh not_active Expired - Fee Related
- 2003-06-17 EP EP03740097A patent/EP1514304B1/de not_active Expired - Fee Related
-
2004
- 2004-12-17 US US11/015,747 patent/US7323383B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US7323383B2 (en) | 2008-01-29 |
DE10226964A1 (de) | 2004-01-08 |
US20050158953A1 (en) | 2005-07-21 |
JP2005534167A (ja) | 2005-11-10 |
CN1663041A (zh) | 2005-08-31 |
WO2003107416A1 (de) | 2003-12-24 |
EP1514304A1 (de) | 2005-03-16 |
EP1514304B1 (de) | 2007-11-21 |
CN1312761C (zh) | 2007-04-25 |
TWI264088B (en) | 2006-10-11 |
TW200403816A (en) | 2004-03-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition |