DE512463T1 - Verfahren zur Herstellung von dynamischer Speichern mit wahlfreiem Zugriff. - Google Patents

Verfahren zur Herstellung von dynamischer Speichern mit wahlfreiem Zugriff.

Info

Publication number
DE512463T1
DE512463T1 DE92107517T DE92107517T DE512463T1 DE 512463 T1 DE512463 T1 DE 512463T1 DE 92107517 T DE92107517 T DE 92107517T DE 92107517 T DE92107517 T DE 92107517T DE 512463 T1 DE512463 T1 DE 512463T1
Authority
DE
Germany
Prior art keywords
random access
dynamic random
access memories
making dynamic
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE92107517T
Other languages
English (en)
Inventor
Charles H Dennison
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of DE512463T1 publication Critical patent/DE512463T1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE92107517T 1991-05-03 1992-05-04 Verfahren zur Herstellung von dynamischer Speichern mit wahlfreiem Zugriff. Pending DE512463T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/695,182 US5100826A (en) 1991-05-03 1991-05-03 Process for manufacturing ultra-dense dynamic random access memories using partially-disposable dielectric filler strips between wordlines

Publications (1)

Publication Number Publication Date
DE512463T1 true DE512463T1 (de) 1993-10-14

Family

ID=24791969

Family Applications (1)

Application Number Title Priority Date Filing Date
DE92107517T Pending DE512463T1 (de) 1991-05-03 1992-05-04 Verfahren zur Herstellung von dynamischer Speichern mit wahlfreiem Zugriff.

Country Status (4)

Country Link
US (1) US5100826A (de)
EP (1) EP0512463A1 (de)
JP (1) JP3219850B2 (de)
DE (1) DE512463T1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5126290A (en) * 1991-09-11 1992-06-30 Micron Technology, Inc. Method of making memory devices utilizing one-sided ozone teos spacers
KR950011643B1 (ko) * 1992-04-17 1995-10-07 현대전자산업주식회사 반도체장치 및 그 제조방법
US5480837A (en) * 1994-06-27 1996-01-02 Industrial Technology Research Institute Process of making an integrated circuit having a planar conductive layer
EP0791583B1 (de) * 1995-09-08 2001-04-18 Nippon Soda Co., Ltd. Verfahren zur herstellung von 3-(aminomethyl)-6-chlorpyridinen
JP3703885B2 (ja) * 1995-09-29 2005-10-05 株式会社東芝 半導体記憶装置とその製造方法
KR0161474B1 (ko) * 1995-12-15 1999-02-01 김광호 셀 플러그 이온주입을 이용한 반도체 메모리장치의 제조방법
JPH10308498A (ja) * 1997-05-08 1998-11-17 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JP3028080B2 (ja) * 1997-06-18 2000-04-04 日本電気株式会社 半導体装置の構造およびその製造方法
US5917213A (en) 1997-08-21 1999-06-29 Micron Technology, Inc. Depletion compensated polysilicon electrodes
US6010935A (en) * 1997-08-21 2000-01-04 Micron Technology, Inc. Self aligned contacts
US6185473B1 (en) 1998-01-08 2001-02-06 Micron Technology, Inc. Optical pattern transfer tool
US6373114B1 (en) * 1998-10-23 2002-04-16 Micron Technology, Inc. Barrier in gate stack for improved gate dielectric integrity
US6358788B1 (en) 1999-08-30 2002-03-19 Micron Technology, Inc. Method of fabricating a wordline in a memory array of a semiconductor device
US6265297B1 (en) 1999-09-01 2001-07-24 Micron Technology, Inc. Ammonia passivation of metal gate electrodes to inhibit oxidation of metal
US6171948B1 (en) 1999-11-02 2001-01-09 Micron Technology, Inc. Method for filling structural gaps and intergrated circuitry
US6306767B1 (en) * 2000-05-31 2001-10-23 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned etching method for forming high areal density patterned microelectronic structures
US6458714B1 (en) 2000-11-22 2002-10-01 Micron Technology, Inc. Method of selective oxidation in semiconductor manufacture
US6548347B2 (en) * 2001-04-12 2003-04-15 Micron Technology, Inc. Method of forming minimally spaced word lines
US10700072B2 (en) 2018-10-18 2020-06-30 Applied Materials, Inc. Cap layer for bit line resistance reduction
US11631680B2 (en) 2018-10-18 2023-04-18 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal
US10903112B2 (en) 2018-10-18 2021-01-26 Applied Materials, Inc. Methods and apparatus for smoothing dynamic random access memory bit line metal

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60217644A (ja) * 1984-04-12 1985-10-31 Matsushita Electronics Corp 半導体装置の製造方法
JPS62210646A (ja) * 1986-03-11 1987-09-16 Mitsubishi Electric Corp 半導体装置の製造方法
US4775550A (en) * 1986-06-03 1988-10-04 Intel Corporation Surface planarization method for VLSI technology
JPS63142A (ja) * 1986-06-19 1988-01-05 Toshiba Corp 半導体装置の製造方法
US4855801A (en) * 1986-08-22 1989-08-08 Siemens Aktiengesellschaft Transistor varactor for dynamics semiconductor storage means
JPS63302537A (ja) * 1987-06-02 1988-12-09 Rohm Co Ltd 集積回路の製造方法
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
KR910009805B1 (ko) * 1987-11-25 1991-11-30 후지쓰 가부시끼가이샤 다이나믹 랜덤 액세스 메모리 장치와 그의 제조방법
US4894351A (en) * 1988-02-16 1990-01-16 Sprague Electric Company Method for making a silicon IC with planar double layer metal conductors system
JP2755591B2 (ja) * 1988-03-25 1998-05-20 株式会社東芝 半導体記憶装置
JP2904533B2 (ja) * 1989-03-09 1999-06-14 株式会社東芝 半導体装置の製造方法
JP2586182B2 (ja) * 1989-05-31 1997-02-26 日本電気株式会社 半導体メモリセルおよびその製造方法

Also Published As

Publication number Publication date
JPH077083A (ja) 1995-01-10
EP0512463A1 (de) 1992-11-11
JP3219850B2 (ja) 2001-10-15
US5100826A (en) 1992-03-31

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