DE58907307D1 - Verfahren zur plazierung von modulen auf einem träger. - Google Patents

Verfahren zur plazierung von modulen auf einem träger.

Info

Publication number
DE58907307D1
DE58907307D1 DE89911775T DE58907307T DE58907307D1 DE 58907307 D1 DE58907307 D1 DE 58907307D1 DE 89911775 T DE89911775 T DE 89911775T DE 58907307 T DE58907307 T DE 58907307T DE 58907307 D1 DE58907307 D1 DE 58907307D1
Authority
DE
Germany
Prior art keywords
carrier
placing modules
modules
placing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE89911775T
Other languages
English (en)
Inventor
Kurt Antreich
Frank Johannes
Juergen Kleinhans
Georg Sigl
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Application granted granted Critical
Publication of DE58907307D1 publication Critical patent/DE58907307D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
DE89911775T 1988-11-02 1989-10-26 Verfahren zur plazierung von modulen auf einem träger. Expired - Fee Related DE58907307D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP88118251 1988-11-02
PCT/DE1989/000688 WO1990005344A1 (de) 1988-11-02 1989-10-26 Verfahren zur plazierung von modulen auf einem träger

Publications (1)

Publication Number Publication Date
DE58907307D1 true DE58907307D1 (de) 1994-04-28

Family

ID=8199514

Family Applications (1)

Application Number Title Priority Date Filing Date
DE89911775T Expired - Fee Related DE58907307D1 (de) 1988-11-02 1989-10-26 Verfahren zur plazierung von modulen auf einem träger.

Country Status (5)

Country Link
US (1) US5267176A (de)
EP (1) EP0441810B1 (de)
JP (1) JPH04501475A (de)
DE (1) DE58907307D1 (de)
WO (1) WO1990005344A1 (de)

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US5566078A (en) * 1993-05-26 1996-10-15 Lsi Logic Corporation Integrated circuit cell placement using optimization-driven clustering
US5598343A (en) * 1993-10-01 1997-01-28 Texas Instruments Incorporated Method of segmenting an FPGA channel architecture for maximum routability and performance
JP2922404B2 (ja) * 1993-11-15 1999-07-26 富士通株式会社 集積回路の配置決定方法
US5818726A (en) * 1994-04-18 1998-10-06 Cadence Design Systems, Inc. System and method for determining acceptable logic cell locations and generating a legal location structure
US6155725A (en) * 1994-04-19 2000-12-05 Lsi Logic Corporation Cell placement representation and transposition for integrated circuit physical design automation system
US5875117A (en) * 1994-04-19 1999-02-23 Lsi Logic Corporation Simultaneous placement and routing (SPAR) method for integrated circuit physical design automation system
US6493658B1 (en) 1994-04-19 2002-12-10 Lsi Logic Corporation Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithms
US5963975A (en) * 1994-04-19 1999-10-05 Lsi Logic Corporation Single chip integrated circuit distributed shared memory (DSM) and communications nodes
US5914887A (en) * 1994-04-19 1999-06-22 Lsi Logic Corporation Congestion based cost factor computing apparatus for integrated circuit physical design automation system
US5557533A (en) * 1994-04-19 1996-09-17 Lsi Logic Corporation Cell placement alteration apparatus for integrated circuit chip physical design automation system
US5815403A (en) * 1994-04-19 1998-09-29 Lsi Logic Corporation Fail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chip
US5495419A (en) * 1994-04-19 1996-02-27 Lsi Logic Corporation Integrated circuit physical design automation system utilizing optimization process decomposition and parallel processing
US5535134A (en) * 1994-06-03 1996-07-09 International Business Machines Corporation Object placement aid
US5638293A (en) * 1994-09-13 1997-06-10 Lsi Logic Corporation Optimal pad location method for microelectronic circuit cell placement
US5696693A (en) * 1995-03-31 1997-12-09 Unisys Corporation Method for placing logic functions and cells in a logic design using floor planning by analogy
JP3504394B2 (ja) * 1995-09-08 2004-03-08 松下電器産業株式会社 部品配列のデータ作成方法
US5818722A (en) * 1995-11-03 1998-10-06 Yoji Kajitani Method of placing and extracting modules
EP0791887B1 (de) * 1996-02-21 2001-05-23 Matsushita Electric Industrial Co., Ltd. Verfahren un Vorrichtung zur Eingabe eines Flipchip-Layouts
US5818729A (en) * 1996-05-23 1998-10-06 Synopsys, Inc. Method and system for placing cells using quadratic placement and a spanning tree model
US5798936A (en) * 1996-06-21 1998-08-25 Avant| Corporation Congestion-driven placement method and computer-implemented integrated-circuit design tool
US5872718A (en) * 1996-06-28 1999-02-16 Lsi Logic Corporation Advanced modular cell placement system
US6085032A (en) * 1996-06-28 2000-07-04 Lsi Logic Corporation Advanced modular cell placement system with sinusoidal optimization
US5963455A (en) * 1996-06-28 1999-10-05 Lsi Logic Corporation Advanced modular cell placement system with functional sieve optimization technique
US5870312A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with dispersion-driven levelizing system
US5831863A (en) * 1996-06-28 1998-11-03 Lsi Logic Corporation Advanced modular cell placement system with wire length driven affinity system
US5867398A (en) * 1996-06-28 1999-02-02 Lsi Logic Corporation Advanced modular cell placement system with density driven capacity penalty system
US5892688A (en) * 1996-06-28 1999-04-06 Lsi Logic Corporation Advanced modular cell placement system with iterative one dimensional preplacement optimization
US6067409A (en) * 1996-06-28 2000-05-23 Lsi Logic Corporation Advanced modular cell placement system
US5870311A (en) * 1996-06-28 1999-02-09 Lsi Logic Corporation Advanced modular cell placement system with fast procedure for finding a levelizing cut point
US5914888A (en) * 1996-06-28 1999-06-22 Lsi Logic Corporation Advanced modular cell placement system with coarse overflow remover
US6030110A (en) * 1996-06-28 2000-02-29 Lsi Logic Corporation Advanced modular cell placement system with median control and increase in resolution
US5844811A (en) * 1996-06-28 1998-12-01 Lsi Logic Corporation Advanced modular cell placement system with universal affinity driven discrete placement optimization
US5835381A (en) * 1996-06-28 1998-11-10 Lsi Logic Corporation Advanced modular cell placement system with minimizing maximal cut driven affinity system
US6026223A (en) * 1996-06-28 2000-02-15 Scepanovic; Ranko Advanced modular cell placement system with overlap remover with minimal noise
US5812740A (en) * 1996-06-28 1998-09-22 Lsi Logic Corporation Advanced modular cell placement system with neighborhood system driven optimization
US5808899A (en) * 1996-06-28 1998-09-15 Lsi Logic Corporation Advanced modular cell placement system with cell placement crystallization
US5980093A (en) * 1996-12-04 1999-11-09 Lsi Logic Corporation Integrated circuit layout routing using multiprocessing
US6754879B1 (en) 1997-01-27 2004-06-22 Unisys Corporation Method and apparatus for providing modularity to a behavioral description of a circuit design
US6718520B1 (en) 1997-01-27 2004-04-06 Unisys Corporation Method and apparatus for selectively providing hierarchy to a circuit design
US6378114B1 (en) * 1997-07-01 2002-04-23 Synopsys, Inc. Method for the physical placement of an integrated circuit adaptive to netlist changes
US6385760B2 (en) * 1998-06-12 2002-05-07 Monterey Design Systems, Inc. System and method for concurrent placement of gates and associated wiring
US6378119B1 (en) * 1999-05-24 2002-04-23 Dell Usa, L.P. Method and system for adaptive component placement
US6415426B1 (en) 2000-06-02 2002-07-02 Incentia Design Systems, Inc. Dynamic weighting and/or target zone analysis in timing driven placement of cells of an integrated circuit design
US7080336B2 (en) 2000-12-06 2006-07-18 Cadence Design Systems, Inc. Method and apparatus for computing placement costs
US7003754B2 (en) * 2000-12-07 2006-02-21 Cadence Design Systems, Inc. Routing method and apparatus that use of diagonal routes
US6957410B2 (en) 2000-12-07 2005-10-18 Cadence Design Systems, Inc. Method and apparatus for adaptively selecting the wiring model for a design region
US6516455B1 (en) * 2000-12-06 2003-02-04 Cadence Design Systems, Inc. Partitioning placement method using diagonal cutlines
US6826737B2 (en) * 2000-12-06 2004-11-30 Cadence Design Systems, Inc. Recursive partitioning placement method and apparatus
WO2002047165A2 (en) * 2000-12-06 2002-06-13 Simplex Solutions, Inc. Method and apparatus for considering diagonal wiring in placement
US7024650B2 (en) * 2000-12-06 2006-04-04 Cadence Design Systems, Inc. Method and apparatus for considering diagonal wiring in placement
US7055120B2 (en) 2000-12-06 2006-05-30 Cadence Design Systems, Inc. Method and apparatus for placing circuit modules
US7073150B2 (en) 2000-12-07 2006-07-04 Cadence Design Systems, Inc. Hierarchical routing method and apparatus that use diagonal routes
US6915501B2 (en) 2001-01-19 2005-07-05 Cadence Design Systems, Inc. LP method and apparatus for identifying routes
US6738960B2 (en) * 2001-01-19 2004-05-18 Cadence Design Systems, Inc. Method and apparatus for producing sub-optimal routes for a net by generating fake configurations
US6507937B1 (en) * 2001-06-19 2003-01-14 Lsi Logic Corporation Method of global placement of control cells and hardmac pins in a datapath macro for an integrated circuit design
US6795958B2 (en) 2001-08-23 2004-09-21 Cadence Design Systems, Inc. Method and apparatus for generating routes for groups of related node configurations
US6931616B2 (en) * 2001-08-23 2005-08-16 Cadence Design Systems, Inc. Routing method and apparatus
US7143382B2 (en) 2001-08-23 2006-11-28 Cadence Design Systems, Inc. Method and apparatus for storing routes
US6877149B2 (en) 2001-08-23 2005-04-05 Cadence Design Systems, Inc. Method and apparatus for pre-computing routes
US7058913B1 (en) 2001-09-06 2006-06-06 Cadence Design Systems, Inc. Analytical placement method and apparatus
US7225116B2 (en) * 2002-08-20 2007-05-29 Cadence Design Systems, Inc. Method for eliminating routing congestion in an IC layout
US7080342B2 (en) * 2002-11-18 2006-07-18 Cadence Design Systems, Inc Method and apparatus for computing capacity of a region for non-Manhattan routing
US7480885B2 (en) 2002-11-18 2009-01-20 Cadence Design Systems, Inc. Method and apparatus for routing with independent goals on different layers
US7010771B2 (en) * 2002-11-18 2006-03-07 Cadence Design Systems, Inc. Method and apparatus for searching for a global path
US6988257B2 (en) * 2002-11-18 2006-01-17 Cadence Design Systems, Inc. Method and apparatus for routing
US7003752B2 (en) * 2002-11-18 2006-02-21 Cadence Design Systems, Inc. Method and apparatus for routing
US6996789B2 (en) * 2002-11-18 2006-02-07 Cadence Design Systems, Inc. Method and apparatus for performing an exponential path search
US7171635B2 (en) * 2002-11-18 2007-01-30 Cadence Design Systems, Inc. Method and apparatus for routing
US7624367B2 (en) 2002-11-18 2009-11-24 Cadence Design Systems, Inc. Method and system for routing
US7047513B2 (en) * 2002-11-18 2006-05-16 Cadence Design Systems, Inc. Method and apparatus for searching for a three-dimensional global path
US7506295B1 (en) 2002-12-31 2009-03-17 Cadence Design Systems, Inc. Non manhattan floor plan architecture for integrated circuits
US7013445B1 (en) 2002-12-31 2006-03-14 Cadence Design Systems, Inc. Post processor for optimizing manhattan integrated circuits placements into non manhattan placements
US7089519B1 (en) 2002-12-31 2006-08-08 Cadence Design System, Inc. Method and system for performing placement on non Manhattan semiconductor integrated circuits
US8032855B1 (en) * 2005-12-06 2011-10-04 Altera Corporation Method and apparatus for performing incremental placement on a structured application specific integrated circuit

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US3629843A (en) * 1970-05-11 1971-12-21 Bell Telephone Labor Inc Machine process for assigning interconnected components to locations in a planar matrix
US4342090A (en) * 1980-06-27 1982-07-27 International Business Machines Corp. Batch chip placement system
US4593363A (en) * 1983-08-12 1986-06-03 International Business Machines Corporation Simultaneous placement and wiring for VLSI chips
US4577276A (en) * 1983-09-12 1986-03-18 At&T Bell Laboratories Placement of components on circuit substrates
US4630219A (en) * 1983-11-23 1986-12-16 International Business Machines Corporation Element placement method
US4908772A (en) * 1987-03-30 1990-03-13 Bell Telephone Laboratories Integrated circuits with component placement by rectilinear partitioning
US4852015A (en) * 1987-06-24 1989-07-25 Eta Systems, Inc. Automatic circuit layout router

Also Published As

Publication number Publication date
JPH04501475A (ja) 1992-03-12
EP0441810B1 (de) 1994-03-23
EP0441810A1 (de) 1991-08-21
WO1990005344A1 (de) 1990-05-17
US5267176A (en) 1993-11-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee