DE60044639D1 - Verfahren zur herstellung einer halbleitervorrichtung - Google Patents

Verfahren zur herstellung einer halbleitervorrichtung

Info

Publication number
DE60044639D1
DE60044639D1 DE60044639T DE60044639T DE60044639D1 DE 60044639 D1 DE60044639 D1 DE 60044639D1 DE 60044639 T DE60044639 T DE 60044639T DE 60044639 T DE60044639 T DE 60044639T DE 60044639 D1 DE60044639 D1 DE 60044639D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor device
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60044639T
Other languages
English (en)
Inventor
Pierre H Woerlee
Jurriaan Schmitz
Andreas H Montree
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP BV
Original Assignee
NXP BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP BV filed Critical NXP BV
Application granted granted Critical
Publication of DE60044639D1 publication Critical patent/DE60044639D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
DE60044639T 1999-12-17 2000-12-01 Verfahren zur herstellung einer halbleitervorrichtung Expired - Lifetime DE60044639D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP99204374 1999-12-17
PCT/EP2000/012136 WO2001045156A1 (en) 1999-12-17 2000-12-01 A method of manufacturing a semiconductor device

Publications (1)

Publication Number Publication Date
DE60044639D1 true DE60044639D1 (de) 2010-08-19

Family

ID=8241019

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60044639T Expired - Lifetime DE60044639D1 (de) 1999-12-17 2000-12-01 Verfahren zur herstellung einer halbleitervorrichtung

Country Status (7)

Country Link
US (2) US6406963B2 (de)
EP (1) EP1157417B1 (de)
JP (1) JP2003517209A (de)
KR (1) KR100702282B1 (de)
DE (1) DE60044639D1 (de)
TW (1) TW514992B (de)
WO (1) WO2001045156A1 (de)

Families Citing this family (42)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100352909B1 (ko) 2000-03-17 2002-09-16 삼성전자 주식회사 반도체소자의 자기정렬 콘택 구조체 형성방법 및 그에의해 형성된 자기정렬 콘택 구조체
KR100372643B1 (ko) * 2000-06-30 2003-02-17 주식회사 하이닉스반도체 다마신 공정을 이용한 반도체 소자의 제조방법
US6969539B2 (en) 2000-09-28 2005-11-29 President And Fellows Of Harvard College Vapor deposition of metal oxides, silicates and phosphates, and silicon dioxide
JP3669919B2 (ja) * 2000-12-04 2005-07-13 シャープ株式会社 半導体装置の製造方法
US6787424B1 (en) * 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
US6583060B2 (en) * 2001-07-13 2003-06-24 Micron Technology, Inc. Dual depth trench isolation
KR100442780B1 (ko) * 2001-12-24 2004-08-04 동부전자 주식회사 반도체 소자의 트랜지스터 제조 방법
KR100477543B1 (ko) * 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
JP3865233B2 (ja) * 2002-08-19 2007-01-10 富士通株式会社 Ｃｍｏｓ集積回路装置
US7033894B1 (en) * 2003-08-05 2006-04-25 Advanced Micro Devices, Inc. Method for modulating flatband voltage of devices having high-k gate dielectrics by post-deposition annealing
US7078282B2 (en) * 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US6887785B1 (en) 2004-05-13 2005-05-03 International Business Machines Corporation Etching openings of different depths using a single mask layer method and structure
KR100606933B1 (ko) * 2004-06-30 2006-08-01 동부일렉트로닉스 주식회사 반도체 소자의 제조방법
US7166506B2 (en) * 2004-12-17 2007-01-23 Intel Corporation Poly open polish process
JP2007005489A (ja) * 2005-06-22 2007-01-11 Seiko Instruments Inc 半導体装置の製造方法
US7964921B2 (en) * 2005-08-22 2011-06-21 Renesas Electronics Corporation MOSFET and production method of semiconductor device
US20070105295A1 (en) * 2005-11-08 2007-05-10 Dongbuanam Semiconductor Inc. Method for forming lightly-doped-drain metal-oxide-semiconductor (LDD MOS) device
KR100732767B1 (ko) * 2005-12-29 2007-06-27 주식회사 하이닉스반도체 반도체 소자의 리세스 채널용 트렌치 형성방법
JP5380827B2 (ja) * 2006-12-11 2014-01-08 ソニー株式会社 半導体装置の製造方法
US7871915B2 (en) * 2008-09-26 2011-01-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming metal gates in a gate last process
CN102087980A (zh) * 2009-12-04 2011-06-08 中国科学院微电子研究所 高性能半导体器件及其形成方法
US8664070B2 (en) * 2009-12-21 2014-03-04 Taiwan Semiconductor Manufacturing Company, Ltd. High temperature gate replacement process
DE102010002411B4 (de) * 2010-02-26 2012-10-31 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Kontaktbalken mit reduzierter Randzonenkapazität in einem Halbleiterbauelement
CN102214576A (zh) * 2010-04-09 2011-10-12 中国科学院微电子研究所 半导体器件及其制作方法
KR20110120695A (ko) * 2010-04-29 2011-11-04 삼성전자주식회사 반도체 소자
US20120098043A1 (en) * 2010-10-25 2012-04-26 Ya-Hsueh Hsieh Semiconductor device having metal gate and manufacturing method thereof
US8084311B1 (en) * 2010-11-17 2011-12-27 International Business Machines Corporation Method of forming replacement metal gate with borderless contact and structure thereof
US20120289015A1 (en) * 2011-05-13 2012-11-15 United Microelectronics Corp. Method for fabricating semiconductor device with enhanced channel stress
US8946031B2 (en) * 2012-01-18 2015-02-03 United Microelectronics Corp. Method for fabricating MOS device
CN105810729B (zh) * 2014-12-29 2018-09-11 中国科学院微电子研究所 鳍式场效应晶体管及其制造方法
US10714621B2 (en) * 2016-12-14 2020-07-14 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming doped channel thereof
US20190013387A1 (en) 2017-07-05 2019-01-10 Micron Technology, Inc. Memory cell structures
US10153039B1 (en) 2017-07-05 2018-12-11 Micron Technology, Inc. Memory cells programmed via multi-mechanism charge transports
US10374101B2 (en) 2017-07-05 2019-08-06 Micron Technology, Inc. Memory arrays
US10297493B2 (en) 2017-07-05 2019-05-21 Micron Technology, Inc. Trench isolation interfaces
US10153348B1 (en) 2017-07-05 2018-12-11 Micron Technology, Inc. Memory configurations
US10411026B2 (en) 2017-07-05 2019-09-10 Micron Technology, Inc. Integrated computing structures formed on silicon
US10262736B2 (en) 2017-07-05 2019-04-16 Micron Technology, Inc. Multifunctional memory cells
US10153381B1 (en) 2017-07-05 2018-12-11 Micron Technology, Inc. Memory cells having an access gate and a control gate and dielectric stacks above and below the access gate
US10176870B1 (en) 2017-07-05 2019-01-08 Micron Technology, Inc. Multifunctional memory cells
US10276576B2 (en) 2017-07-05 2019-04-30 Micron Technology, Inc. Gated diode memory cells
KR102078626B1 (ko) 2019-08-16 2020-02-18 정현욱 한글 학습 방법 및 그 장치

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5739579A (en) * 1992-06-29 1998-04-14 Intel Corporation Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections
JPH0653237A (ja) * 1992-07-31 1994-02-25 Oki Electric Ind Co Ltd 半導体素子の製造方法
US5804846A (en) * 1996-05-28 1998-09-08 Harris Corporation Process for forming a self-aligned raised source/drain MOS device and device therefrom
US5714398A (en) * 1996-07-16 1998-02-03 National Science Council Of Republic Of China Self-aligned tungsten strapped source/drain and gate technology for deep submicron CMOS
US6063675A (en) * 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US5856225A (en) 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
JP3523093B2 (ja) * 1997-11-28 2004-04-26 株式会社東芝 半導体装置およびその製造方法
US6127232A (en) * 1997-12-30 2000-10-03 Texas Instruments Incorporated Disposable gate/replacement gate MOSFETS for sub-0.1 micron gate length and ultra-shallow junctions
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
US6177303B1 (en) * 1998-09-28 2001-01-23 U.S. Philips Corporation Method of manufacturing a semiconductor device with a field effect transistor
US6225173B1 (en) * 1998-11-06 2001-05-01 Advanced Micro Devices, Inc. Recessed channel structure for manufacturing shallow source/drain extensions
US6200865B1 (en) * 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6245618B1 (en) * 1999-02-03 2001-06-12 Advanced Micro Devices, Inc. Mosfet with localized amorphous region with retrograde implantation
US6281559B1 (en) * 1999-03-03 2001-08-28 Advanced Micro Devices, Inc. Gate stack structure for variable threshold voltage
US6232164B1 (en) * 1999-05-24 2001-05-15 Taiwan Semiconductor Manufacturing Company Process of making CMOS device structure having an anti-SCE block implant
DE19940758A1 (de) * 1999-08-27 2001-03-15 Infineon Technologies Ag Verfahren zur Herstellung eines HF-FET und HF-FET
US6146955A (en) * 1999-11-12 2000-11-14 United Microelectronics Corp. Method for forming dynamic random access memory device with an ultra-short channel and an ultra-shallow junction

Also Published As

Publication number Publication date
EP1157417A1 (de) 2001-11-28
TW514992B (en) 2002-12-21
US20020094647A1 (en) 2002-07-18
EP1157417B1 (de) 2010-07-07
KR100702282B1 (ko) 2007-03-30
US6406963B2 (en) 2002-06-18
US20010004542A1 (en) 2001-06-21
US6743682B2 (en) 2004-06-01
KR20010102168A (ko) 2001-11-15
WO2001045156A1 (en) 2001-06-21
JP2003517209A (ja) 2003-05-20

Similar Documents

Publication Publication Date Title
DE60044639D1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE60042254D1 (de) Verfahren zur Herstellung einer Halbleiter-Anordnung
DE60113574D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE60042787D1 (de) Verfahren zur Herstellung einer verpackten Halbleiteranordnung
DE69918636D1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE69836401D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE60143882D1 (de) Verfahren zur Herstellung einer MOS-gesteuerten Halbleiteranordnung
DE69942812D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE60307157D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE60038423D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE69926960D1 (de) Verfahren zur Herstellung einer photovoltaischen Vorrichtung
DE10080916T1 (de) Verfahren zur Herstellung einer photovoltaischen Vorrichtung
DE69730940D1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE69636338D1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE60030949D1 (de) Verfahren zur herstellung einer karte
DE60028912D1 (de) Verfahren zur Herstellung von Hableitervorrichtungen
DE69939514D1 (de) Verfahren zur herstellung einer strukturierten dünnschichtvorrichtung
DE60033847D1 (de) Vorrichtung und verfahren zur herstellung einer kohlenstoffhaltigen schicht
DE60125755D1 (de) Verfahren zur herstellung einer flexodruckplatte
DE69912376D1 (de) Verfahren zur herstellung eines halbleiterbauelements
DE69906491D1 (de) VERFAHREN ZUR HERSTELLUNG EINER SiCOI-STRUKTUR
DE60218802D1 (de) Verfahren zur Herstellung einer Vorrichtung
DE60022857D1 (de) Verfahren zur Herstellung eines Halbleiterbauelements
DE69940737D1 (de) Verfahren zur herstellung einer halbleiteranordnung
DE60044470D1 (de) Verfahren zur herstellung eines halbleiterelement