DE60127767D1 - Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten Schaltkreis - Google Patents

Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten Schaltkreis

Info

Publication number
DE60127767D1
DE60127767D1 DE60127767T DE60127767T DE60127767D1 DE 60127767 D1 DE60127767 D1 DE 60127767D1 DE 60127767 T DE60127767 T DE 60127767T DE 60127767 T DE60127767 T DE 60127767T DE 60127767 D1 DE60127767 D1 DE 60127767D1
Authority
DE
Germany
Prior art keywords
integrated circuit
interconnect structures
metallized interconnect
making metallized
making
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60127767T
Other languages
English (en)
Other versions
DE60127767T2 (de
Inventor
Alain Blosse
Sanjay Thedki
Jianmin Qiao
Yitzhak Gilboa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cypress Semiconductor Corp
Original Assignee
Cypress Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cypress Semiconductor Corp filed Critical Cypress Semiconductor Corp
Publication of DE60127767D1 publication Critical patent/DE60127767D1/de
Application granted granted Critical
Publication of DE60127767T2 publication Critical patent/DE60127767T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005—Formation and after-treatment of dielectrics
    • H01L2221/101—Forming openings in dielectrics
    • H01L2221/1015—Forming openings in dielectrics for dual damascene structures
    • H01L2221/1036—Dual damascene with different via-level and trench-level dielectrics
DE60127767T 2000-06-15 2001-06-14 Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten Schaltkreis Expired - Fee Related DE60127767T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US593967 2000-06-15
US09/593,967 US6635566B1 (en) 2000-06-15 2000-06-15 Method of making metallization and contact structures in an integrated circuit

Publications (2)

Publication Number Publication Date
DE60127767D1 true DE60127767D1 (de) 2007-05-24
DE60127767T2 DE60127767T2 (de) 2007-12-27

Family

ID=24376952

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60127767T Expired - Fee Related DE60127767T2 (de) 2000-06-15 2001-06-14 Verfahren zur Herstellung von metallisierten Verbindungsstrukturen in einem integrierten Schaltkreis

Country Status (7)

Country Link
US (2) US6635566B1 (de)
EP (1) EP1168434B1 (de)
JP (1) JP3637000B2 (de)
KR (1) KR100421154B1 (de)
DE (1) DE60127767T2 (de)
SG (1) SG99903A1 (de)
TW (1) TW580753B (de)

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JP2005508078A (ja) * 2001-10-31 2005-03-24 東京エレクトロン株式会社 高アスペクト比形態のエッチング方法
DE10201448A1 (de) * 2002-01-16 2003-07-24 Infineon Technologies Ag Durchgangskontakt und Verfahren zum Herstellen desselben
US7078334B1 (en) * 2002-06-06 2006-07-18 Cypress Semiconductor Corporation In situ hard mask approach for self-aligned contact etch
US6751125B2 (en) 2002-11-04 2004-06-15 Freescale Semiconductor, Inc. Gate voltage reduction in a memory read
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KR100478498B1 (ko) * 2003-01-30 2005-03-28 동부아남반도체 주식회사 반도체 소자의 금속 배선 형성 방법
KR100485388B1 (ko) * 2003-02-28 2005-04-27 삼성전자주식회사 트렌치 형성 방법 및 이를 이용한 반도체 장치의 제조 방법
TW200527485A (en) * 2004-01-30 2005-08-16 Semiconductor Leading Edge Tec Multilayered wiring structure, method of forming buried wiring, semiconductor device, method of manufacturing semiconductor device, semiconductor mounted device, and method of manufacturing semiconductor mounted device
KR100613392B1 (ko) * 2004-12-23 2006-08-17 동부일렉트로닉스 주식회사 자기 정렬 콘택홀 형성 방법
US7429524B2 (en) * 2005-09-14 2008-09-30 Texas Instruments Incorporated Transistor design self-aligned to contact
US20080116494A1 (en) * 2006-11-20 2008-05-22 Matthias Goldbach Method for manufacturing a semiconductor device
US7786019B2 (en) * 2006-12-18 2010-08-31 Applied Materials, Inc. Multi-step photomask etching with chlorine for uniformity control
US7858513B2 (en) * 2007-06-18 2010-12-28 Organicid, Inc. Fabrication of self-aligned via holes in polymer thin films
US7888169B2 (en) * 2007-12-26 2011-02-15 Organicid, Inc. Organic semiconductor device and method of manufacturing the same
DE102010028458A1 (de) * 2010-04-30 2011-11-03 Globalfoundries Dresden Module One Llc & Co. Kg Halbleiterbauelement mit Kontaktelementen und Metallsilizidgebieten, die in einer gemeinsamen Prozesssequenz hergestellt sind
US9048296B2 (en) 2011-02-11 2015-06-02 International Business Machines Corporation Method to fabricate copper wiring structures and structures formed thereby
US9034703B2 (en) 2012-09-13 2015-05-19 International Business Machines Corporation Self aligned contact with improved robustness
US8728927B1 (en) * 2012-12-10 2014-05-20 International Business Machines Corporation Borderless contacts for semiconductor transistors
CN104737293B (zh) * 2013-12-23 2017-05-03 伍震威 用于功率半导体装置的场板结构及其制造方法
US9478508B1 (en) * 2015-06-08 2016-10-25 Raytheon Company Microwave integrated circuit (MMIC) damascene electrical interconnect for microwave energy transmission
DE102015112135B4 (de) * 2015-07-24 2023-04-06 Kennametal Inc. Verdampferkörper mit Titanhydridbeschichtung, Verfahren zu dessen Herstellung und Verwendung
US10163797B2 (en) * 2015-10-09 2018-12-25 Taiwan Semiconductor Manufacturing Company, Ltd. Forming interlayer dielectric material by spin-on metal oxide deposition
US9704754B1 (en) * 2016-09-22 2017-07-11 International Business Machines Corporation Self-aligned spacer for cut-last transistor fabrication
US10510851B2 (en) * 2016-11-29 2019-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Low resistance contact method and structure
US10522644B1 (en) 2018-06-21 2019-12-31 Globalfoundries Inc. Different upper and lower spacers for contact
US10685869B2 (en) * 2018-10-19 2020-06-16 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and method of forming the same

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Also Published As

Publication number Publication date
KR20010113010A (ko) 2001-12-24
KR100421154B1 (ko) 2004-03-03
US20040082182A1 (en) 2004-04-29
JP2002016139A (ja) 2002-01-18
SG99903A1 (en) 2003-11-27
US6635566B1 (en) 2003-10-21
EP1168434A2 (de) 2002-01-02
TW580753B (en) 2004-03-21
DE60127767T2 (de) 2007-12-27
JP3637000B2 (ja) 2005-04-06
EP1168434B1 (de) 2007-04-11
EP1168434A3 (de) 2003-11-05

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