DE60131906D1 - Träger für integrierte schaltungen mit aussparungen - Google Patents

Träger für integrierte schaltungen mit aussparungen

Info

Publication number
DE60131906D1
DE60131906D1 DE60131906T DE60131906T DE60131906D1 DE 60131906 D1 DE60131906 D1 DE 60131906D1 DE 60131906 T DE60131906 T DE 60131906T DE 60131906 T DE60131906 T DE 60131906T DE 60131906 D1 DE60131906 D1 DE 60131906D1
Authority
DE
Germany
Prior art keywords
receiving zone
carrier
savings
integrated circuit
integrated circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60131906T
Other languages
English (en)
Inventor
Kia Silverbrook
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silverbrook Research Pty Ltd
Original Assignee
Silverbrook Research Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silverbrook Research Pty Ltd filed Critical Silverbrook Research Pty Ltd
Application granted granted Critical
Publication of DE60131906D1 publication Critical patent/DE60131906D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
DE60131906T 2000-10-20 2001-10-19 Träger für integrierte schaltungen mit aussparungen Expired - Lifetime DE60131906D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/693,707 US7221043B1 (en) 2000-10-20 2000-10-20 Integrated circuit carrier with recesses
PCT/AU2001/001330 WO2002035896A1 (en) 2000-10-20 2001-10-19 Integrated circuit carrier with recesses

Publications (1)

Publication Number Publication Date
DE60131906D1 true DE60131906D1 (de) 2008-01-24

Family

ID=24785760

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60131906T Expired - Lifetime DE60131906D1 (de) 2000-10-20 2001-10-19 Träger für integrierte schaltungen mit aussparungen

Country Status (12)

Country Link
US (4) US7221043B1 (de)
EP (1) EP1410700B1 (de)
JP (1) JP3761520B2 (de)
KR (1) KR100526330B1 (de)
CN (1) CN1235453C (de)
AT (1) ATE381249T1 (de)
AU (2) AU1025202A (de)
DE (1) DE60131906D1 (de)
IL (2) IL155466A0 (de)
SG (1) SG126771A1 (de)
WO (1) WO2002035896A1 (de)
ZA (1) ZA200303169B (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7221043B1 (en) * 2000-10-20 2007-05-22 Silverbrook Research Pty Ltd Integrated circuit carrier with recesses
US7425990B2 (en) * 2003-05-16 2008-09-16 Sony Corporation Motion correction device and method
TW201241941A (en) * 2010-10-21 2012-10-16 Sumitomo Bakelite Co A method for manufacturing an electronic equipment, and the electronic equipment obtained by using the method, as well as a method for manufacturing electronics and electronic parts, and the electronics and the electronic parts obtained using the method
US9513666B2 (en) * 2014-07-25 2016-12-06 VivaLnk, Inc. Highly compliant wearable wireless patch having stress-relief capability
CN105338727B (zh) * 2015-10-22 2018-05-25 北大方正集团有限公司 阶梯电路板的阶梯槽的制备方法以及阶梯电路板
CN105392306A (zh) * 2015-11-27 2016-03-09 北大方正集团有限公司 一种高频盲槽电路板及其加工方法
US10064275B1 (en) 2017-07-18 2018-08-28 Mellanox Technologies, Ltd. Extending the lifetime of a leadless SMT solder joint using pads comprising spring-shaped traces

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4802277A (en) * 1985-04-12 1989-02-07 Hughes Aircraft Company Method of making a chip carrier slotted array
EP0551395A4 (en) 1990-09-27 1993-08-25 E.I. Du Pont De Nemours And Company Thermal stress-relieved composite microelectronic device
US5483421A (en) * 1992-03-09 1996-01-09 International Business Machines Corporation IC chip attachment
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
JP3294740B2 (ja) 1995-07-31 2002-06-24 富士通株式会社 半導体装置
DE19540814A1 (de) 1995-11-02 1997-05-07 Vdo Schindling Platine
FR2745930B1 (fr) 1996-03-11 1998-04-10 Solaic Sa Carte a circuit integre comportant une zone desolidarisee par une rainure
US6064576A (en) 1997-01-02 2000-05-16 Texas Instruments Incorporated Interposer having a cantilevered ball connection and being electrically connected to a printed circuit board
US6121678A (en) * 1997-12-19 2000-09-19 Stmicroelectronics, Inc. Wrap-around interconnect for fine pitch ball grid array
JP3020201B2 (ja) 1998-05-27 2000-03-15 亜南半導体株式会社 ボールグリッドアレイ半導体パッケージのモールディング方法
JP2997746B2 (ja) 1998-05-27 2000-01-11 亜南半導体株式会社 印刷回路基板
JP2000012732A (ja) 1998-06-24 2000-01-14 Rohm Co Ltd Ｂｇａ型半導体装置の構造
US6050832A (en) 1998-08-07 2000-04-18 Fujitsu Limited Chip and board stress relief interposer
TW399309B (en) * 1998-09-30 2000-07-21 World Wiser Electronics Inc Cavity-down package structure with thermal via
US6341071B1 (en) 1999-03-19 2002-01-22 International Business Machines Corporation Stress relieved ball grid array package
JP2000312075A (ja) 1999-04-27 2000-11-07 Nec Corp プリント配線板への接続方法および構造
US6078505A (en) 1999-05-14 2000-06-20 Triquint Semiconductor, Inc. Circuit board assembly method
JP2001036222A (ja) 1999-07-21 2001-02-09 Fuji Photo Film Co Ltd プリント回路基板
US6524115B1 (en) * 1999-08-20 2003-02-25 3M Innovative Properties Company Compliant interconnect assembly
JP2001094228A (ja) 1999-09-22 2001-04-06 Seiko Epson Corp 半導体装置の実装構造
US6775906B1 (en) * 2000-10-20 2004-08-17 Silverbrook Research Pty Ltd Method of manufacturing an integrated circuit carrier
US6710457B1 (en) * 2000-10-20 2004-03-23 Silverbrook Research Pty Ltd Integrated circuit carrier
US7221043B1 (en) * 2000-10-20 2007-05-22 Silverbrook Research Pty Ltd Integrated circuit carrier with recesses
US7443010B2 (en) * 2001-04-05 2008-10-28 Taiwan Semiconductor Manufacturing Co., Ltd. Matrix form semiconductor package substrate having an electrode of serpentine shape
US7114961B2 (en) * 2003-04-11 2006-10-03 Neoconix, Inc. Electrical connector on a flexible carrier
US6890185B1 (en) * 2003-11-03 2005-05-10 Kulicke & Soffa Interconnect, Inc. Multipath interconnect with meandering contact cantilevers

Also Published As

Publication number Publication date
AU2002210252B2 (en) 2004-12-09
US7221043B1 (en) 2007-05-22
AU1025202A (en) 2002-05-06
EP1410700A1 (de) 2004-04-21
CN1471804A (zh) 2004-01-28
US20110226520A1 (en) 2011-09-22
IL155466A0 (en) 2003-11-23
US7402896B2 (en) 2008-07-22
WO2002035896A1 (en) 2002-05-02
ATE381249T1 (de) 2007-12-15
EP1410700A4 (de) 2006-05-03
KR20030082931A (ko) 2003-10-23
EP1410700B1 (de) 2007-12-12
JP3761520B2 (ja) 2006-03-29
JP2004511922A (ja) 2004-04-15
US20070284725A1 (en) 2007-12-13
SG126771A1 (en) 2006-11-29
KR100526330B1 (ko) 2005-11-08
ZA200303169B (en) 2003-11-05
US20080247144A1 (en) 2008-10-09
IL155466A (en) 2010-05-31
US7974102B2 (en) 2011-07-05
CN1235453C (zh) 2006-01-04

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Legal Events

Date Code Title Description
8332 No legal effect for de