DE60132829D1 - Halbleiterspeicheranordnung und Datenverarbeitungseinheit - Google Patents
Halbleiterspeicheranordnung und DatenverarbeitungseinheitInfo
- Publication number
- DE60132829D1 DE60132829D1 DE60132829T DE60132829T DE60132829D1 DE 60132829 D1 DE60132829 D1 DE 60132829D1 DE 60132829 T DE60132829 T DE 60132829T DE 60132829 T DE60132829 T DE 60132829T DE 60132829 D1 DE60132829 D1 DE 60132829D1
- Authority
- DE
- Germany
- Prior art keywords
- processing unit
- data processing
- memory device
- semiconductor memory
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1042—Read-write modes for single port memories, i.e. having either a random port or a serial port using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/229—Timing of a write operation
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001045545A JP4651206B2 (ja) | 2001-02-21 | 2001-02-21 | 半導体記憶装置および情報処理装置 |
| JP2001045545 | 2001-02-21 | ||
| JP2001048653 | 2001-02-23 | ||
| JP2001048653A JP5226161B2 (ja) | 2001-02-23 | 2001-02-23 | 半導体記憶装置および情報処理システム |
| JP2001054567A JP4772975B2 (ja) | 2001-02-28 | 2001-02-28 | 半導体記憶装置 |
| JP2001054567 | 2001-02-28 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| DE60132829D1 true DE60132829D1 (de) | 2008-03-27 |
| DE60132829T2 DE60132829T2 (de) | 2009-02-12 |
Family
ID=27346055
Family Applications (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60116975T Expired - Lifetime DE60116975T2 (de) | 2001-02-21 | 2001-11-29 | Halbleiterspeicheranordnung und Datenverarbeitungseinheit |
| DE60122025T Expired - Lifetime DE60122025T2 (de) | 2001-02-21 | 2001-11-29 | Halbleiterspeicheranordnung und Datenverarbeitungseinheit |
| DE60132829T Expired - Lifetime DE60132829T2 (de) | 2001-02-21 | 2001-11-29 | Halbleiterspeicheranordnung und Datenverarbeitungseinheit |
Family Applications Before (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE60116975T Expired - Lifetime DE60116975T2 (de) | 2001-02-21 | 2001-11-29 | Halbleiterspeicheranordnung und Datenverarbeitungseinheit |
| DE60122025T Expired - Lifetime DE60122025T2 (de) | 2001-02-21 | 2001-11-29 | Halbleiterspeicheranordnung und Datenverarbeitungseinheit |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6545942B2 (de) |
| EP (3) | EP1235155B1 (de) |
| KR (1) | KR100708558B1 (de) |
| CN (2) | CN100536022C (de) |
| DE (3) | DE60116975T2 (de) |
| TW (1) | TWI231903B (de) |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4078119B2 (ja) * | 2002-04-15 | 2008-04-23 | 富士通株式会社 | 半導体メモリ |
| JP2004246525A (ja) * | 2003-02-13 | 2004-09-02 | Matsushita Electric Ind Co Ltd | 順序回路、記憶素子、クロック発生回路およびクロック制御方法、ならびに回路変更方法および回路設計支援装置、半導体集積回路およびそれを備えた電子装置、ならびに電子制御装置およびそれを備えた移動体 |
| US7191162B2 (en) * | 2003-10-21 | 2007-03-13 | Texas Instruments Incorporated | FIFO interface for flag-initiated DMA frame synchro-burst operation |
| KR100809690B1 (ko) * | 2006-07-14 | 2008-03-07 | 삼성전자주식회사 | 저속 테스트 동작이 가능한 반도체 메모리 장치 및 반도체메모리 장치의 테스트 방법 |
| TWI425354B (zh) | 2007-10-16 | 2014-02-01 | Mstar Semiconductor Inc | 資料存取系統及方法 |
| CN101419599B (zh) * | 2007-10-25 | 2013-03-13 | 晨星半导体股份有限公司 | 数据存取系统与方法 |
| KR101507122B1 (ko) | 2008-04-29 | 2015-04-01 | 삼성전자주식회사 | 반도체 메모리 장치 및 그것의 액세스 방법 |
| WO2010065290A2 (en) * | 2008-12-03 | 2010-06-10 | Rambus Inc. | Memory system with command filtering |
| US20100274933A1 (en) * | 2009-04-24 | 2010-10-28 | Mediatek Inc. | Method and apparatus for reducing memory size and bandwidth |
| CN102486757B (zh) * | 2010-12-06 | 2016-09-28 | 群联电子股份有限公司 | 存储器储存装置及其存储器控制器与回应主机指令的方法 |
| KR20130046122A (ko) * | 2011-10-27 | 2013-05-07 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 및 그 동작 방법 |
| CN104281416B (zh) * | 2014-10-17 | 2017-09-01 | 北京海思敏医疗技术有限公司 | 数据采集、读取方法及装置 |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0122099B1 (ko) * | 1994-03-03 | 1997-11-26 | 김광호 | 라이트레이턴시제어기능을 가진 동기식 반도체메모리장치 |
| WO1997002571A1 (en) * | 1995-06-30 | 1997-01-23 | Micron Technologies, Inc. | Distributed write data drivers for burst memories |
| JP2817679B2 (ja) * | 1995-09-20 | 1998-10-30 | 日本電気株式会社 | 半導体メモリ |
| US5587961A (en) * | 1996-02-16 | 1996-12-24 | Micron Technology, Inc. | Synchronous memory allowing early read command in write to read transitions |
| JP3238076B2 (ja) * | 1996-08-30 | 2001-12-10 | 株式会社東芝 | カウンタ回路及びこのカウンタ回路を備えた半導体記憶装置 |
| US5901304A (en) * | 1997-03-13 | 1999-05-04 | International Business Machines Corporation | Emulating quasi-synchronous DRAM with asynchronous DRAM |
| US6172935B1 (en) * | 1997-04-25 | 2001-01-09 | Micron Technology, Inc. | Synchronous dynamic random access memory device |
| US6192002B1 (en) * | 1998-08-28 | 2001-02-20 | Micron Technology | Memory device with command buffer |
| JP2000148580A (ja) * | 1998-11-09 | 2000-05-30 | Nec Corp | 半導体記憶装置 |
| JP3957421B2 (ja) | 1999-02-10 | 2007-08-15 | エルピーダメモリ株式会社 | 半導体記憶装置 |
| EP1073064A1 (de) * | 1999-07-30 | 2001-01-31 | STMicroelectronics S.r.l. | Nichtflüchtiger Speicher mit die funktioneller Fähigkeit von Inhaltsveränderung und gleichzeitig Burst- oder Seitenmoduslesung |
| JP3416083B2 (ja) * | 1999-08-31 | 2003-06-16 | 株式会社日立製作所 | 半導体装置 |
-
2001
- 2001-11-09 US US09/986,582 patent/US6545942B2/en not_active Expired - Lifetime
- 2001-11-14 TW TW090128230A patent/TWI231903B/zh not_active IP Right Cessation
- 2001-11-29 DE DE60116975T patent/DE60116975T2/de not_active Expired - Lifetime
- 2001-11-29 EP EP01310000A patent/EP1235155B1/de not_active Expired - Lifetime
- 2001-11-29 EP EP04021600A patent/EP1486878B1/de not_active Expired - Lifetime
- 2001-11-29 EP EP04021599A patent/EP1486877B1/de not_active Expired - Lifetime
- 2001-11-29 DE DE60122025T patent/DE60122025T2/de not_active Expired - Lifetime
- 2001-11-29 DE DE60132829T patent/DE60132829T2/de not_active Expired - Lifetime
- 2001-11-30 CN CNB2004100325531A patent/CN100536022C/zh not_active Expired - Fee Related
- 2001-11-30 CN CNB011425415A patent/CN1202483C/zh not_active Expired - Fee Related
- 2001-11-30 KR KR1020010075293A patent/KR100708558B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| US20020114210A1 (en) | 2002-08-22 |
| CN1372202A (zh) | 2002-10-02 |
| EP1486877B1 (de) | 2006-08-02 |
| DE60116975D1 (de) | 2006-04-13 |
| EP1235155A2 (de) | 2002-08-28 |
| EP1235155A3 (de) | 2003-11-05 |
| DE60132829T2 (de) | 2009-02-12 |
| EP1486878B1 (de) | 2008-02-13 |
| EP1486877A2 (de) | 2004-12-15 |
| US6545942B2 (en) | 2003-04-08 |
| KR100708558B1 (ko) | 2007-04-19 |
| EP1486877A3 (de) | 2005-09-21 |
| KR20020068454A (ko) | 2002-08-27 |
| EP1486878A3 (de) | 2005-09-21 |
| DE60122025D1 (de) | 2006-09-14 |
| DE60122025T2 (de) | 2006-11-23 |
| CN1530961A (zh) | 2004-09-22 |
| CN1202483C (zh) | 2005-05-18 |
| EP1235155B1 (de) | 2006-02-01 |
| EP1486878A2 (de) | 2004-12-15 |
| CN100536022C (zh) | 2009-09-02 |
| DE60116975T2 (de) | 2006-07-27 |
| TWI231903B (en) | 2005-05-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 8364 | No opposition during term of opposition | ||
| 8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU MICROELECTRONICS LTD., TOKYO, JP |
|
| 8327 | Change in the person/name/address of the patent owner |
Owner name: FUJITSU SEMICONDUCTOR LTD., YOKOHAMA, KANAGAWA, JP |
|
| 8328 | Change in the person/name/address of the agent |
Representative=s name: SEEGER SEEGER LINDNER PARTNERSCHAFT PATENTANWAELTE |