DE60133214D1 - Gateherstellungsprozess für den dram-bereich und logikbauteile auf demselben chip - Google Patents

Gateherstellungsprozess für den dram-bereich und logikbauteile auf demselben chip

Info

Publication number
DE60133214D1
DE60133214D1 DE60133214T DE60133214T DE60133214D1 DE 60133214 D1 DE60133214 D1 DE 60133214D1 DE 60133214 T DE60133214 T DE 60133214T DE 60133214 T DE60133214 T DE 60133214T DE 60133214 D1 DE60133214 D1 DE 60133214D1
Authority
DE
Germany
Prior art keywords
manufacturing process
same chip
logic components
dram area
gate manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE60133214T
Other languages
English (en)
Other versions
DE60133214T2 (de
Inventor
Ramachandra Divakaruni
Mary E Weybright
Peter Hoh
Gary Bronner
Richard A Conti
Uwe Schroeder
Jeffrey Peter Gambino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qimonda AG
International Business Machines Corp
Original Assignee
International Business Machines Corp
Infineon Technologies North America Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp, Infineon Technologies North America Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE60133214D1 publication Critical patent/DE60133214D1/de
Publication of DE60133214T2 publication Critical patent/DE60133214T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
DE60133214T 2000-11-15 2001-11-13 Gateherstellungsprozess für den dram-bereich und logikbauteile auf demselben chip Expired - Fee Related DE60133214T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US713272 2000-11-15
US09/713,272 US6403423B1 (en) 2000-11-15 2000-11-15 Modified gate processing for optimized definition of array and logic devices on same chip
PCT/US2001/051214 WO2002045134A2 (en) 2000-11-15 2001-11-13 Gate process for dram array and logic devices on same chip

Publications (2)

Publication Number Publication Date
DE60133214D1 true DE60133214D1 (de) 2008-04-24
DE60133214T2 DE60133214T2 (de) 2009-04-23

Family

ID=24865486

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60133214T Expired - Fee Related DE60133214T2 (de) 2000-11-15 2001-11-13 Gateherstellungsprozess für den dram-bereich und logikbauteile auf demselben chip

Country Status (5)

Country Link
US (2) US6403423B1 (de)
EP (1) EP1334517B1 (de)
KR (1) KR100533511B1 (de)
DE (1) DE60133214T2 (de)
WO (1) WO2002045134A2 (de)

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DE10208728B4 (de) * 2002-02-28 2009-05-07 Advanced Micro Devices, Inc., Sunnyvale Ein Verfahren zur Herstellung eines Halbleiterelements mit unterschiedlichen Metallsilizidbereichen
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DE10214065B4 (de) * 2002-03-28 2006-07-06 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines verbesserten Metallsilizidbereichs in einem Silizium enthaltenden leitenden Gebiet in einer integrierten Schaltung
DE10234931A1 (de) * 2002-07-31 2004-02-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Herstellung eines Metallsilizidgates in einer standardmässigen MOS-Prozesssequenz
US6869862B2 (en) * 2002-08-09 2005-03-22 Texas Instruments Incorporated Method for improving a physical property defect value of a gate dielectric
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DE10250872B4 (de) * 2002-10-31 2005-04-21 Infineon Technologies Ag Verfahren zur Herstellung einer Halbleiterstruktur mit mehreren Gate-Stapeln
US6815235B1 (en) 2002-11-25 2004-11-09 Advanced Micro Devices, Inc. Methods of controlling formation of metal silicide regions, and system for performing same
US6927135B2 (en) * 2002-12-18 2005-08-09 Micron Technology, Inc. Methods of fabricating multiple sets of field effect transistors
US6734089B1 (en) * 2003-01-16 2004-05-11 Micron Technology Inc Techniques for improving wordline fabrication of a memory device
US6828181B2 (en) * 2003-05-08 2004-12-07 International Business Machines Corporation Dual gate material process for CMOS technologies
KR100560941B1 (ko) * 2004-01-09 2006-03-14 매그나칩 반도체 유한회사 고전압 소자의 금속 배선 형성 방법
US7030431B2 (en) * 2004-03-19 2006-04-18 Nanya Technology Corp. Metal gate with composite film stack
US6893927B1 (en) * 2004-03-22 2005-05-17 Intel Corporation Method for making a semiconductor device with a metal gate electrode
JP2005327848A (ja) * 2004-05-13 2005-11-24 Toshiba Corp 半導体装置及びその製造方法
US7074666B2 (en) * 2004-07-28 2006-07-11 International Business Machines Corporation Borderless contact structures
US7485910B2 (en) * 2005-04-08 2009-02-03 International Business Machines Corporation Simplified vertical array device DRAM/eDRAM integration: method and structure
US7462534B2 (en) * 2005-08-02 2008-12-09 Micron Technology, Inc. Methods of forming memory circuitry
US20070200149A1 (en) * 2006-02-28 2007-08-30 Veronika Polei Semiconductor device and method of production
JP4921837B2 (ja) * 2006-04-14 2012-04-25 株式会社東芝 半導体装置の製造方法
US7858514B2 (en) * 2007-06-29 2010-12-28 Qimonda Ag Integrated circuit, intermediate structure and a method of fabricating a semiconductor structure
US7691751B2 (en) * 2007-10-26 2010-04-06 Spansion Llc Selective silicide formation using resist etchback
US20090159947A1 (en) * 2007-12-19 2009-06-25 International Business Machines Corporation SIMPLIFIED VERTICAL ARRAY DEVICE DRAM/eDRAM INTEGRATION
US7989307B2 (en) * 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
KR20100076256A (ko) * 2008-12-26 2010-07-06 주식회사 동부하이텍 Ｐｉｐ 커패시터의 제조 방법
US8530971B2 (en) * 2009-11-12 2013-09-10 International Business Machines Corporation Borderless contacts for semiconductor devices
US8907405B2 (en) 2011-04-18 2014-12-09 International Business Machines Corporation Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures
US9620619B2 (en) 2012-01-12 2017-04-11 Globalfoundries Inc. Borderless contact structure
US8927387B2 (en) 2012-04-09 2015-01-06 International Business Machines Corporation Robust isolation for thin-box ETSOI MOSFETS
TWI567785B (zh) * 2013-03-27 2017-01-21 聯華電子股份有限公司 半導體裝置圖案化結構之製作方法
JP6193695B2 (ja) * 2013-09-13 2017-09-06 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
KR102374052B1 (ko) 2016-02-26 2022-03-14 삼성전자주식회사 반도체 소자 및 그 제조 방법
CN113921386A (zh) * 2020-07-10 2022-01-11 长鑫存储技术有限公司 半导体器件及其制备方法

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JP3149937B2 (ja) 1997-12-08 2001-03-26 日本電気株式会社 半導体装置およびその製造方法
US5998252A (en) * 1997-12-29 1999-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Method of salicide and sac (self-aligned contact) integration
US6015730A (en) * 1998-03-05 2000-01-18 Taiwan Semiconductor Manufacturing Company Integration of SAC and salicide processes by combining hard mask and poly definition
US6037222A (en) * 1998-05-22 2000-03-14 Taiwan Semiconductor Manufacturing Company Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology
JP3869128B2 (ja) * 1998-09-11 2007-01-17 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
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Also Published As

Publication number Publication date
EP1334517A2 (de) 2003-08-13
US6403423B1 (en) 2002-06-11
DE60133214T2 (de) 2009-04-23
US20020111025A1 (en) 2002-08-15
KR20030060933A (ko) 2003-07-16
WO2002045134A3 (en) 2003-04-03
EP1334517B1 (de) 2008-03-12
KR100533511B1 (ko) 2005-12-06
US6548357B2 (en) 2003-04-15
WO2002045134A2 (en) 2002-06-06

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Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: INTERNATIONAL BUSINESS MACHINES CORP., ARMONK,, US

Owner name: QIMONDA AG, 81739 MUENCHEN, DE

8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee