DE602004008067D1 - Speichermodularchitektur-reigentopologie, detektionen und meldungen, präsenz eines äusseren speichermoduls zu innerem modul - Google Patents

Speichermodularchitektur-reigentopologie, detektionen und meldungen, präsenz eines äusseren speichermoduls zu innerem modul

Info

Publication number
DE602004008067D1
DE602004008067D1 DE602004008067T DE602004008067T DE602004008067D1 DE 602004008067 D1 DE602004008067 D1 DE 602004008067D1 DE 602004008067 T DE602004008067 T DE 602004008067T DE 602004008067 T DE602004008067 T DE 602004008067T DE 602004008067 D1 DE602004008067 D1 DE 602004008067D1
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DE
Germany
Prior art keywords
memory module
module
reigent
detections
topology
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004008067T
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English (en)
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DE602004008067T2 (de
Inventor
Pete Vogt
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE602004008067D1 publication Critical patent/DE602004008067D1/de
Application granted granted Critical
Publication of DE602004008067T2 publication Critical patent/DE602004008067T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System (AREA)
  • Multi Processors (AREA)
  • Dram (AREA)
  • Debugging And Monitoring (AREA)
  • Electronic Switches (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Information Transfer Systems (AREA)
DE602004008067T 2003-06-03 2004-05-20 Speichermodularchitektur-reigentopologie, detektionen und meldungen, präsenz eines äusseren speichermoduls zu innerem modul Active DE602004008067T2 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/454,399 US7194581B2 (en) 2003-06-03 2003-06-03 Memory channel with hot add/remove
US454399 2003-06-03
PCT/US2004/015978 WO2004109525A2 (en) 2003-06-03 2004-05-20 Memory module architecture daisy chain topology detects and reports presence of outer memory module to inner module

Publications (2)

Publication Number Publication Date
DE602004008067D1 true DE602004008067D1 (de) 2007-09-20
DE602004008067T2 DE602004008067T2 (de) 2007-11-22

Family

ID=33489727

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004008067T Active DE602004008067T2 (de) 2003-06-03 2004-05-20 Speichermodularchitektur-reigentopologie, detektionen und meldungen, präsenz eines äusseren speichermoduls zu innerem modul

Country Status (9)

Country Link
US (1) US7194581B2 (de)
EP (1) EP1629392B1 (de)
JP (1) JP4210300B2 (de)
KR (1) KR100806445B1 (de)
CN (1) CN100483380C (de)
AT (1) ATE369589T1 (de)
DE (1) DE602004008067T2 (de)
TW (1) TW200502732A (de)
WO (1) WO2004109525A2 (de)

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Also Published As

Publication number Publication date
EP1629392B1 (de) 2007-08-08
DE602004008067T2 (de) 2007-11-22
EP1629392A2 (de) 2006-03-01
US7194581B2 (en) 2007-03-20
WO2004109525A2 (en) 2004-12-16
CN100483380C (zh) 2009-04-29
CN1799040A (zh) 2006-07-05
TW200502732A (en) 2005-01-16
ATE369589T1 (de) 2007-08-15
KR20060023983A (ko) 2006-03-15
JP2006526846A (ja) 2006-11-24
JP4210300B2 (ja) 2009-01-14
US20040250024A1 (en) 2004-12-09
KR100806445B1 (ko) 2008-02-21
WO2004109525A3 (en) 2005-01-27

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