DE602004012106D1 - Multikanal-DMA mit gemeinsamem FIFO-Puffer - Google Patents

Multikanal-DMA mit gemeinsamem FIFO-Puffer

Info

Publication number
DE602004012106D1
DE602004012106D1 DE602004012106T DE602004012106T DE602004012106D1 DE 602004012106 D1 DE602004012106 D1 DE 602004012106D1 DE 602004012106 T DE602004012106 T DE 602004012106T DE 602004012106 T DE602004012106 T DE 602004012106T DE 602004012106 D1 DE602004012106 D1 DE 602004012106D1
Authority
DE
Germany
Prior art keywords
fifo buffer
channel dma
shared fifo
shared
dma
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004012106T
Other languages
English (en)
Other versions
DE602004012106T2 (de
Inventor
Franck Seigneret
Sivayya Ayinala
Nabil Khalifa
Praveen Kolli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments France SAS
Texas Instruments Inc
Original Assignee
Texas Instruments France SAS
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments France SAS, Texas Instruments Inc filed Critical Texas Instruments France SAS
Publication of DE602004012106D1 publication Critical patent/DE602004012106D1/de
Application granted granted Critical
Publication of DE602004012106T2 publication Critical patent/DE602004012106T2/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
DE602004012106T 2004-10-11 2004-10-11 Multikanal-DMA mit gemeinsamem FIFO-Puffer Active DE602004012106T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP04292404A EP1645967B1 (de) 2004-10-11 2004-10-11 Multikanal-DMA mit gemeinsamem FIFO-Puffer

Publications (2)

Publication Number Publication Date
DE602004012106D1 true DE602004012106D1 (de) 2008-04-10
DE602004012106T2 DE602004012106T2 (de) 2009-02-19

Family

ID=34931444

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004012106T Active DE602004012106T2 (de) 2004-10-11 2004-10-11 Multikanal-DMA mit gemeinsamem FIFO-Puffer

Country Status (3)

Country Link
US (1) US7373437B2 (de)
EP (1) EP1645967B1 (de)
DE (1) DE602004012106T2 (de)

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US20090024772A1 (en) * 2007-07-20 2009-01-22 Wenjeng Ko Overlayed separate dma mapping of adapters
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US10445267B2 (en) * 2016-06-29 2019-10-15 Nxp Usa, Inc. Direct memory access (DMA) unit with address alignment
CN108959107B (zh) 2017-05-18 2020-06-16 深圳市中兴微电子技术有限公司 一种共享方法及装置
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CN112948322B (zh) * 2021-02-26 2023-05-16 西安微电子技术研究所 一种基于弹性缓存的虚通道及实现方法
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US20050223131A1 (en) * 2004-04-02 2005-10-06 Goekjian Kenneth S Context-based direct memory access engine for use with a memory system shared by devices associated with multiple input and output ports

Also Published As

Publication number Publication date
US20060080477A1 (en) 2006-04-13
US7373437B2 (en) 2008-05-13
EP1645967B1 (de) 2008-02-27
DE602004012106T2 (de) 2009-02-19
EP1645967A1 (de) 2006-04-12

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