DE602004015813D1 - Speichervorrichtung und verfahren zur löschung derselben - Google Patents

Speichervorrichtung und verfahren zur löschung derselben

Info

Publication number
DE602004015813D1
DE602004015813D1 DE602004015813T DE602004015813T DE602004015813D1 DE 602004015813 D1 DE602004015813 D1 DE 602004015813D1 DE 602004015813 T DE602004015813 T DE 602004015813T DE 602004015813 T DE602004015813 T DE 602004015813T DE 602004015813 D1 DE602004015813 D1 DE 602004015813D1
Authority
DE
Germany
Prior art keywords
erasing
same
memory device
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
DE602004015813T
Other languages
English (en)
Inventor
Wei Zheng
Yun Wayne Wu
Hidehiko Shiraiwa
Mark T Ramsbey
Tazrien Kamal
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Spansion LLC
Original Assignee
Spansion LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Spansion LLC filed Critical Spansion LLC
Publication of DE602004015813D1 publication Critical patent/DE602004015813D1/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H01L29/7923Programmable transistors with more than two possible different levels of programmation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7887Programmable transistors with more than two possible different levels of programmation
DE602004015813T 2003-09-09 2004-05-21 Speichervorrichtung und verfahren zur löschung derselben Active DE602004015813D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/658,506 US6912163B2 (en) 2003-01-14 2003-09-09 Memory device having high work function gate and method of erasing same
PCT/US2004/016071 WO2005027227A1 (en) 2003-09-09 2004-05-21 Memory device and method of erasing the same

Publications (1)

Publication Number Publication Date
DE602004015813D1 true DE602004015813D1 (de) 2008-09-25

Family

ID=34312687

Family Applications (1)

Application Number Title Priority Date Filing Date
DE602004015813T Active DE602004015813D1 (de) 2003-09-09 2004-05-21 Speichervorrichtung und verfahren zur löschung derselben

Country Status (5)

Country Link
US (1) US6912163B2 (de)
EP (1) EP1665387B1 (de)
DE (1) DE602004015813D1 (de)
TW (1) TWI337354B (de)
WO (1) WO2005027227A1 (de)

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050012143A1 (en) * 2003-06-24 2005-01-20 Hideaki Tanaka Semiconductor device and method of manufacturing the same
KR100721547B1 (ko) * 2003-12-29 2007-05-23 주식회사 하이닉스반도체 고속으로 데이터 엑세스를 하기 위한 반도체 메모리 장치
US7151692B2 (en) * 2004-01-27 2006-12-19 Macronix International Co., Ltd. Operation scheme for programming charge trapping non-volatile memory
US7158411B2 (en) * 2004-04-01 2007-01-02 Macronix International Co., Ltd. Integrated code and data flash memory
US7209390B2 (en) * 2004-04-26 2007-04-24 Macronix International Co., Ltd. Operation scheme for spectrum shift in charge trapping non-volatile memory
US7187590B2 (en) * 2004-04-26 2007-03-06 Macronix International Co., Ltd. Method and system for self-convergent erase in charge trapping memory cells
US7133313B2 (en) * 2004-04-26 2006-11-07 Macronix International Co., Ltd. Operation scheme with charge balancing for charge trapping non-volatile memory
US7075828B2 (en) * 2004-04-26 2006-07-11 Macronix International Co., Intl. Operation scheme with charge balancing erase for charge trapping non-volatile memory
US7164603B2 (en) * 2004-04-26 2007-01-16 Yen-Hao Shih Operation scheme with high work function gate and charge balancing for charge trapping non-volatile memory
US7133316B2 (en) * 2004-06-02 2006-11-07 Macronix International Co., Ltd. Program/erase method for P-channel charge trapping memory device
US7190614B2 (en) * 2004-06-17 2007-03-13 Macronix International Co., Ltd. Operation scheme for programming charge trapping non-volatile memory
US7274601B2 (en) * 2004-09-27 2007-09-25 Macronix International Co., Ltd. Programming and erasing method for charge-trapping memory devices
US20060007732A1 (en) * 2004-07-06 2006-01-12 Macronix International Co., Ltd. Charge trapping non-volatile memory and method for operating same
US7106625B2 (en) * 2004-07-06 2006-09-12 Macronix International Co, Td Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same
KR100665186B1 (ko) * 2004-08-14 2007-01-09 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조 방법
US7133317B2 (en) * 2004-11-19 2006-11-07 Macronix International Co., Ltd. Method and apparatus for programming nonvolatile memory
US20060113586A1 (en) * 2004-11-29 2006-06-01 Macronix International Co., Ltd. Charge trapping dielectric structure for non-volatile memory
KR100699830B1 (ko) * 2004-12-16 2007-03-27 삼성전자주식회사 이레이즈 효율을 개선하는 비휘발성 메모리 소자 및 제조방법
US7473589B2 (en) 2005-12-09 2009-01-06 Macronix International Co., Ltd. Stacked thin film transistor, non-volatile memory devices and methods for fabricating the same
US8264028B2 (en) * 2005-01-03 2012-09-11 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US7642585B2 (en) * 2005-01-03 2010-01-05 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US20060198189A1 (en) * 2005-01-03 2006-09-07 Macronix International Co., Ltd. Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
US7709334B2 (en) * 2005-12-09 2010-05-04 Macronix International Co., Ltd. Stacked non-volatile memory device and methods for fabricating the same
US8482052B2 (en) 2005-01-03 2013-07-09 Macronix International Co., Ltd. Silicon on insulator and thin film transistor bandgap engineered split gate memory
US7315474B2 (en) 2005-01-03 2008-01-01 Macronix International Co., Ltd Non-volatile memory cells, memory arrays including the same and methods of operating cells and arrays
DE102005008321B4 (de) * 2005-02-23 2008-09-25 Qimonda Ag Mittels Feldeffekt steuerbares Halbleiterspeicherelement mit verbessertem Einfangdielektrikum
US7158420B2 (en) * 2005-04-29 2007-01-02 Macronix International Co., Ltd. Inversion bit line, charge trapping non-volatile memory and method of operating same
US7636257B2 (en) * 2005-06-10 2009-12-22 Macronix International Co., Ltd. Methods of operating p-channel non-volatile memory devices
US7763927B2 (en) * 2005-12-15 2010-07-27 Macronix International Co., Ltd. Non-volatile memory device having a nitride-oxide dielectric layer
US7576386B2 (en) * 2005-08-04 2009-08-18 Macronix International Co., Ltd. Non-volatile memory semiconductor device having an oxide-nitride-oxide (ONO) top dielectric layer
US7881123B2 (en) * 2005-09-23 2011-02-01 Macronix International Co., Ltd. Multi-operation mode nonvolatile memory
US7462907B1 (en) * 2005-11-07 2008-12-09 Spansion Llc Method of increasing erase speed in memory arrays
US7391652B2 (en) * 2006-05-05 2008-06-24 Macronix International Co., Ltd. Method of programming and erasing a p-channel BE-SONOS NAND flash memory
US7907450B2 (en) * 2006-05-08 2011-03-15 Macronix International Co., Ltd. Methods and apparatus for implementing bit-by-bit erase of a flash memory device
US7948799B2 (en) 2006-05-23 2011-05-24 Macronix International Co., Ltd. Structure and method of sub-gate NAND memory with bandgap engineered SONOS devices
US7414889B2 (en) * 2006-05-23 2008-08-19 Macronix International Co., Ltd. Structure and method of sub-gate and architectures employing bandgap engineered SONOS devices
TWI300931B (en) * 2006-06-20 2008-09-11 Macronix Int Co Ltd Method of operating non-volatile memory device
US7471568B2 (en) * 2006-06-21 2008-12-30 Macronix International Co., Ltd. Multi-level cell memory structures with enlarged second bit operation window
US7746694B2 (en) * 2006-07-10 2010-06-29 Macronix International Co., Ltd. Nonvolatile memory array having modified channel region interface
US7772068B2 (en) 2006-08-30 2010-08-10 Macronix International Co., Ltd. Method of manufacturing non-volatile memory
US8772858B2 (en) 2006-10-11 2014-07-08 Macronix International Co., Ltd. Vertical channel memory and manufacturing method thereof and operating method using the same
US7811890B2 (en) * 2006-10-11 2010-10-12 Macronix International Co., Ltd. Vertical channel transistor structure and manufacturing method thereof
US7851848B2 (en) 2006-11-01 2010-12-14 Macronix International Co., Ltd. Cylindrical channel charge trapping devices with effectively high coupling ratios
US8101989B2 (en) 2006-11-20 2012-01-24 Macronix International Co., Ltd. Charge trapping devices with field distribution layer over tunneling barrier
US8223540B2 (en) * 2007-02-02 2012-07-17 Macronix International Co., Ltd. Method and apparatus for double-sided biasing of nonvolatile memory
US8940645B2 (en) 2007-05-25 2015-01-27 Cypress Semiconductor Corporation Radical oxidation process for fabricating a nonvolatile charge trap memory device
US8063434B1 (en) 2007-05-25 2011-11-22 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US20090179253A1 (en) 2007-05-25 2009-07-16 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US9449831B2 (en) 2007-05-25 2016-09-20 Cypress Semiconductor Corporation Oxide-nitride-oxide stack having multiple oxynitride layers
US8633537B2 (en) 2007-05-25 2014-01-21 Cypress Semiconductor Corporation Memory transistor with multiple charge storing layers and a high work function gate electrode
US7838923B2 (en) * 2007-08-09 2010-11-23 Macronix International Co., Ltd. Lateral pocket implant charge trapping devices
US20090039414A1 (en) * 2007-08-09 2009-02-12 Macronix International Co., Ltd. Charge trapping memory cell with high speed erase
EP2026384A3 (de) 2007-08-13 2009-06-10 Macronix International Co., Ltd. Ladungsabfangende Speicherzelle mit Hochgeschwindigkeitslöschung
US7816727B2 (en) 2007-08-27 2010-10-19 Macronix International Co., Ltd. High-κ capped blocking dielectric bandgap engineered SONOS and MONOS
US8320191B2 (en) 2007-08-30 2012-11-27 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device
US7643349B2 (en) * 2007-10-18 2010-01-05 Macronix International Co., Ltd. Efficient erase algorithm for SONOS-type NAND flash
US7848148B2 (en) * 2007-10-18 2010-12-07 Macronix International Co., Ltd. One-transistor cell semiconductor on insulator random access memory
US8189397B2 (en) * 2008-01-08 2012-05-29 Spansion Israel Ltd Retention in NVM with top or bottom injection
US8068370B2 (en) 2008-04-18 2011-11-29 Macronix International Co., Ltd. Floating gate memory device with interpoly charge trapping structure
US7971177B2 (en) * 2008-05-05 2011-06-28 Macronix International Co., Ltd. Design tool for charge trapping memory using simulated programming operations
US20090303794A1 (en) * 2008-06-04 2009-12-10 Macronix International Co., Ltd. Structure and Method of A Field-Enhanced Charge Trapping-DRAM
US8081516B2 (en) * 2009-01-02 2011-12-20 Macronix International Co., Ltd. Method and apparatus to suppress fringing field interference of charge trapping NAND memory
US8861273B2 (en) * 2009-04-21 2014-10-14 Macronix International Co., Ltd. Bandgap engineered charge trapping memory in two-transistor nor architecture
US8169835B2 (en) * 2009-09-28 2012-05-01 Macronix International Co., Ltd. Charge trapping memory cell having bandgap engineered tunneling structure with oxynitride isolation layer
US9548206B2 (en) 2010-02-11 2017-01-17 Cree, Inc. Ohmic contact structure for group III nitride semiconductor device having improved surface morphology and well-defined edge features
US8383443B2 (en) 2010-05-14 2013-02-26 International Business Machines Corporation Non-uniform gate dielectric charge for pixel sensor cells and methods of manufacturing
JP5156060B2 (ja) * 2010-07-29 2013-03-06 シャープ株式会社 不揮発性半導体記憶装置
GB201104261D0 (en) 2011-03-14 2011-04-27 Univ Leeds Oxide removal from semiconductor surfaces
US9240405B2 (en) 2011-04-19 2016-01-19 Macronix International Co., Ltd. Memory with off-chip controller
US9001564B2 (en) * 2011-06-29 2015-04-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and a method for driving the same
KR102072244B1 (ko) 2011-11-30 2020-01-31 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치 및 반도체 장치의 제작 방법
US8685813B2 (en) 2012-02-15 2014-04-01 Cypress Semiconductor Corporation Method of integrating a charge-trapping gate stack into a CMOS flow
US8987098B2 (en) 2012-06-19 2015-03-24 Macronix International Co., Ltd. Damascene word line
CN109585453A (zh) * 2012-07-01 2019-04-05 赛普拉斯半导体公司 具有多个电荷存储层的存储器晶体管
US9379126B2 (en) 2013-03-14 2016-06-28 Macronix International Co., Ltd. Damascene conductor for a 3D device
US9099538B2 (en) 2013-09-17 2015-08-04 Macronix International Co., Ltd. Conductor with a plurality of vertical extensions for a 3D device
US8883624B1 (en) * 2013-09-27 2014-11-11 Cypress Semiconductor Corporation Integration of a memory transistor into high-K, metal gate CMOS process flow
US9559113B2 (en) 2014-05-01 2017-01-31 Macronix International Co., Ltd. SSL/GSL gate oxide in 3D vertical channel NAND
US9391084B2 (en) 2014-06-19 2016-07-12 Macronix International Co., Ltd. Bandgap-engineered memory with multiple charge trapping layers storing charge
US10043819B1 (en) 2017-05-17 2018-08-07 Macronix International Co., Ltd. Method for manufacturing 3D NAND memory using gate replacement, and resulting structures

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110114A (ja) 1991-10-17 1993-04-30 Rohm Co Ltd 不揮発性半導体記憶素子
US5612547A (en) 1993-10-18 1997-03-18 Northrop Grumman Corporation Silicon carbide static induction transistor
JP3123924B2 (ja) 1996-06-06 2001-01-15 三洋電機株式会社 不揮発性半導体メモリ
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
DE19631146A1 (de) 1996-08-01 1998-02-05 Siemens Ag Nichtflüchtige Speicherzelle
EP0916138B1 (de) 1996-08-01 2001-09-26 Infineon Technologies AG Verfahren zum betrieb einer speicherzellenanordnung
US6768165B1 (en) * 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6232643B1 (en) * 1997-11-13 2001-05-15 Micron Technology, Inc. Memory using insulator traps
US5888867A (en) 1998-02-13 1999-03-30 Advanced Micro Devices, Inc. Non-uniform threshold voltage adjustment in flash eproms through gate work function alteration
US6122201A (en) * 1999-10-20 2000-09-19 Taiwan Semiconductor Manufacturing Company Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM
US6265268B1 (en) 1999-10-25 2001-07-24 Advanced Micro Devices, Inc. High temperature oxide deposition process for fabricating an ONO floating-gate electrode in a two bit EEPROM device
US6348420B1 (en) 1999-12-23 2002-02-19 Asm America, Inc. Situ dielectric stacks
KR20010066386A (ko) 1999-12-31 2001-07-11 박종섭 플래시 메모리의 게이트전극 제조방법
US6215702B1 (en) 2000-02-16 2001-04-10 Advanced Micro Devices, Inc. Method of maintaining constant erasing speeds for non-volatile memory cells
US6456533B1 (en) 2001-02-28 2002-09-24 Advanced Micro Devices, Inc. Higher program VT and faster programming rates based on improved erase methods
JP4282248B2 (ja) 2001-03-30 2009-06-17 株式会社東芝 半導体記憶装置
US6897522B2 (en) 2001-10-31 2005-05-24 Sandisk Corporation Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements
US6754105B1 (en) * 2003-05-06 2004-06-22 Advanced Micro Devices, Inc. Trench side wall charge trapping dielectric flash memory device

Also Published As

Publication number Publication date
EP1665387A1 (de) 2006-06-07
WO2005027227A1 (en) 2005-03-24
EP1665387B1 (de) 2008-08-13
TW200511308A (en) 2005-03-16
US20040136240A1 (en) 2004-07-15
TWI337354B (en) 2011-02-11
US6912163B2 (en) 2005-06-28

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